armv8: fsl-layerscape: Update TZASC registers type
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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@ -148,26 +148,26 @@ ENTRY(lowlevel_init)
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* placeholders.
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*/
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ldr x1, =TZASC_GATE_KEEPER(0)
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ldr x0, [x1] /* Filter 0 Gate Keeper Register */
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orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
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str x0, [x1]
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ldr w0, [x1] /* Filter 0 Gate Keeper Register */
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orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
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str w0, [x1]
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ldr x1, =TZASC_GATE_KEEPER(1)
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ldr x0, [x1] /* Filter 0 Gate Keeper Register */
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orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
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str x0, [x1]
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ldr w0, [x1] /* Filter 0 Gate Keeper Register */
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orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
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str w0, [x1]
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ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
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ldr x0, [x1] /* Region-0 Attributes Register */
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orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str x0, [x1]
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ldr w0, [x1] /* Region-0 Attributes Register */
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orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str w0, [x1]
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ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
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ldr x0, [x1] /* Region-1 Attributes Register */
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orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str x0, [x1]
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ldr w0, [x1] /* Region-1 Attributes Register */
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orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str w0, [x1]
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ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
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ldr w0, [x1] /* Region-0 Access Register */
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