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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-stm

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- fix SPL boot issue due to early dbgmcu_init() call
- fix SPL boot issue due to dcache memory region configuration
- add support of CONFIG_ENV_IS_IN_MMC
- add specific SD/eMMC partition for U-Boot enviromnent
- enable env in SPL
- use "env info -q" to remove log during boot
- remove env location override for dh_stm32mp1
- update management of misc_read
- check result of find_mmc_device in stm32prog
- use regulator_set_enable_if_allowed for disabling vdd supply in usbphyc
- enable CMD_ADTIMG flag to handle Android images
- device tree alignment with Linux Kernel v5.8-rc1
- remove hnp-srp-disable for usbotg on dk1
- add reset support to uart nodes on stm32mp15x
- use correct weak function name spl_board_prepare_for_linux
- use cd-gpios for ST and DHSOM boards
- add seeed studio odyssey-stm32mp157c board support
- move ethernet PHY into SoM DT
- add DHSOM based DRC02 board support
This commit is contained in:
Tom Rini 2020-07-29 16:30:45 -04:00
commit 7cb2060b4e
31 changed files with 1599 additions and 209 deletions
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2
arch/arm/dts/Makefile
View File

@ -942,6 +942,8 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
stm32mp157c-odyssey.dtb \
stm32mp15xx-dhcom-drc02.dtb \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcor-avenger96.dtb

564
arch/arm/dts/stm32mp15-pinctrl.dtsi
View File

@ -6,7 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
adc1_in6_pins_a: adc1-in6 {
adc1_in6_pins_a: adc1-in6-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
};
@ -21,6 +21,13 @@
};
};
adc12_ain_pins_b: adc12-ain-1 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
<STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
};
};
adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
@ -37,7 +44,7 @@
};
};
cec_pins_sleep_a: cec-sleep-0 {
cec_sleep_pins_a: cec-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
};
@ -52,19 +59,19 @@
};
};
cec_pins_sleep_b: cec-sleep-1 {
cec_sleep_pins_b: cec-sleep-1 {
pins {
pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
};
};
dac_ch1_pins_a: dac-ch1 {
dac_ch1_pins_a: dac-ch1-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
};
};
dac_ch2_pins_a: dac-ch2 {
dac_ch2_pins_a: dac-ch2-0 {
pins {
pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
};
@ -142,7 +149,7 @@
};
};
ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@ -163,6 +170,57 @@
};
ethernet0_rgmii_pins_b: rgmii-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
};
ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
};
};
ethernet0_rgmii_pins_c: rgmii-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
@ -193,7 +251,7 @@
};
};
ethernet0_rgmii_pins_sleep_b: rgmii-sleep-1 {
ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
@ -233,7 +291,7 @@
};
};
ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
@ -301,14 +359,14 @@
};
};
i2c1_pins_sleep_a: i2c1-1 {
i2c1_sleep_pins_a: i2c1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
};
};
i2c1_pins_b: i2c1-2 {
i2c1_pins_b: i2c1-1 {
pins {
pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
@ -318,7 +376,7 @@
};
};
i2c1_pins_sleep_b: i2c1-3 {
i2c1_sleep_pins_b: i2c1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
<STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
@ -335,14 +393,14 @@
};
};
i2c2_pins_sleep_a: i2c2-1 {
i2c2_sleep_pins_a: i2c2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
};
};
i2c2_pins_b1: i2c2-2 {
i2c2_pins_b1: i2c2-1 {
pins {
pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
bias-disable;
@ -351,13 +409,13 @@
};
};
i2c2_pins_sleep_b1: i2c2-3 {
i2c2_sleep_pins_b1: i2c2-sleep-1 {
pins {
pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
};
};
i2c2_pins_c: i2c2-4 {
i2c2_pins_c: i2c2-2 {
pins {
pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
@ -367,7 +425,7 @@
};
};
i2c2_pins_sleep_c: i2c2-5 {
i2c2_pins_sleep_c: i2c2-sleep-2 {
pins {
pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
<STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
@ -384,7 +442,7 @@
};
};
i2c5_pins_sleep_a: i2c5-1 {
i2c5_sleep_pins_a: i2c5-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
<STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
@ -392,6 +450,23 @@
};
};
i2c5_pins_b: i2c5-1 {
pins {
pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
<STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
i2c5_sleep_pins_b: i2c5-sleep-1 {
pins {
pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
<STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
};
};
i2s2_pins_a: i2s2-0 {
pins {
pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
@ -403,7 +478,7 @@
};
};
i2s2_pins_sleep_a: i2s2-1 {
i2s2_sleep_pins_a: i2s2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
<STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
@ -411,7 +486,7 @@
};
};
ltdc_pins_a: ltdc-a-0 {
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
<STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
@ -447,7 +522,7 @@
};
};
ltdc_pins_sleep_a: ltdc-a-1 {
ltdc_sleep_pins_a: ltdc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
@ -480,7 +555,7 @@
};
};
ltdc_pins_b: ltdc-b-0 {
ltdc_pins_b: ltdc-1 {
pins {
pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
<STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
@ -516,7 +591,7 @@
};
};
ltdc_pins_sleep_b: ltdc-b-1 {
ltdc_sleep_pins_b: ltdc-sleep-1 {
pins {
pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
@ -549,6 +624,142 @@
};
};
ltdc_pins_c: ltdc-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
<STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
<STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */
<STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
<STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
<STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
<STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */
<STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */
<STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
<STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
<STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */
<STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
<STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
<STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
<STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
<STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
<STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
<STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
<STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */
<STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
<STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
};
ltdc_sleep_pins_c: ltdc-sleep-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
<STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
<STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */
<STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
<STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
<STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */
<STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */
<STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */
<STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */
<STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */
<STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */
<STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
<STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */
<STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */
<STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */
<STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
<STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */
<STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */
<STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
<STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */
<STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */
};
};
ltdc_pins_d: ltdc-3 {
pins1 {
pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
<STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
<STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
<STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
<STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
<STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
<STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
<STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
<STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
<STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
<STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
<STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */
<STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
<STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
<STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
<STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
<STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
<STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
<STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
<STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
<STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
<STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
<STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
<STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
<STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
<STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
ltdc_sleep_pins_d: ltdc-sleep-3 {
pins {
pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
<STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
<STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
<STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */
<STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
<STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
<STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
<STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
<STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
<STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
<STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
<STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
<STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */
<STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
<STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
<STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
<STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
<STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
<STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */
<STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
<STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
<STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
<STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
<STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
<STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
<STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
<STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
};
};
m_can1_pins_a: m-can1-0 {
pins1 {
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
@ -569,6 +780,46 @@
};
};
m_can1_pins_b: m-can1-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
bias-disable;
};
};
m_can1_sleep_pins_b: m_can1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
<STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
};
};
m_can2_pins_a: m-can2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
bias-disable;
};
};
m_can2_sleep_pins_a: m_can2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
<STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
};
};
pwm1_pins_a: pwm1-0 {
pins {
pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
@ -618,6 +869,21 @@
};
};
pwm3_pins_b: pwm3-1 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
pwm3_sleep_pins_b: pwm3-sleep-1 {
pins {
pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */
};
};
pwm4_pins_a: pwm4-0 {
pins {
pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
@ -665,6 +931,25 @@
};
};
pwm5_pins_b: pwm5-1 {
pins {
pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */
<STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */
<STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
pwm5_sleep_pins_b: pwm5-sleep-1 {
pins {
pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */
<STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */
<STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
};
};
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
@ -778,7 +1063,7 @@
};
};
sai2a_sleep_pins_a: sai2a-1 {
sai2a_sleep_pins_a: sai2a-sleep-0 {
pins {
pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
<STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
@ -787,7 +1072,7 @@
};
};
sai2a_pins_b: sai2a-2 {
sai2a_pins_b: sai2a-1 {
pins1 {
pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
<STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
@ -798,7 +1083,7 @@
};
};
sai2a_sleep_pins_b: sai2a-sleep-3 {
sai2a_sleep_pins_b: sai2a-sleep-1 {
pins {
pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
<STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
@ -806,6 +1091,25 @@
};
};
sai2a_pins_c: sai2a-4 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
<STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
};
sai2a_sleep_pins_c: sai2a-5 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
<STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
};
};
sai2b_pins_a: sai2b-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
@ -821,7 +1125,7 @@
};
};
sai2b_sleep_pins_a: sai2b-1 {
sai2b_sleep_pins_a: sai2b-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
<STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
@ -830,14 +1134,27 @@
};
};
sai2b_pins_b: sai2b-2 {
sai2b_pins_b: sai2b-1 {
pins {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_b: sai2b-3 {
sai2b_sleep_pins_b: sai2b-sleep-1 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};
};
sai2b_pins_c: sai2a-4 {
pins1 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_c: sai2a-sleep-5 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};
@ -852,7 +1169,7 @@
};
};
sai4a_sleep_pins_a: sai4a-1 {
sai4a_sleep_pins_a: sai4a-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
};
@ -939,7 +1256,7 @@
sdmmc1_dir_pins_b: sdmmc1-dir-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('E', 14, AF8)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
slew-rate = <1>;
drive-push-pull;
@ -954,9 +1271,9 @@
sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
pins {
pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
<STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
<STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
<STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
};
};
@ -1079,6 +1396,27 @@
};
sdmmc2_d47_pins_b: sdmmc2-d47-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
};
};
sdmmc2_d47_pins_c: sdmmc2-d47-2 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
@ -1090,7 +1428,7 @@
};
};
sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
@ -1153,6 +1491,60 @@
};
};
sdmmc3_b4_pins_b: sdmmc3-b4-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
<STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
<STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
slew-rate = <2>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
<STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
<STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
slew-rate = <2>;
drive-push-pull;
bias-pull-up;
};
pins3 {
pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-open-drain;
bias-pull-up;
};
};
sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
pins {
pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
<STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
<STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
<STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
<STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
<STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
};
};
spdifrx_pins_a: spdifrx-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
@ -1160,7 +1552,7 @@
};
};
spdifrx_sleep_pins_a: spdifrx-1 {
spdifrx_sleep_pins_a: spdifrx-sleep-0 {
pins {
pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
};
@ -1168,15 +1560,15 @@
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
<STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */
<STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <3>;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
bias-disable;
};
};
@ -1188,6 +1580,54 @@
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
<STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_sleep_pins_a: usart2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
};
};
usart2_pins_b: usart2-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
<STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
bias-disable;
};
};
usart2_sleep_pins_b: usart2-sleep-1 {
pins {
pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
<STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
<STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
};
};
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
@ -1227,6 +1667,19 @@
};
};
uart4_pins_c: uart4-2 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
@ -1242,6 +1695,19 @@
};
};
uart7_pins_b: uart7-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
bias-disable;
};
};
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
@ -1279,7 +1745,7 @@
};
};
i2c2_pins_sleep_b2: i2c2-1 {
i2c2_sleep_pins_b2: i2c2-sleep-0 {
pins {
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
};
@ -1295,7 +1761,7 @@
};
};
i2c4_pins_sleep_a: i2c4-1 {
i2c4_sleep_pins_a: i2c4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
@ -1316,4 +1782,18 @@
bias-disable;
};
};
spi4_pins_a: spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
<STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
bias-disable;
};
};
};

36
arch/arm/dts/stm32mp15-u-boot.dtsi
View File

@ -32,6 +32,10 @@
reboot {
u-boot,dm-pre-reloc;
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
mask = <0x1>;
};
soc {
@ -185,6 +189,38 @@
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&usart1 {
resets = <&rcc USART1_R>;
};
&usart2 {
resets = <&rcc USART2_R>;
};
&usart3 {
resets = <&rcc USART3_R>;
};
&uart4 {
resets = <&rcc UART4_R>;
};
&uart5 {
resets = <&rcc UART5_R>;
};
&usart6 {
resets = <&rcc USART6_R>;
};
&uart7 {
resets = <&rcc UART7_R>;
};
&uart8{
resets = <&rcc UART8_R>;
};
&usbotg_hs {
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
};

48
arch/arm/dts/stm32mp151.dtsi
View File

@ -44,8 +44,6 @@
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_off = <0x84000002>;
cpu_on = <0x84000003>;
};
intc: interrupt-controller@a0021000 {
@ -128,13 +126,6 @@
status = "disabled";
};
reboot {
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
mask = <0x1>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -500,7 +491,7 @@
};
i2c1: i2c@40012000 {
compatible = "st,stm32f7-i2c";
compatible = "st,stm32mp15-i2c";
reg = <0x40012000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
@ -509,12 +500,13 @@
resets = <&rcc I2C1_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x1>;
wakeup-source;
status = "disabled";
};
i2c2: i2c@40013000 {
compatible = "st,stm32f7-i2c";
compatible = "st,stm32mp15-i2c";
reg = <0x40013000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
@ -523,12 +515,13 @@
resets = <&rcc I2C2_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
wakeup-source;
status = "disabled";
};
i2c3: i2c@40014000 {
compatible = "st,stm32f7-i2c";
compatible = "st,stm32mp15-i2c";
reg = <0x40014000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@ -537,12 +530,13 @@
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
wakeup-source;
status = "disabled";
};
i2c5: i2c@40015000 {
compatible = "st,stm32f7-i2c";
compatible = "st,stm32mp15-i2c";
reg = <0x40015000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
@ -551,6 +545,7 @@
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
wakeup-source;
status = "disabled";
};
@ -575,14 +570,14 @@
dac1: dac@1 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
#io-channel-cells = <1>;
reg = <1>;
status = "disabled";
};
dac2: dac@2 {
compatible = "st,stm32-dac";
#io-channels-cells = <1>;
#io-channel-cells = <1>;
reg = <2>;
status = "disabled";
};
@ -1157,6 +1152,11 @@
};
};
pwr_mcu: pwr_mcu@50001014 {
compatible = "syscon";
reg = <0x50001014 0x4>;
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
@ -1413,14 +1413,12 @@
"mac-clk-tx",
"mac-clk-rx",
"eth-ck",
"ethstp",
"syscfg-clk";
"ethstp";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
<&rcc ETHCK_K>,
<&rcc ETHSTP>,
<&rcc SYSCFG>;
<&rcc ETHSTP>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
@ -1458,6 +1456,11 @@
clock-names = "lcd";
resets = <&rcc LTDC_R>;
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
iwdg2: watchdog@5a002000 {
@ -1513,7 +1516,7 @@
};
i2c4: i2c@5c002000 {
compatible = "st,stm32f7-i2c";
compatible = "st,stm32mp15-i2c";
reg = <0x5c002000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
@ -1522,6 +1525,7 @@
resets = <&rcc I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
wakeup-source;
status = "disabled";
};
@ -1552,7 +1556,7 @@
};
i2c6: i2c@5c009000 {
compatible = "st,stm32f7-i2c";
compatible = "st,stm32mp15-i2c";
reg = <0x5c009000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
@ -1561,6 +1565,7 @@
resets = <&rcc I2C6_R>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x20>;
wakeup-source;
status = "disabled";
};
@ -1742,6 +1747,7 @@
resets = <&rcc MCU_R>;
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
status = "disabled";
};
};

8
arch/arm/dts/stm32mp157.dtsi
View File

@ -15,7 +15,6 @@
clocks = <&rcc GPU>, <&rcc GPU_K>;
clock-names = "bus" ,"core";
resets = <&rcc GPU_R>;
status = "disabled";
};
dsi: dsi@5a000000 {
@ -25,7 +24,14 @@
clock-names = "pclk", "ref", "px_clk";
resets = <&rcc DSI_R>;
reset-names = "apb";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};

4
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
View File

@ -16,6 +16,7 @@
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
u-boot,mmc-env-partition = "ssbl";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
@ -162,8 +163,6 @@
&sdmmc1 {
u-boot,dm-spl;
broken-cd;
/delete-property/ cd-gpios;
};
&sdmmc1_b4_pins_a {
@ -194,5 +193,4 @@
&usbotg_hs {
u-boot,force-b-session-valid;
hnp-srp-disable;
};

8
arch/arm/dts/stm32mp157c-dk2.dts
View File

@ -27,15 +27,10 @@
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
phy-dsi-supply = <&reg18>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
@ -83,9 +78,6 @@
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in>;

3
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
View File

@ -17,6 +17,7 @@
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
u-boot,mmc-env-partition = "ssbl";
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
@ -158,8 +159,6 @@
&sdmmc1 {
u-boot,dm-spl;
broken-cd;
/delete-property/ cd-gpios;
};
&sdmmc1_b4_pins_a {

7
arch/arm/dts/stm32mp157c-ed1.dts
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@ -134,13 +134,12 @@
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_pins_a>;
pinctrl-1 = <&i2c4_pins_sleep_a>;
pinctrl-1 = <&i2c4_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
@ -328,6 +327,10 @@
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-ddr50;
status = "okay";
};

14
arch/arm/dts/stm32mp157c-ev1.dts
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@ -98,15 +98,10 @@
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
phy-dsi-supply = <&reg18>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
@ -141,7 +136,7 @@
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
@ -176,7 +171,7 @@
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
pinctrl-1 = <&i2c2_pins_sleep_a>;
pinctrl-1 = <&i2c2_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
@ -230,7 +225,7 @@
&i2c5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_pins_a>;
pinctrl-1 = <&i2c5_pins_sleep_a>;
pinctrl-1 = <&i2c5_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
@ -240,9 +235,6 @@
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&dsi_in>;

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@ -0,0 +1,125 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
config {
u-boot,boot-led = "heartbeat";
};
};
&clk_hse {
st,digbypass;
};
&i2c2 {
u-boot,dm-pre-reloc;
};
&i2c2_pins_a {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
};
};
&pmic {
u-boot,dm-pre-reloc;
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};

364
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@ -0,0 +1,364 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/st,stpmic1.h>
/ {
model = "Seeed Studio Odyssey-STM32MP157C SOM";
compatible = "seeed,odyssey-stm32mp157c-som", "st,stm32mp157";
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
mcuram2: mcuram2@10000000 {
compatible = "shared-dma-pool";
reg = <0x10000000 0x40000>;
no-map;
};
vdev0vring0: vdev0vring0@10040000 {
compatible = "shared-dma-pool";
reg = <0x10040000 0x1000>;
no-map;
};
vdev0vring1: vdev0vring1@10041000 {
compatible = "shared-dma-pool";
reg = <0x10041000 0x1000>;
no-map;
};
vdev0buffer: vdev0buffer@10042000 {
compatible = "shared-dma-pool";
reg = <0x10042000 0x4000>;
no-map;
};
mcuram: mcuram@30000000 {
compatible = "shared-dma-pool";
reg = <0x30000000 0x40000>;
no-map;
};
retram: retram@38000000 {
compatible = "shared-dma-pool";
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@d4000000 {
reg = <0xd4000000 0x4000000>;
no-map;
};
optee@de000000 {
reg = <0xde000000 0x02000000>;
no-map;
};
};
led {
compatible = "gpio-leds";
blue {
label = "heartbeat";
gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_a>;
pinctrl-1 = <&i2c2_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
regulators {
compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo6-supply = <&v3v3>;
pwr_sw1-supply = <&bst_out>;
pwr_sw2-supply = <&bst_out>;
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
regulator-initial-mode = <0>;
};
v1v8_audio: ldo1 {
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO1 0>;
};
v3v3_hdmi: ldo2 {
regulator-name = "v3v3_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO2 0>;
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
interrupts = <IT_CURLIM_LDO4 0>;
};
vdda: ldo5 {
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
interrupts = <IT_CURLIM_LDO5 0>;
regulator-boot-on;
};
v1v2_hdmi: ldo6 {
regulator-name = "v1v2_hdmi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
interrupts = <IT_CURLIM_LDO6 0>;
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
};
bst_out: boost {
regulator-name = "bst_out";
interrupts = <IT_OCP_BOOST 0>;
};
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
regulator-active-discharge = <1>;
};
};
onkey {
compatible = "st,stpmic1-onkey";
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
interrupt-names = "onkey-falling", "onkey-rising";
power-off-time-sec = <10>;
status = "okay";
};
watchdog {
compatible = "st,stpmic1-wdt";
status = "disabled";
};
};
};
&ipcc {
status = "okay";
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
broken-cd;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "okay";
};
&timers1 {
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm1_pins_a>;
pinctrl-1 = <&pwm1_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@0 {
status = "okay";
};
};
&timers3 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@2 {
status = "okay";
};
};
&timers4 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@3 {
status = "okay";
};
};
&timers5 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm5_pins_a>;
pinctrl-1 = <&pwm5_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@4 {
status = "okay";
};
};
&timers6 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
timer@5 {
status = "okay";
};
};
&timers12 {
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled";
pwm {
pinctrl-0 = <&pwm12_pins_a>;
pinctrl-1 = <&pwm12_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@11 {
status = "okay";
};
};
&vrefbuf {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
vdda-supply = <&vdd>;
status = "okay";
};

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@ -0,0 +1,58 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>
*/
#include "stm32mp157c-odyssey-som-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
usb0 = &usbotg_hs;
};
config {
u-boot,boot-led = "heartbeat";
u-boot,error-led = "error";
};
led {
red {
label = "error";
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
default-state = "off";
status = "okay";
};
};
};
&adc {
status = "okay";
};
&sdmmc1 {
u-boot,dm-spl;
};
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};

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@ -0,0 +1,161 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>
*/
/dts-v1/;
#include "stm32mp157c-odyssey-som.dtsi"
/ {
model = "Seeed Studio Odyssey-STM32MP157C Board";
compatible = "seeed,odyssey-stm32mp157c", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
led {
compatible = "gpio-leds";
blue {
label = "heartbeat";
gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
};
&adc {
pinctrl-names = "default";
pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&vrefbuf>;
status = "disabled";
adc1: adc@0 {
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
* Use arbitrary margin here (e.g. 5us).
*/
st,min-sample-time-nsecs = <5000>;
/* AIN connector, USB Type-C CC1 & CC2 */
st,adc-channels = <0 1 6 13 18 19>;
status = "okay";
};
adc2: adc@100 {
/* AIN connector, USB Type-C CC1 & CC2 */
st,adc-channels = <0 1 2 6 18 19>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
};
};
&cec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cec_pins_b>;
pinctrl-1 = <&cec_sleep_pins_b>;
status = "okay";
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_sleep_pins_a>;
i2c-scl-rising-time-ns = <100>;
i2c-scl-falling-time-ns = <7>;
status = "okay";
/delete-property/dmas;
/delete-property/dma-names;
};
&i2s2 {
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
clock-names = "pclk", "i2sclk", "x8k", "x11k";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2s2_pins_a>;
pinctrl-1 = <&i2s2_sleep_pins_a>;
status = "okay";
};
&pwr_regulators {
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
broken-cd;
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbotg_hs {
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
phy-names = "usb2-phy";
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcom-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcom.dtsi"
/ {
model = "DH Electronics STM32MP15xx DHCOM DRC02";
compatible = "dh,stm32mp15xx-dhcom-drc02", "st,stm32mp1xx";
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc {
status = "disabled";
};
&dac {
status = "disabled";
};
&gpiob {
/*
* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
* GPIO line, however the STM32 UART driver assumes RX happens
* during TX anyway and that it only controls drive enable DE
* line. Hence, the RX is always enabled here.
*/
usb-hub {
gpio-hog;
gpios = <8 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "rs485-rx-en";
};
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "Out1",
"Out2", "", "", "";
};
&gpioi {
gpio-line-names = "In1", "", "", "",
"", "", "", "",
"In2", "", "", "",
"", "", "", "";
/*
* NOTE: The USB Hub on the DRC02 needs a reset signal to be
* pulled high in order to be detected by the USB Controller.
* This signal should be handled by USB power sequencing in
* order to reset the Hub when USB bus is powered down, but
* so far there is no such functionality.
*/
usb-hub {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c5 { /* TP7/TP8 */
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
/* spare dmas for other usage */
/delete-property/dmas;
/delete-property/dma-names;
};
&sdmmc3 {
/*
* On DRC02, the SoM does not have SDIO WiFi. The pins
* are used for on-board microSD slot instead.
*/
/delete-property/broken-cd;
cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>;
cs-gpios = <&gpioz 3 0>;
/* Use PIO for the display */
/delete-property/dmas;
/delete-property/dma-names;
status = "disabled"; /* Enable once there is display driver */
/*
* Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are
* also connected to the display board connector.
*/
};
&usart3 {
pinctrl-names = "default";
pinctrl-0 = <&usart3_pins_a>;
status = "okay";
};
/*
* Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1),
* however the STM32MP1 pinmux cannot map them to UART4 .
*/
&uart8 { /* RS485 */
pinctrl-names = "default";
pinctrl-0 = <&uart8_pins_a>;
rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
};

69
arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
View File

@ -11,78 +11,9 @@
aliases {
serial0 = &uart4;
ethernet0 = &ethernet0;
};
chosen {
stdout-path = "serial0:115200n8";
};
ethernet_vio: vioregulator {
compatible = "regulator-fixed";
regulator-name = "vio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
st,eth_ref_clk_sel;
phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@1 {
reg = <1>;
};
};
};
&pinctrl {
ethernet0_rmii_pins_a: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
bias-disable;
};
};
ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
};
};
};

3
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View File

@ -264,9 +264,6 @@
&sdmmc1 {
u-boot,dm-spl;
broken-cd;
/delete-property/ cd-gpios;
/delete-property/ disable-wp;
};
&sdmmc1_b4_pins_a {

69
arch/arm/dts/stm32mp15xx-dhcom.dtsi
View File

@ -14,12 +14,23 @@
/ {
aliases {
eeprom0 = &eeprom0;
ethernet0 = &ethernet0;
};
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x40000000>;
};
ethernet_vio: vioregulator {
compatible = "regulator-fixed";
regulator-name = "vio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
};
};
&cec {
@ -39,6 +50,28 @@
status = "okay";
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rmii_pins_a>;
pinctrl-1 = <&ethernet0_rmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <100>;
phy-handle = <&phy0>;
st,eth_ref_clk_sel;
phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@1 {
reg = <1>;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
@ -228,6 +261,42 @@
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&pinctrl {
ethernet0_rmii_pins_a: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
bias-disable;
};
};
ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
};
};
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;

4
arch/arm/dts/stm32mp15xx-dhcor-avenger96.dts
View File

@ -89,8 +89,8 @@
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_b>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_b>;
pinctrl-0 = <&ethernet0_rgmii_pins_c>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
max-speed = <1000>;

20
arch/arm/dts/stm32mp15xx-dkx.dtsi
View File

@ -112,7 +112,11 @@
&cec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cec_pins_b>;
pinctrl-1 = <&cec_pins_sleep_b>;
pinctrl-1 = <&cec_sleep_pins_b>;
status = "okay";
};
&dts {
status = "okay";
};
@ -127,7 +131,7 @@
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii-id";
max-speed = <1000>;
@ -145,13 +149,12 @@
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
pinctrl-1 = <&i2c1_pins_sleep_a>;
pinctrl-1 = <&i2c1_sleep_pins_a>;
i2c-scl-rising-time-ns = <100>;
i2c-scl-falling-time-ns = <7>;
status = "okay";
@ -226,7 +229,7 @@
&i2c4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_pins_a>;
pinctrl-1 = <&i2c4_pins_sleep_a>;
pinctrl-1 = <&i2c4_sleep_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
clock-frequency = <400000>;
@ -393,7 +396,7 @@
clock-names = "pclk", "i2sclk", "x8k", "x11k";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2s2_pins_a>;
pinctrl-1 = <&i2s2_pins_sleep_a>;
pinctrl-1 = <&i2s2_sleep_pins_a>;
status = "okay";
i2s2_port: port {
@ -417,13 +420,10 @@
&ltdc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-1 = <&ltdc_pins_sleep_a>;
pinctrl-1 = <&ltdc_sleep_pins_a>;
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&sii9022_in>;

1
arch/arm/mach-stm32mp/Kconfig
View File

@ -1,6 +1,7 @@
if ARCH_STM32MP
config SPL
select SPL_BOARD_INIT
select SPL_CLK
select SPL_DM
select SPL_DM_SEQ_ALIAS

2
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
View File

@ -560,7 +560,7 @@ static int init_device(struct stm32prog_data *data,
#ifdef CONFIG_MMC
case STM32PROG_MMC:
mmc = find_mmc_device(dev->dev_id);
if (mmc_init(mmc)) {
if (!mmc || mmc_init(mmc)) {
stm32prog_err("mmc device %d not found", dev->dev_id);
return -ENODEV;
}

19
arch/arm/mach-stm32mp/cpu.c
View File

@ -154,15 +154,20 @@ static void security_init(void)
*/
static void dbgmcu_init(void)
{
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
/*
* Freeze IWDG2 if Cortex-A7 is in debug mode
* done in TF-A for TRUSTED boot and
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
*/
if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable())
if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
}
}
void spl_board_init(void)
{
dbgmcu_init();
}
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
@ -220,9 +225,10 @@ static void early_enable_caches(void)
dcache_enable();
if (IS_ENABLED(CONFIG_SPL_BUILD))
mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
STM32_SYSRAM_SIZE,
DCACHE_DEFAULT_OPTION);
mmu_set_region_dcache_behaviour(
ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
DCACHE_DEFAULT_OPTION);
else
mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
DCACHE_DEFAULT_OPTION);
@ -241,7 +247,6 @@ int arch_cpu_init(void)
timer_init();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
dbgmcu_init();
#ifndef CONFIG_TFABOOT
security_init();
update_bootmode();

2
arch/arm/mach-stm32mp/spl.c
View File

@ -147,7 +147,7 @@ void spl_board_prepare_for_boot(void)
dcache_disable();
}
void spl_board_prepare_for_boot_linux(void)
void spl_board_prepare_for_linux(void)
{
dcache_disable();
}

12
board/dhelectronics/dh_stm32mp1/board.c
View File

@ -653,18 +653,6 @@ int board_interface_eth_init(struct udevice *dev,
return 0;
}
enum env_location env_get_location(enum env_operation op, int prio)
{
if (prio)
return ENVL_UNKNOWN;
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
return ENVL_SPI_FLASH;
#else
return ENVL_NOWHERE;
#endif
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{

22
board/st/stm32mp1/stm32mp1.c
View File

@ -686,7 +686,7 @@ int board_late_init(void)
if (!ret)
ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
&otp, sizeof(otp));
if (!ret && otp) {
if (ret > 0 && otp) {
snprintf(buf, sizeof(buf), "0x%04x", otp >> 16);
env_set("board_id", buf);
@ -787,17 +787,22 @@ enum env_location env_get_location(enum env_operation op, int prio)
return ENVL_UNKNOWN;
switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
#ifdef CONFIG_ENV_IS_IN_EXT4
#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC)
case BOOT_FLASH_SD:
case BOOT_FLASH_EMMC:
return ENVL_MMC;
#endif
#if CONFIG_IS_ENABLED(ENV_IS_IN_EXT4)
case BOOT_FLASH_SD:
case BOOT_FLASH_EMMC:
return ENVL_EXT4;
#endif
#ifdef CONFIG_ENV_IS_IN_UBI
#if CONFIG_IS_ENABLED(ENV_IS_IN_UBI)
case BOOT_FLASH_NAND:
case BOOT_FLASH_SPINAND:
return ENVL_UBI;
#endif
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#if CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)
case BOOT_FLASH_NOR:
return ENVL_SPI_FLASH;
#endif
@ -829,6 +834,15 @@ const char *env_ext4_get_dev_part(void)
}
#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
int mmc_get_env_dev(void)
{
u32 bootmode = get_bootmode();
return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1;
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{

9
configs/stm32mp15_basic_defconfig
View File

@ -22,12 +22,14 @@ CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
@ -59,17 +61,16 @@ CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_IS_IN_UBI=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_EXT4_INTERFACE="mmc"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto"
CONFIG_ENV_EXT4_FILE="/uboot.env"
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot_config"
CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_SPL_ENV_IS_NOWHERE is not set
# CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set
CONFIG_STM32_ADC=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_USB_FUNCTION_FASTBOOT=y

6
configs/stm32mp15_trusted_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
@ -42,13 +43,10 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_IS_IN_UBI=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_EXT4_INTERFACE="mmc"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto"
CONFIG_ENV_EXT4_FILE="/uboot.env"
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot_config"
CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"

2
drivers/phy/phy-stm32-usbphyc.c
View File

@ -263,7 +263,7 @@ static int stm32_usbphyc_phy_power_off(struct phy *phy)
return 0;
if (usbphyc_phy->vdd) {
ret = regulator_set_enable(usbphyc_phy->vdd, false);
ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
if (ret)
return ret;
}

2
include/configs/stm32mp1.h
View File

@ -156,7 +156,7 @@
"splashimage=0xc4300000\0" \
"ramdisk_addr_r=0xc4400000\0" \
"altbootcmd=run bootcmd\0" \
"env_check=if env info -p -d; then env save; fi\0" \
"env_check=if env info -p -d -q; then env save; fi\0" \
STM32MP_BOOTCMD \
BOOTENV \
"boot_net_usb_start=true\0"