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mpc83xx: Migrate CONFIG_LCRR_* to Kconfig

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Migrate the CONFIG_LCRR_* settings to Kconfig.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2019-01-21 09:18:14 +01:00
parent e35012e802
commit 7c2e535770
83 changed files with 281 additions and 120 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -127,28 +127,6 @@ void cpu_init_f (volatile immap_t * im)
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
#endif
0;
__be32 lcrr_mask =
#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
LCRR_DBYP |
#endif
#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
LCRR_EADC |
#endif
#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
LCRR_CLKDIV |
#endif
0;
__be32 lcrr_val =
#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
CONFIG_SYS_LCRR_DBYP |
#endif
#ifdef CONFIG_SYS_LCRR_EADC
CONFIG_SYS_LCRR_EADC |
#endif
#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
CONFIG_SYS_LCRR_CLKDIV |
#endif
0;

1
arch/powerpc/cpu/mpc83xx/initreg/Kconfig
View File

@ -1,5 +1,6 @@
menu "Initial register configuration"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
endmenu

139
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr Normal file
View File

@ -0,0 +1,139 @@
menu "LCRR - Clock Ratio Register register"
if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X
choice
prompt "DLL bypass"
config LCRR_DBYP_UNSET
bool "Don't set value"
config LCRR_DBYP_PLL_ENABLED
bool "PLL enabled"
config LCRR_DBYP_PLL_BYPASSED
bool "PLL bypassed"
endchoice
endif
if ARCH_MPC834X || ARCH_MPC8360
choice
prompt "Additional delay cycles for SDRAM control signals"
config LCRR_BUFCMDC_UNSET
bool "Don't set value"
config LCRR_BUFCMDC_4
bool "4"
config LCRR_BUFCMDC_1
bool "1"
config LCRR_BUFCMDC_2
bool "2"
config LCRR_BUFCMDC_3
bool "3"
endchoice
choice
prompt "Extended CAS latency"
config LCRR_ECL_UNSET
bool "Don't set value"
config LCRR_ECL_4
bool "4"
config LCRR_ECL_5
bool "5"
config LCRR_ECL_6
bool "6"
config LCRR_ECL_7
bool "7"
endchoice
endif # ARCH_MPC834X || ARCH_MPC8360
if !ARCH_MPC8308
choice
prompt "External address delay cycles"
config LCRR_EADC_UNSET
bool "Don't set value"
config LCRR_EADC_4
bool "4"
config LCRR_EADC_1
bool "1"
config LCRR_EADC_2
bool "2"
config LCRR_EADC_3
bool "3"
endchoice
endif # !ARCH_MPC8308
choice
prompt "System clock divider"
config LCRR_CLKDIV_UNSET
bool "Don't set value"
config LCRR_CLKDIV_2
bool "2"
config LCRR_CLKDIV_4
bool "4"
config LCRR_CLKDIV_8
bool "8"
endchoice
config LCRR_DBYP
hex
default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED
default 0x80000000 if LCRR_DBYP_PLL_BYPASSED
config LCRR_BUFCMDC
hex
default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET
default 0x10000000 if LCRR_BUFCMDC_1
default 0x20000000 if LCRR_BUFCMDC_2
default 0x30000000 if LCRR_BUFCMDC_3
config LCRR_ECL
hex
default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET
default 0x1000000 if LCRR_ECL_5
default 0x2000000 if LCRR_ECL_6
default 0x3000000 if LCRR_ECL_7
config LCRR_EADC
hex
default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET
default 0x10000 if LCRR_EADC_1
default 0x20000 if LCRR_EADC_2
default 0x30000 if LCRR_EADC_3
config LCRR_CLKDIV
hex
default 0x0 if LCRR_CLKDIV_UNSET
default 0x2 if LCRR_CLKDIV_2
default 0x4 if LCRR_CLKDIV_4
default 0x8 if LCRR_CLKDIV_8
endmenu

36
arch/powerpc/cpu/mpc83xx/initreg/initreg.h
View File

@ -39,5 +39,41 @@
#endif
#if defined(CONFIG_SPCR_TSEC2EP) && !defined(CONFIG_SPCR_TSEC2EP_UNSET)
CONFIG_SPCR_TSEC2EP |
#endif
0;
const __be32 lcrr_mask =
#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
LCRR_DBYP |
#endif
#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
LCRR_BUFCMDC |
#endif
#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
LCRR_ECL |
#endif
#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
LCRR_EADC |
#endif
#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
LCRR_CLKDIV |
#endif
0;
const __be32 lcrr_val =
#if defined(CONFIG_LCRR_DBYP) && !defined(CONFIG_LCRR_DBYP_UNSET)
CONFIG_LCRR_DBYP |
#endif
#if defined(CONFIG_LCRR_BUFCMDC) && !defined(CONFIG_LCRR_BUFCMDC_UNSET)
CONFIG_LCRR_BUFCMDC |
#endif
#if defined(CONFIG_LCRR_ECL) && !defined(CONFIG_LCRR_ECL_UNSET)
CONFIG_LCRR_ECL |
#endif
#if defined(CONFIG_LCRR_EADC) && !defined(CONFIG_LCRR_EADC_UNSET)
CONFIG_LCRR_EADC |
#endif
#if defined(CONFIG_LCRR_CLKDIV) && !defined(CONFIG_LCRR_CLKDIV_UNSET)
CONFIG_LCRR_CLKDIV |
#endif
0;

2
configs/MPC8308RDB_defconfig
View File

@ -73,6 +73,8 @@ CONFIG_SICR_TMSOBI2_2_5_V=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSECEP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y

2
configs/MPC8313ERDB_33_defconfig
View File

@ -159,3 +159,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8313ERDB_66_defconfig
View File

@ -158,3 +158,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8313ERDB_NAND_33_defconfig
View File

@ -167,3 +167,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8313ERDB_NAND_66_defconfig
View File

@ -166,3 +166,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8315ERDB_defconfig
View File

@ -143,3 +143,5 @@ CONFIG_OR1_CHT_TWO_CLOCK=y
CONFIG_OR1_CSCT_8_CYCLE=y
CONFIG_OR1_CST_ONE_CLOCK=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/MPC8323ERDB_defconfig
View File

@ -108,3 +108,5 @@ CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/MPC832XEMDS_ATM_defconfig
View File

@ -143,3 +143,5 @@ CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_XAM_SET=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/MPC832XEMDS_HOST_33_defconfig
View File

@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_XAM_SET=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/MPC832XEMDS_HOST_66_defconfig
View File

@ -163,3 +163,5 @@ CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_XAM_SET=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/MPC832XEMDS_SLAVE_defconfig
View File

@ -160,3 +160,5 @@ CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_XAM_SET=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/MPC832XEMDS_defconfig
View File

@ -142,3 +142,5 @@ CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_XAM_SET=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/MPC8349EMDS_PCI64_defconfig
View File

@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8349EMDS_SDRAM_defconfig
View File

@ -113,3 +113,5 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_MPC8XXX_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8349EMDS_SLAVE_defconfig
View File

@ -104,3 +104,5 @@ CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8349EMDS_defconfig
View File

@ -107,3 +107,5 @@ CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8349ITXGP_defconfig
View File

@ -178,3 +178,5 @@ CONFIG_BR3_MACHINE_UPMA=y
CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_OR3_AM_32_KBYTES=y
CONFIG_OR3_BI_BURSTINHIBIT=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8349ITX_LOWBOOT_defconfig
View File

@ -186,3 +186,5 @@ CONFIG_BR3_MACHINE_UPMA=y
CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_OR3_AM_32_KBYTES=y
CONFIG_OR3_BI_BURSTINHIBIT=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC8349ITX_defconfig
View File

@ -185,3 +185,5 @@ CONFIG_BR3_MACHINE_UPMA=y
CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_OR3_AM_32_KBYTES=y
CONFIG_OR3_BI_BURSTINHIBIT=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/MPC837XEMDS_HOST_defconfig
View File

@ -178,3 +178,5 @@ CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_CHT_TWO_CLOCK=y
CONFIG_OR3_CST_ONE_CLOCK=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y

2
configs/MPC837XEMDS_SLAVE_defconfig
View File

@ -131,3 +131,5 @@ CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_CHT_TWO_CLOCK=y
CONFIG_OR3_CST_ONE_CLOCK=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y

2
configs/MPC837XEMDS_defconfig
View File

@ -154,3 +154,5 @@ CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_CHT_TWO_CLOCK=y
CONFIG_OR3_CST_ONE_CLOCK=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y

2
configs/MPC837XERDB_SLAVE_defconfig
View File

@ -132,3 +132,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y

2
configs/MPC837XERDB_defconfig
View File

@ -175,3 +175,5 @@ CONFIG_OR2_SETA_EXTERNAL=y
CONFIG_OR2_XACS_EXTENDED=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y

2
configs/TQM834x_defconfig
View File

@ -147,3 +147,5 @@ CONFIG_OR0_ACS_QUARTER_CYCLE_EARLIER=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_SCY_5=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_8=y

2
configs/hrcon_defconfig
View File

@ -131,3 +131,5 @@ CONFIG_OR1_XACS_EXTENDED=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/hrcon_dh_defconfig
View File

@ -129,3 +129,5 @@ CONFIG_OR1_XACS_EXTENDED=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_TRLX_RELAXED=y
CONFIG_OR1_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/ids8313_defconfig
View File

@ -170,3 +170,5 @@ CONFIG_OR3_AM_32_KBYTES=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_SCY_1=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/kmcoge5ne_defconfig
View File

@ -192,3 +192,6 @@ CONFIG_OR4_CSNT_EARLIER=y
CONFIG_OR4_EAD_EXTRA=y
CONFIG_OR4_SCY_2=y
CONFIG_OR4_TRLX_RELAXED=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_LCRR_EADC_2=y

3
configs/kmeter1_defconfig
View File

@ -154,3 +154,6 @@ CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_EAD_EXTRA=y
CONFIG_OR3_SCY_2=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_LCRR_EADC_2=y

3
configs/kmopti2_defconfig
View File

@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_OR3_AM_256_MBYTES=y
CONFIG_OR3_SCY_4=y
CONFIG_OR3_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/kmsupx5_defconfig
View File

@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y
CONFIG_OR2_SCY_2=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_4_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/kmtegr1_defconfig
View File

@ -157,3 +157,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_OR3_AM_256_MBYTES=y
CONFIG_OR3_SCY_5=y
CONFIG_OR3_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/kmtepr2_defconfig
View File

@ -179,3 +179,6 @@ CONFIG_BR3_PORTSIZE_16BIT=y
CONFIG_OR3_AM_256_MBYTES=y
CONFIG_OR3_SCY_4=y
CONFIG_OR3_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/kmvect1_defconfig
View File

@ -177,3 +177,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_SCY_3=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/mpc8308_p1m_defconfig
View File

@ -122,3 +122,5 @@ CONFIG_BR2_PORTSIZE_8BIT=y
CONFIG_OR2_AM_32_KBYTES=y
CONFIG_OR2_SCY_4=y
CONFIG_OR2_EHTR_1_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/sbc8349_PCI_33_defconfig
View File

@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/sbc8349_PCI_66_defconfig
View File

@ -106,3 +106,5 @@ CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/sbc8349_defconfig
View File

@ -84,3 +84,5 @@ CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y

2
configs/strider_con_defconfig
View File

@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/strider_con_dp_defconfig
View File

@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/strider_cpu_defconfig
View File

@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/strider_cpu_dp_defconfig
View File

@ -130,3 +130,5 @@ CONFIG_OR1_CSNT_EARLIER=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_EHTR_NORMAL=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/suvd3_defconfig
View File

@ -175,3 +175,6 @@ CONFIG_OR3_ACS_QUARTER_CYCLE_EARLIER=y
CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_SCY_3=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/tuge1_defconfig
View File

@ -157,3 +157,6 @@ CONFIG_OR2_EAD_EXTRA=y
CONFIG_OR2_SCY_2=y
CONFIG_OR2_TRLX_RELAXED=y
CONFIG_OR2_EHTR_4_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

3
configs/tuxx1_defconfig
View File

@ -182,3 +182,6 @@ CONFIG_OR3_CSNT_EARLIER=y
CONFIG_OR3_SCY_2=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_4_CYCLE=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y

2
configs/ve8313_defconfig
View File

@ -145,3 +145,5 @@ CONFIG_OR3_SCY_15=y
CONFIG_OR3_XACS_EXTENDED=y
CONFIG_OR3_TRLX_RELAXED=y
CONFIG_OR3_EHTR_8_CYCLE=y
CONFIG_LCRR_EADC_3=y
CONFIG_LCRR_CLKDIV_2=y

1
configs/vme8349_defconfig
View File

@ -118,3 +118,4 @@ CONFIG_BR1_MACHINE_GPCM=y
CONFIG_BR1_PORTSIZE_32BIT=y
CONFIG_OR1_AM_256_KBYTES=y
CONFIG_OR1_SETA_EXTERNAL=y
CONFIG_LCRR_CLKDIV_4=y

2
include/configs/MPC8308RDB.h
View File

@ -126,8 +126,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
/*

2
include/configs/MPC8313ERDB_NAND.h
View File

@ -191,8 +191,6 @@
/*
* Local Bus LCRR and LBCR regs
*/
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF) /* 0x0004ff0f */

2
include/configs/MPC8313ERDB_NOR.h
View File

@ -164,8 +164,6 @@
/*
* Local Bus LCRR and LBCR regs
*/
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF) /* 0x0004ff0f */

2
include/configs/MPC8315ERDB.h
View File

@ -121,8 +121,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
#define CONFIG_FSL_ELBC 1

2
include/configs/MPC8323ERDB.h
View File

@ -118,8 +118,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*

2
include/configs/MPC832XEMDS.h
View File

@ -118,8 +118,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*

2
include/configs/MPC8349EMDS.h
View File

@ -161,8 +161,6 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*

2
include/configs/MPC8349EMDS_SDRAM.h
View File

@ -158,8 +158,6 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*

2
include/configs/MPC8349ITX.h
View File

@ -258,8 +258,6 @@ boards, we say we have two, but don't display a message if we find only one. */
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/* LB sdram refresh timer, about 6us */

2
include/configs/MPC837XEMDS.h
View File

@ -139,8 +139,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1

2
include/configs/MPC837XERDB.h
View File

@ -163,8 +163,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1

12
include/configs/TQM834x.h
View File

@ -16,18 +16,6 @@
*/
#define CONFIG_E300 1 /* E300 Family */
/*
* Local Bus LCRR
* LCRR: DLL bypass, Clock divider is 8
*
* for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
*
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
/* board pre init: do not call, nothing to do */
/* detect the number of flash banks */

1
include/configs/caddy2.h
View File

@ -104,7 +104,6 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */

2
include/configs/hrcon.h
View File

@ -115,8 +115,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
/*

2
include/configs/ids8313.h
View File

@ -39,8 +39,6 @@
/*
* Local Bus LCRR and LBCR regs
*/
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
(0xFF << LBCR_BMT_SHIFT) |\
0xF)

7
include/configs/kmcoge5ne.h
View File

@ -296,13 +296,6 @@
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
/*
* PAXE on the local bus CS3
*/

7
include/configs/kmeter1.h
View File

@ -276,13 +276,6 @@
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
/*
* PAXE on the local bus CS3
*/

4
include/configs/kmopti2.h
View File

@ -294,10 +294,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */

4
include/configs/kmsupx5.h
View File

@ -294,10 +294,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */

4
include/configs/kmtegr1.h
View File

@ -346,10 +346,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
/* must be after the include because KMBEC_FPGA is otherwise undefined */

4
include/configs/kmtepr2.h
View File

@ -294,10 +294,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */

4
include/configs/kmvect1.h
View File

@ -338,10 +338,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000

2
include/configs/mpc8308_p1m.h
View File

@ -130,8 +130,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
/*

2
include/configs/sbc8349.h
View File

@ -131,8 +131,6 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */

2
include/configs/strider.h
View File

@ -115,8 +115,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
/*

4
include/configs/suvd3.h
View File

@ -291,10 +291,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000

4
include/configs/tuge1.h
View File

@ -294,10 +294,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */

4
include/configs/tuxx1.h
View File

@ -294,10 +294,6 @@
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR_DBYP 0x80000000
#define CONFIG_SYS_LCRR_EADC 0x00010000
#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */

3
include/configs/ve8313.h
View File

@ -133,9 +133,6 @@
/*
* Local Bus LCRR and LBCR regs
*/
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
#define CONFIG_SYS_LBC_MRTPR 0x20000000

1
include/configs/vme8349.h
View File

@ -104,7 +104,6 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */

3
scripts/config_whitelist.txt
View File

@ -3203,9 +3203,6 @@ CONFIG_SYS_LBC_SDRAM_BASE_PHYS
CONFIG_SYS_LBC_SDRAM_SIZE
CONFIG_SYS_LB_SDRAM
CONFIG_SYS_LCD_BASE
CONFIG_SYS_LCRR_CLKDIV
CONFIG_SYS_LCRR_DBYP
CONFIG_SYS_LCRR_EADC
CONFIG_SYS_LDB_CLOCK
CONFIG_SYS_LDSCRIPT
CONFIG_SYS_LED_BASE