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net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x"

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After the discussion here:
https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/

which resulted in this patch:
https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/

and many other discussions before it, notably:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/

it became apparent that nobody really knows what "SGMII 2500" is.
Certainly, Freescale/NXP hardware engineers name this protocol
"SGMII 2500" in the reference manuals, but the PCS devices do not
support any "SGMII" specific features when operating at the speed of
2500 Mbps, no in-band autoneg and no speed change via symbol replication
. So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b
with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without
in-band autoneg and at a fixed speed" is indistinguishable from
"2500base-x without in-band autoneg", which is precisely what these NXP
devices support.

So it just appears that "SGMII 2500" is an unclear name with no clear
definition that stuck.

As such, in the Linux kernel, the drivers which use this SERDES protocol
use the 2500base-x phy-mode.

This patch converts U-Boot to use 2500base-x too, or at least, as much
as it can.

Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500
completely, but the mvpp2 driver seems to even distinguish between SGMII
2500 and 2500base-X. Namely, it enables in-band autoneg for one but not
the other, and forces flow control for one but not the other. This goes
back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500
is an MII protocol (connects a MAC to a PHY such as Aquantia), but the
two are practically indistinguishable through everything except use case.

NXP devices can support both use cases through an identical configuration,
for example RX flow control can be unconditionally enabled in order to
support rate adaptation performed by an Aquantia PHY. At least I can
find no indication in online documents published by Cisco which would
point towards "SGMII-2500" being an actual standard with an actual
definition, so I cannot say "yes, NXP devices support it".

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This commit is contained in:
Vladimir Oltean
2021-09-18 15:32:35 +03:00
committed by Ramon Fried
parent 77b11f7604
commit 7c2d5d1642
23 changed files with 45 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
View File

@@ -14,6 +14,6 @@
&enetc0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

8
arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
View File

@@ -30,25 +30,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

4
arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
View File

@@ -19,13 +19,13 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

2
arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
View File

@@ -19,7 +19,7 @@
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};

2
arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
View File

@@ -19,7 +19,7 @@
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};

2
arch/arm/dts/fsl-sch-30841.dtsi
View File

@@ -9,7 +9,7 @@
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
* It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R.
* It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/

2
arch/arm/dts/fsl-sch-30842.dtsi
View File

@@ -8,7 +8,7 @@
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
* SGMII-2500, USXGMII, 10GBase-R.
* 2500base-x, USXGMII, 10GBase-R.
* PHY address is 0x02.
*/
phy@02 {

4
board/freescale/ls1012aqds/eth.c
View File

@@ -244,7 +244,7 @@ int pfe_eth_board_init(struct udevice *dev)
bus = miiphy_get_dev_by_name(mdio_name);
pfe_set_mdio(1, bus);
pfe_set_phy_address_mode(1, CONFIG_PFE_SGMII_2500_PHY2_ADDR,
PHY_INTERFACE_MODE_SGMII_2500);
PHY_INTERFACE_MODE_2500BASEX);
data8 = QIXIS_READ(brdcfg[12]);
data8 |= 0x20;
@@ -263,7 +263,7 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(0, bus);
pfe_set_phy_address_mode(0,
CONFIG_PFE_SGMII_2500_PHY1_ADDR,
PHY_INTERFACE_MODE_SGMII_2500);
PHY_INTERFACE_MODE_2500BASEX);
}
break;

4
board/freescale/ls1012aqds/ls1012aqds.c
View File

@@ -265,7 +265,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
ETH_1_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
prop_val.phy_mode = "sgmii-2500";
prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
ETH_1_MDIO);
} else {
@@ -277,7 +277,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
ETH_2_2_5G_MDIO_MUX);
prop_val.phy_mask = cpu_to_fdt32(
ETH_2_5G_MDIO_PHY_MASK);
prop_val.phy_mode = "sgmii-2500";
prop_val.phy_mode = "2500base-x";
pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
ETH_2_MDIO);
}

2
board/freescale/ls1012aqds/ls1012aqds_pfe.h
View File

@@ -17,7 +17,7 @@
#define ETH_1_2_5G_PHY_ID 0x1
#define ETH_1_2_5G_MDIO_MUX 0x2
#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
#define ETH_2_5G_PHY_MODE "sgmii-2500"
#define ETH_2_5G_PHY_MODE "2500base-x"
#define ETH_2_2_5G_BUS_ID 0x1
#define ETH_2_2_5G_PHY_ID 0x2
#define ETH_2_2_5G_MDIO_MUX 0x3

4
board/freescale/ls1012ardb/eth.c
View File

@@ -121,12 +121,12 @@ int pfe_eth_board_init(struct udevice *dev)
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC1_PHY_ADDR,
PHY_INTERFACE_MODE_SGMII_2500);
PHY_INTERFACE_MODE_2500BASEX);
} else {
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
PHY_INTERFACE_MODE_SGMII_2500);
PHY_INTERFACE_MODE_2500BASEX);
}
break;
default:

8
board/freescale/ls1043aqds/eth.c
View File

@@ -176,7 +176,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
"sgmii-riser-s4-p1");
}
} else if (fm_info_get_enet_if(port) ==
PHY_INTERFACE_MODE_SGMII_2500) {
PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
@@ -187,7 +187,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
"sgmii-2500");
"2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (mdio_mux[port]) {
case EMI1_SLOT1:
@@ -430,12 +430,12 @@ int board_eth_init(struct bd_info *bis)
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
} else if (interface == PHY_INTERFACE_MODE_2500BASEX) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {

4
board/freescale/ls1046aqds/eth.c
View File

@@ -178,7 +178,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
default:
break;
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
/* 2.5G SGMII interface */
f_link.phy_id = cpu_to_fdt32(port);
f_link.duplex = cpu_to_fdt32(1);
@@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
"sgmii-2500");
"2500base-x");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:

6
board/freescale/t102xrdb/eth_t102xrdb.c
View File

@@ -103,7 +103,7 @@ int board_eth_init(struct bd_info *bis)
#endif
fm_info_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_2500BASEX:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
@@ -133,12 +133,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
#if defined(CONFIG_TARGET_T1024RDB)
if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) ||
(fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
(port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop_string(fdt, offset, "phy-connection-type",
"sgmii-2500");
"2500base-x");
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
#endif

10
drivers/net/fm/eth.c
View File

@@ -50,7 +50,7 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
u32 value;
struct mii_dev bus;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
PHY_INTERFACE_MODE_2500BASEX) ? true : false;
int i = 0, j;
#ifndef CONFIG_DM_ETH
@@ -133,7 +133,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth)
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
dtsec_configure_serdes(fm_eth);
}
@@ -432,7 +432,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
/* For some reason we need to set SPEED_100 */
if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) ||
(fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
@@ -829,7 +829,7 @@ static int init_phy(struct fm_eth *fm_eth)
if (fm_eth->type == FM_ETH_10G_E)
supported = PHY_10G_FEATURES;
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
if (fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
supported |= SUPPORTED_2500baseX_Full;
#endif
@@ -1090,7 +1090,7 @@ static int fm_eth_probe(struct udevice *dev)
if (fm_eth->num != 0)
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_2500BASEX:
fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
break;
default:

4
drivers/net/fm/ls1043.c
View File

@@ -79,7 +79,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
case FM1_DTSEC2:
if ((port == FM1_DTSEC2) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC2))
return PHY_INTERFACE_MODE_SGMII_2500;
return PHY_INTERFACE_MODE_2500BASEX;
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
@@ -87,7 +87,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
else if ((port == FM1_DTSEC9) &&
is_serdes_configured(SGMII_2500_FM1_DTSEC9))
return PHY_INTERFACE_MODE_SGMII_2500;
return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;

2
drivers/net/fm/ls1046.c
View File

@@ -99,7 +99,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
port - FM1_DTSEC5))
return PHY_INTERFACE_MODE_SGMII_2500;
return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;

2
drivers/net/fm/memac.c
View File

@@ -93,7 +93,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac,
if_mode |= (IF_MODE_GMII | IF_MODE_RM);
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
if_mode &= ~IF_MODE_MASK;
if_mode |= (IF_MODE_GMII);

2
drivers/net/fm/t1024.c
View File

@@ -63,7 +63,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
return PHY_INTERFACE_MODE_SGMII;
else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
+ port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII_2500;
return PHY_INTERFACE_MODE_2500BASEX;
break;
default:
break;

4
drivers/net/fsl_enetc.c
View File

@@ -144,7 +144,7 @@ static int enetc_init_sgmii(struct udevice *dev)
if (!enetc_has_imdio(dev))
return 0;
if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
if (priv->if_type == PHY_INTERFACE_MODE_2500BASEX)
is2500 = true;
/*
@@ -291,7 +291,7 @@ static void enetc_start_pcs(struct udevice *dev)
switch (priv->if_type) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_2500BASEX:
enetc_init_sgmii(dev);
break;
case PHY_INTERFACE_MODE_XGMII:

4
drivers/net/mscc_eswitch/felix_switch.c
View File

@@ -213,12 +213,12 @@ static void felix_start_pcs(struct udevice *dev, int port,
bool autoneg = true;
if (phy->phy_id == PHY_FIXED_ID ||
phy->interface == PHY_INTERFACE_MODE_SGMII_2500)
phy->interface == PHY_INTERFACE_MODE_2500BASEX)
autoneg = false;
switch (phy->interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
felix_init_sgmii(imdio, port, autoneg);
break;

4
drivers/net/pfe_eth/pfe_mdio.c
View File

@@ -161,7 +161,7 @@ static void pfe_configure_serdes(struct pfe_eth_dev *priv)
int value, sgmii_2500 = 0;
struct gemac_s *gem = priv->gem;
if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX)
sgmii_2500 = 1;
@@ -220,7 +220,7 @@ int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
/* Configure SGMII PCS */
if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
out_be32(&scfg->mdioselcr, 0x00000000);
pfe_configure_serdes(priv);
}

4
drivers/net/phy/aquantia.c
View File

@@ -308,7 +308,7 @@ struct {
} aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
[PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
AQUANTIA_VND1_GSTART_RATE_1G},
[PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
[PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
AQUANTIA_VND1_GSTART_RATE_2_5G},
[PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
AQUANTIA_VND1_GSTART_RATE_10G},
@@ -522,7 +522,7 @@ int aquantia_config(struct phy_device *phydev)
phy_write(phydev, MDIO_MMD_PHYXS,
AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
break;
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_2500BASEX:
/* 2.5GBASE-T mode */
phydev->advertising = SUPPORTED_1000baseT_Full;
phydev->supported = phydev->advertising;