pinctrl: single: add get_pin_muxing operation
It allows to display the muxing of a given pin. Inspired by more recent versions of the Linux driver, in addition to the address and the value of the configuration register I added the pin function retrieved from the DT. In doing so, the information displayed does not depend on the platform, being a generic type driver, and it can be useful for debug purposes. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
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0b12162910
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76d470de1a
@ -1,14 +1,18 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
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* Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <dm/pinctrl.h>
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#include <linux/libfdt.h>
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#include <linux/list.h>
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#include <asm/io.h>
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#include <sort.h>
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/**
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* struct single_pdata - platform data
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@ -26,6 +30,20 @@ struct single_pdata {
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bool bits_per_mux;
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};
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/**
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* struct single_func - pinctrl function
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* @node: list node
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* @name: pinctrl function name
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* @npins: number of entries in pins array
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* @pins: pins array
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*/
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struct single_func {
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struct list_head node;
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const char *name;
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unsigned int npins;
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unsigned int *pins;
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};
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/**
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* struct single_priv - private data
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* @bits_per_pin: number of bits per pin
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@ -36,6 +54,7 @@ struct single_priv {
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unsigned int bits_per_pin;
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unsigned int npins;
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char pin_name[PINNAME_SIZE];
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struct list_head functions;
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};
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/**
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@ -100,6 +119,121 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
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}
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}
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/**
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* single_get_pin_by_offset() - get a pin based on the register offset
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* @dev: single driver instance
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* @offset: register offset from the base
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*/
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static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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struct single_priv *priv = dev_get_priv(dev);
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if (offset > pdata->offset) {
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dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n",
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offset, pdata->offset);
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return -EINVAL;
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}
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if (pdata->bits_per_mux)
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return (offset * BITS_PER_BYTE) / priv->bits_per_pin;
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return offset / (pdata->width / BITS_PER_BYTE);
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}
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static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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struct single_priv *priv = dev_get_priv(dev);
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unsigned int mux_bytes;
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if (pin >= priv->npins)
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return -EINVAL;
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mux_bytes = pdata->width / BITS_PER_BYTE;
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if (pdata->bits_per_mux) {
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int byte_num;
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byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE;
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return (byte_num / mux_bytes) * mux_bytes;
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}
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return pin * mux_bytes;
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}
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static const char *single_get_pin_function(struct udevice *dev,
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unsigned int pin)
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{
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struct single_priv *priv = dev_get_priv(dev);
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struct single_func *func;
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int i;
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list_for_each_entry(func, &priv->functions, node) {
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for (i = 0; i < func->npins; i++) {
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if (pin == func->pins[i])
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return func->name;
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if (pin < func->pins[i])
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break;
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}
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}
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return NULL;
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}
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static int single_get_pin_muxing(struct udevice *dev, unsigned int pin,
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char *buf, int size)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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struct single_priv *priv = dev_get_priv(dev);
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fdt_addr_t reg;
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const char *fname;
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unsigned int val;
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int offset, pin_shift = 0;
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offset = single_get_offset_by_pin(dev, pin);
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if (offset < 0)
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return offset;
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reg = pdata->base + offset;
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val = single_read(dev, reg);
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if (pdata->bits_per_mux)
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pin_shift = pin % (pdata->width / priv->bits_per_pin) *
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priv->bits_per_pin;
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val &= (pdata->mask << pin_shift);
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fname = single_get_pin_function(dev, pin);
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snprintf(buf, size, "%pa 0x%08x %s", ®, val,
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fname ? fname : "UNCLAIMED");
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return 0;
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}
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static struct single_func *single_allocate_function(struct udevice *dev,
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unsigned int group_pins)
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{
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struct single_func *func;
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func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL);
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if (!func)
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return ERR_PTR(-ENOMEM);
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func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins,
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GFP_KERNEL);
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if (!func->pins)
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return ERR_PTR(-ENOMEM);
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return func;
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}
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static int single_pin_compare(const void *s1, const void *s2)
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{
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int pin1 = *(const unsigned int *)s1;
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int pin2 = *(const unsigned int *)s2;
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return pin1 - pin2;
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}
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/**
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* single_configure_pins() - Configure pins based on FDT data
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*
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@ -113,13 +247,16 @@ static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
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* @size: Size of the 'pins' array in bytes.
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* The number of register/value pairs in the 'pins' array therefore
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* equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
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* @fname: Function name.
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*/
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static int single_configure_pins(struct udevice *dev,
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const struct single_fdt_pin_cfg *pins,
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int size)
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int size, const char *fname)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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int n, count = size / sizeof(struct single_fdt_pin_cfg);
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struct single_priv *priv = dev_get_priv(dev);
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int n, pin, count = size / sizeof(struct single_fdt_pin_cfg);
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struct single_func *func;
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phys_addr_t reg;
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u32 offset, val;
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@ -127,33 +264,61 @@ static int single_configure_pins(struct udevice *dev,
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if (!pdata->mask)
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return 0;
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func = single_allocate_function(dev, count);
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if (IS_ERR(func))
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return PTR_ERR(func);
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func->name = fname;
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func->npins = 0;
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for (n = 0; n < count; n++, pins++) {
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offset = fdt32_to_cpu(pins->reg);
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if (offset < 0 || offset > pdata->offset) {
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dev_dbg(dev, " invalid register offset 0x%x\n",
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dev_err(dev, " invalid register offset 0x%x\n",
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offset);
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continue;
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}
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reg = pdata->base + offset;
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val = fdt32_to_cpu(pins->val) & pdata->mask;
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pin = single_get_pin_by_offset(dev, offset);
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if (pin < 0) {
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dev_err(dev, " failed to get pin by offset %x\n",
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offset);
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continue;
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}
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single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val,
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reg);
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dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
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func->pins[func->npins] = pin;
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func->npins++;
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}
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qsort(func->pins, func->npins, sizeof(func->pins[0]),
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single_pin_compare);
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list_add(&func->node, &priv->functions);
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return 0;
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}
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static int single_configure_bits(struct udevice *dev,
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const struct single_fdt_bits_cfg *pins,
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int size)
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int size, const char *fname)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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int n, count = size / sizeof(struct single_fdt_bits_cfg);
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struct single_priv *priv = dev_get_priv(dev);
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int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
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int npins_in_reg, pin_num_from_lsb;
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struct single_func *func;
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phys_addr_t reg;
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u32 offset, val, mask;
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u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
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npins_in_reg = pdata->width / priv->bits_per_pin;
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func = single_allocate_function(dev, count * npins_in_reg);
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if (IS_ERR(func))
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return PTR_ERR(func);
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func->name = fname;
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func->npins = 0;
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for (n = 0; n < count; n++, pins++) {
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offset = fdt32_to_cpu(pins->reg);
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if (offset < 0 || offset > pdata->offset) {
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@ -164,11 +329,47 @@ static int single_configure_bits(struct udevice *dev,
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reg = pdata->base + offset;
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pin = single_get_pin_by_offset(dev, offset);
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if (pin < 0) {
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dev_err(dev, " failed to get pin by offset 0x%pa\n",
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®);
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continue;
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}
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mask = fdt32_to_cpu(pins->mask);
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val = fdt32_to_cpu(pins->val) & mask;
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single_write(dev, (single_read(dev, reg) & ~mask) | val, reg);
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dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
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while (mask) {
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bit_pos = __ffs(mask);
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pin_num_from_lsb = bit_pos / priv->bits_per_pin;
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mask_pos = pdata->mask << bit_pos;
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val_pos = val & mask_pos;
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submask = mask & mask_pos;
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if ((mask & mask_pos) == 0) {
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dev_err(dev, "Invalid mask at 0x%x\n", offset);
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break;
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}
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mask &= ~mask_pos;
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if (submask != mask_pos) {
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dev_warn(dev,
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"Invalid submask 0x%x at 0x%x\n",
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submask, offset);
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continue;
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}
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func->pins[func->npins] = pin + pin_num_from_lsb;
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func->npins++;
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}
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}
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qsort(func->pins, func->npins, sizeof(func->pins[0]),
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single_pin_compare);
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list_add(&func->node, &priv->functions);
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return 0;
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}
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static int single_set_state(struct udevice *dev,
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@ -186,7 +387,7 @@ static int single_set_state(struct udevice *dev,
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dev_dbg(dev, " invalid pin configuration in fdt\n");
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return -FDT_ERR_BADSTRUCTURE;
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}
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single_configure_pins(dev, prop, len);
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single_configure_pins(dev, prop, len, config->name);
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return 0;
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}
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@ -198,7 +399,7 @@ static int single_set_state(struct udevice *dev,
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dev_dbg(dev, " invalid bits configuration in fdt\n");
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return -FDT_ERR_BADSTRUCTURE;
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}
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single_configure_bits(dev, prop_bits, len);
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single_configure_bits(dev, prop_bits, len, config->name);
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return 0;
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}
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@ -232,6 +433,8 @@ static int single_probe(struct udevice *dev)
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struct single_priv *priv = dev_get_priv(dev);
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u32 size;
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INIT_LIST_HEAD(&priv->functions);
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size = pdata->offset + pdata->width / BITS_PER_BYTE;
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priv->npins = size / (pdata->width / BITS_PER_BYTE);
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if (pdata->bits_per_mux) {
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@ -296,6 +499,7 @@ const struct pinctrl_ops single_pinctrl_ops = {
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.get_pins_count = single_get_pins_count,
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.get_pin_name = single_get_pin_name,
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.set_state = single_set_state,
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.get_pin_muxing = single_get_pin_muxing,
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};
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static const struct udevice_id single_pinctrl_match[] = {
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