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arm: imx-common: init: extend init_aips to support imx7

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Extend init_aips to support imx7 SoC, use is_soc_type
and is_cpu_type to resolve at run time aips3 settings

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
This commit is contained in:
Adrian Alonso 2015-09-02 13:54:20 -05:00 committed by Stefano Babic
parent c5752f73a5
commit 75a565f297
1 changed files with 20 additions and 24 deletions
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44
arch/arm/imx-common/init.c
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@ -13,16 +13,11 @@
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
struct aipstz_regs *aips3;
#endif
struct aipstz_regs *aips1, *aips2, *aips3;
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
#endif
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
@ -49,25 +44,26 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
#ifdef CONFIG_MX6SX
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips3->mprot0);
writel(0x77777777, &aips3->mprot1);
if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
{
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips3->mprot0);
writel(0x77777777, &aips3->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips3->opacr0);
writel(0x00000000, &aips3->opacr1);
writel(0x00000000, &aips3->opacr2);
writel(0x00000000, &aips3->opacr3);
writel(0x00000000, &aips3->opacr4);
#endif
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips3->opacr0);
writel(0x00000000, &aips3->opacr1);
writel(0x00000000, &aips3->opacr2);
writel(0x00000000, &aips3->opacr3);
writel(0x00000000, &aips3->opacr4);
}
}
#define SRC_SCR_WARM_RESET_ENABLE 0