imx: imx7d: Add SoC system support
Add imx7d basic SoC system support Misc arch dependent functions for system bring up Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
This commit is contained in:
Adrian Alonso
Stefano Babic
parent
7bebc4b04e
commit
c5752f73a5
269
arch/arm/cpu/armv7/mx7/soc.c
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269
arch/arm/cpu/armv7/mx7/soc.c
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@ -0,0 +1,269 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/dma.h>
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#include <asm/arch/crm_regs.h>
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#include <dm.h>
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#include <imx_thermal.h>
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struct src *src_reg = (struct src *)SRC_BASE_ADDR;
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#if defined(CONFIG_IMX_THERMAL)
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static const struct imx_thermal_plat imx7_thermal_plat = {
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.regs = (void *)ANATOP_BASE_ADDR,
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.fuse_bank = 3,
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.fuse_word = 3,
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};
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U_BOOT_DEVICE(imx7_thermal) = {
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.name = "imx_thermal",
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.platdata = &imx7_thermal_plat,
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};
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#endif
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/*
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* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
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* defines a 2-bit SPEED_GRADING
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*/
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#define OCOTP_TESTER3_SPEED_SHIFT 8
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#define OCOTP_TESTER3_SPEED_800MHZ 0
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#define OCOTP_TESTER3_SPEED_850MHZ 1
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#define OCOTP_TESTER3_SPEED_1GHZ 2
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u32 get_cpu_speed_grade_hz(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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uint32_t val;
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val = readl(&fuse->tester3);
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val >>= OCOTP_TESTER3_SPEED_SHIFT;
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val &= 0x3;
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switch(val) {
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case OCOTP_TESTER3_SPEED_800MHZ:
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return 792000000;
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case OCOTP_TESTER3_SPEED_850MHZ:
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return 852000000;
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case OCOTP_TESTER3_SPEED_1GHZ:
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return 996000000;
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}
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return 0;
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}
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/*
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* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
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* defines a 2-bit SPEED_GRADING
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*/
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#define OCOTP_TESTER3_TEMP_SHIFT 6
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u32 get_cpu_temp_grade(int *minc, int *maxc)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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uint32_t val;
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val = readl(&fuse->tester3);
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val >>= OCOTP_TESTER3_TEMP_SHIFT;
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val &= 0x3;
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if (minc && maxc) {
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if ( val == TEMP_AUTOMOTIVE) {
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*minc = -40;
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*maxc = 125;
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} else if (val == TEMP_INDUSTRIAL) {
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*minc = -40;
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*maxc = 105;
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} else if (val == TEMP_EXTCOMMERCIAL) {
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*minc = -20;
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*maxc = 105;
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} else {
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*minc = 0;
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*maxc = 95;
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}
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}
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return val;
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}
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u32 get_cpu_rev(void)
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{
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struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
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ANATOP_BASE_ADDR;
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u32 reg = readl(&ccm_anatop->digprog);
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u32 type = (reg >> 16) & 0xff;
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reg &= 0xff;
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return (type << 12) | reg;
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}
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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return get_cpu_rev();
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}
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#endif
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int arch_cpu_init(void)
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{
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init_aips();
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/* Disable PDE bit of WMCR register */
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imx_set_wdog_powerdown(false);
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#ifdef CONFIG_APBH_DMA
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/* Start APBH DMA */
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mxs_dma_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_SERIAL_TAG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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serialnr->low = fuse->tester0;
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serialnr->high = fuse->tester1;
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}
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#endif
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#if defined(CONFIG_FEC_MXC)
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[9];
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struct fuse_bank9_regs *fuse =
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(struct fuse_bank9_regs *)bank->fuse_regs;
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if (0 == dev_id) {
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u32 value = readl(&fuse->mac_addr1);
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mac[0] = (value >> 8);
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mac[1] = value;
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value = readl(&fuse->mac_addr0);
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mac[2] = value >> 24;
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mac[3] = value >> 16;
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mac[4] = value >> 8;
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mac[5] = value;
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} else {
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u32 value = readl(&fuse->mac_addr2);
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mac[0] = value >> 24;
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mac[1] = value >> 16;
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mac[2] = value >> 8;
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mac[3] = value;
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value = readl(&fuse->mac_addr1);
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mac[4] = value >> 24;
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mac[5] = value >> 16;
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}
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}
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#endif
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void set_wdog_reset(struct wdog_regs *wdog)
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{
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u32 reg = readw(&wdog->wcr);
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/*
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* Output WDOG_B signal to reset external pmic or POR_B decided by
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* the board desgin. Without external reset, the peripherals/DDR/
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* PMIC are not reset, that may cause system working abnormal.
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*/
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reg = readw(&wdog->wcr);
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reg |= 1 << 3;
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/*
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* WDZST bit is write-once only bit. Align this bit in kernel,
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* otherwise kernel code will have no chance to set this bit.
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*/
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reg |= 1 << 0;
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writew(reg, &wdog->wcr);
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}
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/*
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* cfg_val will be used for
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* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
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* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
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* to SBMR1, which will determine the boot device.
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*/
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const struct boot_mode soc_boot_modes[] = {
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{"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
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{"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
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{"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
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{"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
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{"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
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{"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
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/* 4 bit bus width */
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{"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
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{"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
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{"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
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{"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
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{"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
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{"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
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{NULL, 0},
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};
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enum boot_device get_boot_device(void)
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{
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struct bootrom_sw_info **p =
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
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enum boot_device boot_dev = SD1_BOOT;
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u8 boot_type = (*p)->boot_dev_type;
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u8 boot_instance = (*p)->boot_dev_instance;
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switch (boot_type) {
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case BOOT_TYPE_SD:
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boot_dev = boot_instance + SD1_BOOT;
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break;
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case BOOT_TYPE_MMC:
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boot_dev = boot_instance + MMC1_BOOT;
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break;
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case BOOT_TYPE_NAND:
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boot_dev = NAND_BOOT;
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break;
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case BOOT_TYPE_QSPI:
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boot_dev = QSPI_BOOT;
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break;
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case BOOT_TYPE_WEIM:
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boot_dev = WEIM_NOR_BOOT;
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break;
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case BOOT_TYPE_SPINOR:
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boot_dev = SPI_NOR_BOOT;
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break;
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default:
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break;
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}
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return boot_dev;
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}
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void s_init(void)
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{
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#if !defined CONFIG_SPL_BUILD
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/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #1 << 6\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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#endif
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/* clock configuration. */
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clock_init();
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return;
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}
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@ -21,9 +21,11 @@
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#define MXC_CPU_MX6D 0x67
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#define MXC_CPU_MX6DP 0x68
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#define MXC_CPU_MX6QP 0x69
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#define MXC_CPU_MX7D 0x72
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#define MXC_CPU_VF610 0xF6 /* dummy ID */
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#define MXC_SOC_MX6 0x60
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#define MXC_SOC_MX7 0x70
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#define CS0_128 0
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#define CS0_64M_CS1_64M 1
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@ -9,6 +9,27 @@
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#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
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((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
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enum boot_device {
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WEIM_NOR_BOOT,
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ONE_NAND_BOOT,
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PATA_BOOT,
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SATA_BOOT,
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I2C_BOOT,
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SPI_NOR_BOOT,
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SD1_BOOT,
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SD2_BOOT,
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SD3_BOOT,
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SD4_BOOT,
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MMC1_BOOT,
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MMC2_BOOT,
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MMC3_BOOT,
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MMC4_BOOT,
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NAND_BOOT,
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QSPI_BOOT,
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UNKNOWN_BOOT,
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BOOT_DEV_NUM = UNKNOWN_BOOT,
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};
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struct boot_mode {
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const char *name;
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unsigned cfg_val;
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