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* Patches by Denis Peter, 9 Sep 2003:

Browse Source 
add FAT support for IDE, SCSI and USB

* Patches by Gleb Natapov, 2 Sep 2003:
  - cleanup of POST code for unsupported architectures
  - MPC824x locks way0 of data cache for use as initial RAM;
    this patch unlocks it after relocation to RAM and invalidates
    the locked entries.

* Patch by Gleb Natapov, 30 Aug 2003:
  new I2C driver for mpc107 bridge. Now works from flash.

* Patch by Dave Ellis, 11 Aug 2003:
  - JFFS2: fix typo in common/cmd_jffs2.c
  - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
  - JFFS2: remove node version 0 warning
  - JFFS2: accept JFFS2 PADDING nodes
  - SXNI855T: add AM29LV800 support
  - SXNI855T: move environment from EEPROM to flash
  - SXNI855T: boot from JFFS2 in NOR or NAND flash

* Patch by Bill Hargen, 11 Aug 2003:
  fixes for I2C on MPC8240
  - fix i2c_write routine
  - fix iprobe command
  - eliminates use of global variables, plus dead code, cleanup.
This commit is contained in:
wdenk
2003-09-10 22:30:53 +00:00
parent 149dded2b1
commit 7205e4075d
47 changed files with 1269 additions and 2474 deletions
Download Patch File Download Diff File Expand all files Collapse all files

133
board/mpl/common/common_util.c
View File

@@ -375,138 +375,6 @@ void show_stdio_dev(void)
}
}
/* ------------------------------------------------------------------------- */
/* switches the cs0 and the cs1 to the locations.
When boot is TRUE, the the mapping is switched
to the boot configuration, If it is FALSE, the
flash will be switched in the boot area */
#undef SW_CS_DBG
#ifdef SW_CS_DBG
#define SW_CS_PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define SW_CS_PRINTF(fmt,args...)
#endif
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
int switch_cs(unsigned char boot)
{
unsigned long pbcr;
int mode;
mode=get_boot_mode();
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
if (mode & BOOT_MPS) {
/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
/* we need only to switch if boot from MPS */
/* printf(" MPS boot mode detected. ");*/
/* printf("cs0 cfg: %lx\n",pbcr); */
if(boot) {
/* switch to boot configuration */
/* this is a 8bit boot, switch cs0 to flash location */
SW_CS_PRINTF("switch to boot mode (MPS on High address\n");
pbcr&=0x000FFFFF; /*mask base address of the cs0 */
pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
SW_CS_PRINTF(" new cs0 cfg: %lx\n",pbcr);
mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
pbcr = mfdcr(ebccfgd);
SW_CS_PRINTF(" old cs1 cfg: %lx\n",pbcr);
pbcr&=0x000FFFFF; /*mask base address of the cs1 */
pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
mtdcr(ebccfga, pb1cr);
mtdcr(ebccfgd, pbcr);
SW_CS_PRINTF(" new cs1 cfg: %lx, MPS is on High Address\n",pbcr);
}
else {
/* map flash to boot area, */
SW_CS_PRINTF("map Flash to boot area\n");
pbcr&=0x000FFFFF; /*mask base address of the cs0 */
pbcr|=(MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
SW_CS_PRINTF(" new cs0 cfg: %lx\n",pbcr);
mtdcr(ebccfga, pb1cr); /* get cs1 config reg (flash) */
pbcr = mfdcr(ebccfgd);
SW_CS_PRINTF(" cs1 cfg: %lx\n",pbcr);
pbcr&=0x000FFFFF; /*mask base address of the cs1 */
pbcr|=(FLASH_BASE0_PRELIM & 0xFFF00000);
mtdcr(ebccfga, pb1cr);
mtdcr(ebccfgd, pbcr);
SW_CS_PRINTF(" new cs1 cfg: %lx Flash is on High Address\n",pbcr);
}
return 1;
}
else {
SW_CS_PRINTF("Normal boot, no switching necessary\n");
return 0;
}
}
int get_boot_mode(void)
{
unsigned long pbcr;
int res = 0;
pbcr = mfdcr (strap);
if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
/* boot via MPS or MPS mapping */
res = BOOT_MPS;
if(pbcr & PSR_ROM_LOC)
/* boot via PCI.. */
res |= BOOT_PCI;
return res;
}
/* Setup cs0 parameter finally.
Map the flash high (in boot area)
This code can only be executed from SDRAM (after relocation).
*/
void setup_cs_reloc(void)
{
unsigned long pbcr;
/* Since we are relocated, we can set-up the CS finaly
* but first of all, switch off PCI mapping (in case it was a PCI boot) */
out32r(PMM0MA,0L);
icache_enable (); /* we are relocated */
/* for PCI Boot, we have to set-up the remaining CS correctly */
pbcr = mfdcr (strap);
if(pbcr & PSR_ROM_LOC) {
/* boot via PCI.. */
if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) {
/* Boot width = 8 bit MPS Boot, set up MPS on CS0 */
#ifdef DEBUG
printf("Mapping MPS to CS0 @ 0x%lx\n",(MPS_CR_B & 0xfff00000));
#endif
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, MPS_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, MPS_CR_B);
}
else {
/* Flash boot, set up the Flash on CS0 */
#ifdef DEBUG
printf("Mapping Flash to CS0 @ 0x%lx\n",(FLASH_CR_B & 0xfff00000));
#endif
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, FLASH_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, FLASH_CR_B);
}
}
switch_cs(0); /* map Flash High */
}
#elif defined(CONFIG_VCMA9)
int switch_cs(unsigned char boot)
{
return 0;
}
#endif /* CONFIG_VCMA9 */
int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
@@ -625,6 +493,7 @@ void doc_init (void)
#ifdef CONFIG_CONSOLE_EXTRA_INFO
extern GraphicDevice ctfb;
extern int get_boot_mode(void);
void video_get_info_str (int line_number, char *info)
{

4
board/mpl/common/common_util.h
View File

@@ -31,10 +31,8 @@ typedef struct {
} backup_t;
void get_backup_values(backup_t *buf);
int switch_cs(unsigned char boot);
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
int get_boot_mode(void);
void setup_cs_reloc(void);
#define BOOT_MPS 0x01
#define BOOT_PCI 0x02
#endif

155
board/mpl/common/flash.c
View File

@@ -39,6 +39,13 @@
#include <ppc4xx.h>
#include <asm/processor.h>
#include "common_util.h"
#if defined(CONFIG_MIP405)
#include "../mip405/mip405.h"
#endif
#if defined(CONFIG_PIP405)
#include "../pip405/pip405.h"
#endif
#include <405gp_pci.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
@@ -66,23 +73,102 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
#define TRUE 1
/*-----------------------------------------------------------------------
* Some CS switching routines:
*
* On PIP/MIP405 we have 3 (4) possible boot mode
*
* - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
* - Boot from MPS (Flash CS = CS1, MPS CS = CS0)
* - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
* - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0)
* The flash init is the first board specific routine which is called
* after code relocation (running from SDRAM)
* The first thing we do is to map the Flash CS to the Flash area and
* the MPS CS to the MPS area. Since the flash size is unknown at this
* point, we use the max flash size and the lowest flash address as base.
*
* After flash detection we adjust the size of the CS area accordingly.
* The board_init_r will fill in wrong values in the board init structure,
* but this will be fixed in the misc_init_r routine:
* bd->bi_flashstart=0-flash_info[0].size
* bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
* bd->bi_flashoffset=0
*
*/
int get_boot_mode(void)
{
unsigned long pbcr;
int res = 0;
pbcr = mfdcr (strap);
if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
/* boot via MPS or MPS mapping */
res = BOOT_MPS;
if(pbcr & PSR_ROM_LOC)
/* boot via PCI.. */
res |= BOOT_PCI;
return res;
}
/* Map the flash high (in boot area)
This code can only be executed from SDRAM (after relocation).
*/
void setup_cs_reloc(void)
{
int mode;
/* Since we are relocated, we can set-up the CS finaly
* but first of all, switch off PCI mapping (in case it was a PCI boot) */
out32r(PMM0MA,0L);
icache_enable (); /* we are relocated */
/* get boot mode */
mode=get_boot_mode();
/* we map the flash high in every case */
/* first findout on which cs the flash is */
if(mode & BOOT_MPS) {
/* map flash high on CS1 and MPS on CS0 */
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, MPS_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, MPS_CR);
/* we use the default values (max values) for the flash
* because its real size is not yet known */
mtdcr (ebccfga, pb1ap);
mtdcr (ebccfgd, FLASH_AP);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, FLASH_CR_B);
}
else {
/* map flash high on CS0 and MPS on CS1 */
mtdcr (ebccfga, pb1ap);
mtdcr (ebccfgd, MPS_AP);
mtdcr (ebccfga, pb1cr);
mtdcr (ebccfgd, MPS_CR);
/* we use the default values (max values) for the flash
* because its real size is not yet known */
mtdcr (ebccfga, pb0ap);
mtdcr (ebccfgd, FLASH_AP);
mtdcr (ebccfga, pb0cr);
mtdcr (ebccfgd, FLASH_CR_B);
}
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
unsigned long size_b0, size_b1,flashcr;
int mode, i;
extern char version_string;
char *p=&version_string;
/* Since we are relocated, we can set-up the CS finally */
setup_cs_reloc();
/* get and display boot mode */
i=get_boot_mode();
if(i & BOOT_PCI)
printf("(PCI Boot %s Map) ",(i & BOOT_MPS) ?
mode=get_boot_mode();
if(mode & BOOT_PCI)
printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ?
"MPS" : "Flash");
else
printf("(%s Boot) ",(i & BOOT_MPS) ?
printf("(%s Boot) ",(mode & BOOT_MPS) ?
"MPS" : "Flash");
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@@ -91,7 +177,7 @@ unsigned long flash_init (void)
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -109,8 +195,31 @@ unsigned long flash_init (void)
flash_info[0].protect[flash_info[0].sector_count-1] = 1;
size_b1 = 0 ;
flash_info[0].size = size_b0;
/* set up flash cs according to the size */
if(mode & BOOT_MPS) {
/* flash is on CS1 */
mtdcr(ebccfga, pb1cr);
flashcr = mfdcr (ebccfgd);
/* we map the flash high in every case */
flashcr&=0x0001FFFF; /* mask out address bits */
flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
mtdcr(ebccfga, pb1cr);
mtdcr(ebccfgd, flashcr);
}
else {
/* flash is on CS0 */
mtdcr(ebccfga, pb0cr);
flashcr = mfdcr (ebccfgd);
/* we map the flash high in every case */
flashcr&=0x0001FFFF; /* mask out address bits */
flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, flashcr);
}
#if 0
/* include this if you want to test if
/* enable this if you want to test if
the relocation has be done ok.
This will disable both Chipselects */
mtdcr (ebccfga, pb0cr);
@@ -119,6 +228,14 @@ unsigned long flash_init (void)
mtdcr (ebccfgd, 0L);
printf("CS0 & CS1 switched off for test\n");
#endif
/* patch version_string */
for(i=0;i<0x100;i++) {
if(*p=='\n') {
*p=0;
break;
}
p++;
}
return (size_b0);
}
@@ -171,6 +288,8 @@ void flash_print_info (flash_info_t *info)
break;
case FLASH_INTEL320T: printf ("TE28F320C3 (32 Mbit, top sector size)\n");
break;
case FLASH_AM640U: printf ("AM29LV640U (64 Mbit, uniform sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
@@ -211,7 +330,8 @@ void flash_print_info (flash_info_t *info)
/*-----------------------------------------------------------------------
*/
*/
/*
* The following code cannot be run from FLASH!
@@ -220,7 +340,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
ulong base;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
@@ -250,7 +370,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
return (0); /* no or unknown flash */
}
value = addr2[1]; /* device ID */
/* printf("Device value %x\n",value); */
/* printf("Device value %x\n",value); */
switch (value) {
case (FLASH_WORD_SIZE)AMD_ID_F040B:
info->flash_id += FLASH_AM040;
@@ -292,12 +412,17 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
#if 0 /* enable when device IDs are available */
case (FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (FLASH_WORD_SIZE)AMD_ID_LV640U:
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x00800000;
break; /* => 8 MB */
#if 0 /* enable when device IDs are available */
case (FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
@@ -328,10 +453,12 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
return (0); /* => no or unknown flash */
}
/* base address calculation */
base=0-info->size;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)){
(info->flash_id == FLASH_AM040) ||
(info->flash_id == FLASH_AM640U)){
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
}

75
board/mpl/common/isa.c
View File

@@ -32,7 +32,6 @@
#include "kbd.h"
#include "video.h"
extern int drv_isa_kbd_init (void);
#undef ISA_DEBUG
@@ -49,6 +48,9 @@ extern int drv_isa_kbd_init (void);
#define FALSE 0
#endif
#if defined(CONFIG_PIP405)
extern int drv_isa_kbd_init (void);
/* fdc (logical device 0) */
const SIO_LOGDEV_TABLE sio_fdc[] = {
@@ -183,7 +185,7 @@ void isa_sio_setup(void)
close_cfg_super_IO(0x3F0);
}
}
#endif
/******************************************************************************
* IRQ Controller
@@ -202,7 +204,7 @@ static struct isa_irq_action isa_irqs[16];
/*
* This contains the irq mask for both 8259A irq controllers,
*/
static unsigned int cached_irq_mask = 0xffff;
static unsigned int cached_irq_mask = 0xfff9;
#define cached_imr1 (unsigned char)cached_irq_mask
#define cached_imr2 (unsigned char)(cached_irq_mask>>8)
@@ -387,19 +389,22 @@ int handle_isa_int(void)
isr2=in8(ISR_2);
isr1=in8(ISR_1);
irq=(unsigned char)irqack;
if((irq==7)&&((isr1&0x80)==0)) {
irq-=32;
/* if((irq==7)&&((isr1&0x80)==0)) {
PRINTF("IRQ7 detected but not in ISR\n");
}
else {
/* we should handle cascaded interrupts here also */
/* printf("ISA Irq %d\n",irq); */
isa_irqs[irq].count++;
if (isa_irqs[irq].handler != NULL)
(*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */
else
*/ /* we should handle cascaded interrupts here also */
{
PRINTF ("bogus interrupt vector 0x%x\n", irq);
}
/* printf("ISA Irq %d\n",irq); */
isa_irqs[irq].count++;
if(irq!=2) { /* just swallow the cascade irq 2 */
if (isa_irqs[irq].handler != NULL)
(*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */
else {
PRINTF ("bogus interrupt vector 0x%x\n", irq);
}
}
}
/* issue EOI instruction to clear the IRQ */
mask_and_ack_8259A(irq);
@@ -413,13 +418,13 @@ int handle_isa_int(void)
void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
{
if (isa_irqs[vec].handler != NULL) {
printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
vec, (uint)handler, (uint)isa_irqs[vec].handler);
}
isa_irqs[vec].handler = handler;
isa_irqs[vec].arg = arg;
enable_8259A_irq(vec);
if (isa_irqs[vec].handler != NULL) {
printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
vec, (uint)handler, (uint)isa_irqs[vec].handler);
}
isa_irqs[vec].handler = handler;
isa_irqs[vec].arg = arg;
enable_8259A_irq(vec);
PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
}
@@ -427,9 +432,9 @@ void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
void isa_irq_free_handler(int vec)
{
disable_8259A_irq(vec);
isa_irqs[vec].handler = NULL;
isa_irqs[vec].arg = NULL;
printf ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
isa_irqs[vec].handler = NULL;
isa_irqs[vec].arg = NULL;
PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
}
@@ -448,16 +453,42 @@ void isa_init_irq_contr(void)
init_8259A();
out8(IMR_2,0xFF);
}
/*************************************************************************/
void isa_show_irq(void)
{
int vec;
printf ("\nISA Interrupt-Information:\n");
printf ("Nr Routine Arg Count\n");
for (vec=0; vec<16; vec++) {
if (isa_irqs[vec].handler != NULL) {
printf ("%02d %08lx %08lx %d\n",
vec,
(ulong)isa_irqs[vec].handler,
(ulong)isa_irqs[vec].arg,
isa_irqs[vec].count);
}
}
}
int isa_irq_get_count(int vec)
{
return(isa_irqs[vec].count);
}
/******************************************************************
* Init the ISA bus and devices.
*/
#if defined(CONFIG_PIP405)
int isa_init(void)
{
isa_sio_setup();
isa_init_irq_contr();
drv_isa_kbd_init();
return 0;
}
#endif

12
board/mpl/common/isa.h
View File

@@ -21,12 +21,12 @@
* MA 02111-1307 USA
*/
#ifndef _PIP405_ISA_H_
#define _PIP405_ISA_H_
#ifndef _ISA_H_
#define _ISA_H_
/* Super IO */
#define SIO_CFG_PORT 0x3F0 /* Config Port Address */
#if defined(CONFIG_PIP405)
/* table fore SIO initialization */
typedef struct {
const uchar index;
@@ -44,10 +44,14 @@ unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned ch
void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
void close_cfg_super_IO(int address);
void isa_sio_setup(void);
void isa_sio_setup(void);
#endif
void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
void isa_irq_free_handler(int vec);
int handle_isa_int(void);
void isa_init_irq_contr(void);
void isa_show_irq(void);
int isa_irq_get_count(int vec);
#endif

9
board/mpl/common/pci_parts.h
View File

@@ -92,7 +92,7 @@ extern void pci_pip405_write_regs(struct pci_controller *,
/* PIIX4 ISA Bridge Function 0 */
static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
{PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */
{PCI_CFG_PIIX4_GENCFG, 0x00010041, 4}, /* enable SERIRQs, ISA, PNP */
{PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
{PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
{PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
{PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
@@ -106,6 +106,7 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
/* PIIX4 IDE Controller Function 1 */
static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
{PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
#if !defined(CONFIG_MIP405T)
{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
@@ -129,10 +130,10 @@ static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
/* PIIX4 Power Management Function 3 */
static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
{PCI_CFG_PIIX4_PMAB, 0x00004000, 4}, /* set PMBA to "valid" value */
{PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
{PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
{PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
{PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
{ } /* end of device table */
};
/* PPC405 Dummy only used to prevent autosetup on this host bridge */

2
board/mpl/common/piix4_pci.h
View File

@@ -143,7 +143,7 @@
#define PCI_CFG_PIIX4_LEGSUP 0xC0
/* Function 3 Power Management */
#define PCI_CFG_PIIX4_PMAB 0x40
#define PCI_CFG_PIIX4_PMBA 0x40
#define PCI_CFG_PIIX4_CNTA 0x44
#define PCI_CFG_PIIX4_CNTB 0x48
#define PCI_CFG_PIIX4_GPICTL 0x4C

5
board/mpl/mip405/cmd_mip405.c
View File

@@ -54,10 +54,13 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (do_mplcommon(cmdtp, flag, argc, argv));
}
U_BOOT_CMD(
mip405, 6, 1, do_mip405,
mip405, 8, 1, do_mip405,
"mip405 - MIP405 specific Cmds\n",
"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
"mip405 flash mps - updates U-Boot with image from MPS\n"
"mip405 info - displays board information\n"
"mip405 led <on> - switches LED on (on=1) or off (on=0)\n"
"mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever\n"
);
/* ------------------------------------------------------------------------- */

24
board/mpl/mip405/init.S
View File

@@ -87,19 +87,15 @@ ext_bus_cntlr_init:
mfdcr r4,ebccfgd
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
beq 0f /* jump if 8 bit bus width */
beq 0f /* jump if 8 bit bus width */
/* setup 16 bit things (Flash Boot)
/* setup 16 bit things
*-----------------------------------------------------------------------
* Memory Bank 0 (16 Bit Flash) initialization
*---------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
/* addis r4,0,0xFF8F */
/* ori r4,r4,0xFE80 */
/* addis r4,0,0x9B01 */
/* ori r4,r4,0x5480 */
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
mtdcr ebccfgd,r4
@@ -107,8 +103,6 @@ ext_bus_cntlr_init:
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
/* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
/* ori r4,r4,0xA000 / * BW=0x01(16 bits) */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
mtdcr ebccfgd,r4
@@ -123,21 +117,13 @@ ext_bus_cntlr_init:
/* 0x7F8FFE80 slowest boot */
addi r4,0,pb0ap
mtdcr ebccfga,r4
#if 0
addis r4,0,0x9B01
ori r4,r4,0x5480
#else
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
#endif
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
/* addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h */
/* ori r4,r4,0x8000 / * BW=0x0( 8 bits) */
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
@@ -178,18 +164,18 @@ ext_bus_cntlr_init:
ori r4,r4,0x0000
mtdcr ebccfgd,r4
addi r4,0,pb6cr
addi r4,0,pb6cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
addi r4,0,pb7cr
addi r4,0,pb7cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
nop /* pass2 DCR errata #8 */
nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------

7
board/mpl/mip405/mip405.c
View File

@@ -667,9 +667,16 @@ static int test_dram (unsigned long ramsize)
/* used to check if the time in RTC is valid */
static unsigned long start;
static struct rtc_time tm;
extern flash_info_t flash_info[]; /* info for FLASH chips */
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* adjust flash start and size as well as the offset */
gd->bd->bi_flashstart=0-flash_info[0].size;
gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
gd->bd->bi_flashoffset=0;
/* check, if RTC is running */
rtc_get (&tm);
start=get_timer(0);

7
board/mpl/mip405/mip405.h
View File

@@ -137,13 +137,13 @@ void user_led0(unsigned char on);
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_BS 2 /* 4 MByte */
#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define FLASH_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define FLASH_BW 1 /* 16Bit */
/* CR register for Boot */
#define FLASH_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
/* CR register for non Boot */
#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
@@ -172,11 +172,12 @@ void user_led0(unsigned char on);
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define MPS_BS 2 /* 4 MByte */
#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define MPS_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define MPS_BW 0 /* 8Bit */
/* CR register for Boot */
#define MPS_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
/* CR register for non Boot */
#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))

159
board/mpl/pip405/init.S
View File

@@ -41,17 +41,21 @@
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include "configs/PIP405.h"
#include <configs/PIP405.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include "pip405.h"
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
mfdcr r3,strap /* get strapping reg */
andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
bnelr /* jump back if PCI boot */
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
mflr r4 /* save link register */
bl ..getAddr
..getAddr:
mflr r3 /* get address of ..getAddr */
@@ -82,7 +86,7 @@ ext_bus_cntlr_init:
mfdcr r4,ebccfgd
andi. r0, r4, 0x2000 /* mask out irrelevant bits */
beq 0f /* jump if 8 bit bus width */
beq 0f /* jump if 8 bit bus width */
/* setup 16 bit things
*-----------------------------------------------------------------------
@@ -90,74 +94,49 @@ ext_bus_cntlr_init:
*---------------------------------------------------------------------- */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addis r4,0,0x9B01
ori r4,r4,0x5480
mtdcr ebccfgd,r4
mtdcr ebccfga,r4
addis r4,0,(FLASH_AP_B)@h
ori r4,r4,(FLASH_AP_B)@l
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x011(8MB),BU=0x3(R/W), */
addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
ori r4,r4,0xA000 /* BW=0x01(16 bits) */
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 1 (Multi Purpose Socket) initialization
*----------------------------------------------------------------------*/
addi r4,0,pb1ap
mtdcr ebccfga,r4
addis r4,0,0x0281
ori r4,r4,0x5480
mtdcr ebccfgd,r4
addi r4,0,pb1cr
mtdcr ebccfga,r4
/* BS=0x011(8MB),BU=0x3(R/W), */
addis r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(FLASH_CR_B)@h
ori r4,r4,(FLASH_CR_B)@l
mtdcr ebccfgd,r4
b 1f
0:
/* 8Bit boot mode: */
/* 8Bit boot mode: */
/*-----------------------------------------------------------------------
* Memory Bank 0 Multi Purpose Socket initialization
*----------------------------------------------------------------------- */
* Memory Bank 0 Multi Purpose Socket initialization
*----------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
addi r4,0,pb0ap
mtdcr ebccfga,r4
addis r4,0,0x9B01
ori r4,r4,0x5480
mtdcr ebccfgd,r4
mtdcr ebccfga,r4
addis r4,0,(MPS_AP_B)@h
ori r4,r4,(MPS_AP_B)@l
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x011(4MB),BU=0x3(R/W), */
addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
mtdcr ebccfgd,r4
addi r4,0,pb0cr
mtdcr ebccfga,r4
/* BS=0x010(4MB),BU=0x3(R/W), */
addis r4,0,(MPS_CR_B)@h
ori r4,r4,(MPS_CR_B)@l
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 1 (Flash) initialization
*-----------------------------------------------------------------------*/
addi r4,0,pb1ap
mtdcr ebccfga,r4
addis r4,0,0x0281
ori r4,r4,0x5480
mtdcr ebccfgd,r4
addi r4,0,pb1cr
mtdcr ebccfga,r4
/* BS=0x011(8MB),BU=0x3(R/W), */
addis r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
ori r4,r4,0xA000 /* BW=0x0( 8 bits) */
mtdcr ebccfgd,r4
1:
/*-----------------------------------------------------------------------
* Memory Bank 2-3-4-5-6 (not used) initialization
*-----------------------------------------------------------------------*/
addi r4,0,pb1cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
addi r4,0,pb2cr
mtdcr ebccfga,r4
addis r4,0,0x0000
@@ -182,28 +161,18 @@ ext_bus_cntlr_init:
ori r4,r4,0x0000
mtdcr ebccfgd,r4
addi r4,0,pb6cr
addi r4,0,pb6cr
mtdcr ebccfga,r4
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 7 (Config Register) initialization
*----------------------------------------------------------------------- */
addi r4,0,pb7ap
mtdcr ebccfga,r4
addis r4,0,0x0181 /* Doc says TWT=3 and Openios TWT=3!! */
ori r4,r4,0x5280 /* disable Ready, BEM=0 */
mtdcr ebccfgd,r4
addi r4,0,pb7cr
mtdcr ebccfga,r4
/* BS=0x0(1MB),BU=0x3(R/W), */
addis r4,0,((CONFIG_PORT_ADDR & 0xFFF00000) | 0x00010000)@h
ori r4,r4,0x8000 /* BW=0x0(8 bits) */
addis r4,0,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
nop /* pass2 DCR errata #8 */
nop /* pass2 DCR errata #8 */
blr
/*-----------------------------------------------------------------------------
@@ -217,3 +186,45 @@ sdram_init:
blr
#if defined(CONFIG_BOOT_PCI)
.section .bootpg,"ax"
.globl _start_pci
/*******************************************
*/
_start_pci:
/* first handle errata #68 / PCI_18 */
iccci r0, r0 /* invalidate I-cache */
lis r31, 0
mticcr r31 /* ICCR = 0 (all uncachable) */
isync
mfccr0 r28 /* set CCR0[24] = 1 */
ori r28, r28, 0x0080
mtccr0 r28
/* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
lis r28, 0xEF40
addi r28, r28, 0x0004
stw r31, 0x0C(r28) /* clear PMM0PCIHA */
lis r29, 0xFFF8 /* open 512 kByte */
addi r29, r29, 0x0001/* and enable this region */
stwbrx r29, r0, r28 /* write PMM0MA */
lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
lis r31, 0x8000 /* set en bit bus 0 */
ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
stwbrx r31, r0, r28 /* write it */
lwbrx r31, r0, r29 /* load XBCS register */
oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
stwbrx r31, r0, r29 /* write back XBCS register */
nop
nop
b _start /* normal start */
#endif

17
board/mpl/pip405/pip405.c
View File

@@ -194,6 +194,11 @@ int board_pre_init (void)
#ifdef SDRAM_DEBUG
DECLARE_GLOBAL_DATA_PTR;
#endif
/* set up the config port */
mtdcr (ebccfga, pb7ap);
mtdcr (ebccfgd, CONFIG_PORT_AP);
mtdcr (ebccfga, pb7cr);
mtdcr (ebccfgd, CONFIG_PORT_CR);
memclk = get_bus_freq (tmemclk);
tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
@@ -657,8 +662,20 @@ static int test_dram (unsigned long ramsize)
}
extern flash_info_t flash_info[]; /* info for FLASH chips */
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* adjust flash start and size as well as the offset */
gd->bd->bi_flashstart=0-flash_info[0].size;
gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
gd->bd->bi_flashoffset=0;
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
if (mfdcr(strap) & PSR_ROM_LOC)
mtspr(ccr0, (mfspr(ccr0) & ~0x80));
return (0);
}

116
board/mpl/pip405/pip405.h
View File

@@ -25,6 +25,7 @@
* Global routines used for PIP405
*****************************************************************************/
#ifndef __ASSEMBLY__
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
@@ -35,13 +36,13 @@ void user_led1(unsigned char on);
#define PLD_BASE_ADDRESS CFG_ISA_IO_BASE_ADDRESS + 0x800
#define PLD_PART_REG PLD_BASE_ADDRESS + 0
#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
#define PLD_PART_REG PLD_BASE_ADDRESS + 0
#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2
#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3
#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4
#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5
#define PLD_CAN_REG PLD_BASE_ADDRESS + 6
#define PLD_CAN_REG PLD_BASE_ADDRESS + 6
#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7
#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8
#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9
@@ -50,86 +51,32 @@ void user_led1(unsigned char on);
#define PIIX4_VENDOR_ID 0x8086
#define PIIX4_IDE_DEV_ID 0x7111
/* timings */
/* PLD (CS7) */
#define PLD_BME 0 /* Burst disable */
#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define PLD_OEN 1 /* Cycles from CS low to OE low */
#define PLD_WBN 1 /* Cycles from CS low to WE low */
#define PLD_WBF 1 /* Cycles from WE high to CS high */
#define PLD_TH 2 /* Number of hold cycles after transfer */
#define PLD_RE 0 /* Ready disabled */
#define PLD_SOR 1 /* Sample on Ready disabled */
#define PLD_BEM 0 /* Byte Write only active on Write cycles */
#define PLD_PEN 0 /* Parity disable */
#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define PLD_BS 0 /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define PLD_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define PLD_BW 0 /* 16Bit */
#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
#endif
/* timings */
#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
/* Dummy CS to get the board revision */
#define BOARD_BME 0 /* Burst disable */
#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define BOARD_OEN 1 /* Cycles from CS low to OE low */
#define BOARD_WBN 1 /* Cycles from CS low to WE low */
#define BOARD_WBF 1 /* Cycles from WE high to CS high */
#define BOARD_TH 2 /* Number of hold cycles after transfer */
#define BOARD_RE 0 /* Ready disabled */
#define BOARD_SOR 1 /* Sample on Ready disabled */
#define BOARD_BEM 0 /* Byte Write only active on Write cycles */
#define BOARD_PEN 0 /* Parity disable */
#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
/* CS Config register (CS7) */
#define CONFIG_PORT_BME 0 /* Burst disable */
#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */
#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */
#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */
#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */
#define CONFIG_PORT_RE 0 /* Ready disabled */
#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */
#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */
#define CONFIG_PORT_PEN 0 /* Parity disable */
#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define BOARD_BS 0 /* 1 MByte */
#define CONFIG_PORT_BS 0 /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define BOARD_BU 3 /* R/W */
#define CONFIG_PORT_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define BOARD_BW 0 /* 16Bit */
#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
/* UART0 CS2 */
#define UART0_BME 0 /* Burst disable */
#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
#define UART0_OEN 1 /* Cycles from CS low to OE low */
#define UART0_WBN 1 /* Cycles from CS low to WE low */
#define UART0_WBF 1 /* Cycles from WE high to CS high */
#define UART0_TH 2 /* Number of hold cycles after transfer */
#define UART0_RE 0 /* Ready disabled */
#define UART0_SOR 1 /* Sample on Ready disabled */
#define UART0_BEM 0 /* Byte Write only active on Write cycles */
#define UART0_PEN 0 /* Parity disable */
#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define UART0_BS 0 /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define UART0_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define UART0_BW 0 /* 8Bit */
#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
/* UART1 CS3 */
#define UART1_AP UART0_AP /* same timing as UART0 */
#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
#define CONFIG_PORT_BW 0 /* 16Bit */
#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
/* Flash CS0 or CS 1 */
/* 0x7F8FFE80 slowest timing at all... */
@@ -149,19 +96,19 @@ void user_led1(unsigned char on);
#define FLASH_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Access Parameter Register for Boot */
#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define FLASH_BS 2 /* 4 MByte */
#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define FLASH_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define FLASH_BW 1 /* 16Bit */
/* CR register for Boot */
#define FLASH_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
/* CR register for non Boot */
#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
@@ -183,18 +130,19 @@ void user_led1(unsigned char on);
#define MPS_PEN 0 /* Parity disable */
/* Access Parameter Register for non Boot */
#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Access Parameter Register for Boot */
#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
#define MPS_BS 2 /* 4 MByte */
#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
#define MPS_BU 3 /* R/W */
/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
#define MPS_BW 0 /* 8Bit */
/* CR register for Boot */
#define MPS_CR_B ((FLASH_BASE0_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
/* CR register for non Boot */
#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))

44
board/sixnet/flash.c
View File

@@ -23,6 +23,10 @@
#include <common.h>
#include <mpc8xx.h>
/* environment.h defines the various CFG_ENV_... values in terms
* of whichever ones are given in the configuration file.
*/
#include <environment.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
@@ -104,6 +108,19 @@ unsigned long flash_init (void)
&flash_info[0]);
#endif
#ifdef CFG_ENV_ADDR
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
#ifdef CFG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[0]);
#endif
return (size_b);
}
@@ -154,6 +171,21 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
for( i = 0; i < info->sector_count; i++ )
info->start[i] = base + (i * sect_size);
}
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
int sect_size; /* number of bytes/sector */
sect_size = 0x00010000 * (sizeof(FPW)/2);
/* set up sector start address table (top boot sector type) */
for (i = 0; i < info->sector_count - 3; i++)
info->start[i] = base + (i * sect_size);
i = info->sector_count - 1;
info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2);
info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2);
info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2);
}
}
/*-----------------------------------------------------------------------
@@ -196,6 +228,9 @@ void flash_print_info (flash_info_t *info)
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM800T:
fmt = "29LV800B%s (8 Mbit, %s)\n";
break;
case FLASH_AM640U:
fmt = "29LV641D (64 Mbit, uniform sectors)\n";
break;
@@ -295,6 +330,12 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
case (FPW)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000 * (sizeof(FPW)/2);
break; /* => 1 or 2 MiB */
case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
@@ -401,6 +442,7 @@ static void flash_sync_real_protect(flash_info_t *info)
break;
case FLASH_AM640U:
case FLASH_AM800T:
default:
/* no hardware protect that we support */
break;
@@ -438,6 +480,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
case FLASH_28F320C3B:
case FLASH_28F640C3B:
case FLASH_AM640U:
case FLASH_AM800T:
break;
case FLASH_UNKNOWN:
default:
@@ -735,6 +778,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
break;
case FLASH_AM640U:
case FLASH_AM800T:
default:
/* no hardware protect that we support */
info->protect[sector] = prot;

68
board/sixnet/sixnet.c
View File

@@ -24,6 +24,7 @@
#include <common.h>
#include <config.h>
#include <jffs2/jffs2.h>
#include <mpc8xx.h>
#include <net.h> /* for eth_init() */
#include <rtc.h>
@@ -602,3 +603,70 @@ long int initdram(int board_type)
return (size_sdram);
}
#ifdef CFG_JFFS_CUSTOM_PART
static struct part_info part;
#define jffs2_block(i) \
((struct jffs2_unknown_node*)(CFG_JFFS2_BASE + (i) * 65536))
struct part_info* jffs2_part_info(int part_num)
{
DECLARE_GLOBAL_DATA_PTR;
bd_t *bd = gd->bd;
char* s;
int i;
int bootnor = 0; /* assume booting from NAND flash */
if (part_num != 0)
return 0; /* only support one partition */
if (part.usr_priv == (void*)1)
return &part; /* already have part info */
memset(&part, 0, sizeof(part));
if (nand_dev_desc[0].ChipID == NAND_ChipID_UNKNOWN)
bootnor = 1;
else if (bd->bi_flashsize < 0x800000)
bootnor = 0;
else for (i = 0; !bootnor && i < 4; ++i) {
/* boot from NOR if JFFS2 info in any of
* first 4 erase blocks
*/
if (jffs2_block(i)->magic == JFFS2_MAGIC_BITMASK)
bootnor = 1;
}
if (bootnor) {
/* no NAND flash or boot in NOR, use NOR flash */
part.offset = (unsigned char *)CFG_JFFS2_BASE;
part.size = CFG_JFFS2_SIZE;
}
else {
char readcmd[60];
/* boot info in NAND flash, get and use copy in RAM */
/* override info from environment if present */
s = getenv("fsaddr");
part.offset = s ? (void *)simple_strtoul(s, NULL, 16)
: (void *)CFG_JFFS2_RAMBASE;
s = getenv("fssize");
part.size = s ? simple_strtoul(s, NULL, 16)
: CFG_JFFS2_RAMSIZE;
/* read from nand flash */
sprintf(readcmd, "nand read.jffs2 %x 0 %x",
(uint32_t)part.offset, part.size);
run_command(readcmd, 0);
}
part.erasesize = 0; /* unused */
part.usr_priv=(void*)1; /* ready */
return &part;
}
#endif /* ifdef CFG_JFFS_CUSTOM_PART */