FSL DDR: Add e500 TLB helper for DDR code
Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -90,3 +90,67 @@ void init_tlbs(void)
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return ;
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}
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unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
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{
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unsigned int tlb_size;
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unsigned int ram_tlb_index;
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unsigned int ram_tlb_address;
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/*
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* Determine size of each TLB1 entry.
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*/
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switch (memsize_in_meg) {
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case 16:
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case 32:
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tlb_size = BOOKE_PAGESZ_16M;
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break;
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case 64:
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case 128:
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tlb_size = BOOKE_PAGESZ_64M;
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break;
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case 256:
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case 512:
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tlb_size = BOOKE_PAGESZ_256M;
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break;
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case 1024:
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case 2048:
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if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
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tlb_size = BOOKE_PAGESZ_1G;
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else
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tlb_size = BOOKE_PAGESZ_256M;
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break;
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default:
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puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
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" and 2G are supported.\n");
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/*
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* The memory was not able to be mapped.
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* Default to a small size.
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*/
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tlb_size = BOOKE_PAGESZ_64M;
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memsize_in_meg = 64;
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break;
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}
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/*
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* Configure DDR TLB1 entries.
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* Starting at TLB1 8, use no more than 8 TLB1 entries.
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*/
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ram_tlb_index = 8;
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ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
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while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
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&& ram_tlb_index < 16) {
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set_tlb(1, ram_tlb_address, ram_tlb_address,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, ram_tlb_index, tlb_size, 1);
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ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
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ram_tlb_index++;
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}
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/*
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* Confirm that the requested amount of memory was mapped.
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*/
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return memsize_in_meg;
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}
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@ -431,6 +431,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
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extern void disable_tlb(u8 esel);
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extern void invalidate_tlb(u8 tlb);
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extern void init_tlbs(void);
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extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
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#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
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{ .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
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