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Merge with pollux.denx.org:/home/git/u-boot/.git

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This commit is contained in:
2005-08-12 15:33:33 +02:00
commit 6df6d38d2d
48 changed files with 1657 additions and 992 deletions
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31
CHANGELOG
View File

@ -2,6 +2,33 @@
Changes for U-Boot 1.1.3:
======================================================================
* Update AMCC Yosemite to get a consistent setup for all AMCC eval
boards (baudrate, environment...). Flash driver fixed.
Patch by Stefan Roese, 11 Aug 2005
* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port
Patch by Stefan Roese, 11 Aug 2005
* Add NAND FLASH support for AMCC Bamboo 440EP eval board
Patch by Stefan Roese, 11 Aug 2005
* Add configuration for IFM AEV FIFO board.
Minor coding style cleanup.
* Add configuration for IFM SPI eval board
* Fix CompactFlash problem on HMI1001 board
* Make new "mtdparts" code build with older compilers
Patch by Andrea Scian, 09 Aug 2005
* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to
CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design
with the 405 defines and the linux kernel defines.
Patch by Stefan Roese, 08 Aug 2005
* Fix compiler warnings with older GCC versions
* Add common (with Linux) MTD partition scheme and "mtdparts" command
Old, obsolete and duplicated code was cleaned up and replace by the
@ -34,13 +61,13 @@ Changes for U-Boot 1.1.3:
* Fix errors that occur when accessing SystemACE CF
Patch by Jeff Angielski, 09 Jan 2005
* Document switching between U-Boot and PlanetCore on RPXlite
by Sam Song, 24 Dec 2004
* Fix PowerQUICC II mask detection.
Patch by Eugene Surovegin, 20 Dec 2004
* Add support for Altera NIOS DK1C20 board
Patch by Shlomo Kut, 13 Dec 2004

8
Makefile
View File

@ -231,6 +231,9 @@ PATI_config: unconfig
## MPC5xxx Systems
#########################################################################
aev_config: unconfig
@./mkconfig -a aev ppc mpc5xxx tqm5200
hmi1001_config: unconfig
@./mkconfig hmi1001 ppc mpc5xxx hmi1001
@ -357,6 +360,11 @@ MiniFAP_config: unconfig
}
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
spieval_config: unconfig
echo "#define CONFIG_CS_AUTOCONF">>include/config.h
echo "... with automatic CS configuration"
@./mkconfig -a spieval ppc mpc5xxx tqm5200
#########################################################################
## MPC8xx Systems
#########################################################################

122
board/amcc/bamboo/bamboo.c
View File

@ -29,6 +29,7 @@
void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
#if 0
@ -132,10 +133,10 @@ gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
EBC0_BNCR_BW_8BIT
#define EBC0_BNCR_SMALL_FLASH_CS4 \
EBC0_BNCR_BAS_ENCODE(0x87800000) | \
EBC0_BNCR_BS_8MB | \
EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_16BIT
EBC0_BNCR_BW_8BIT
/* Large Flash or SRAM */
#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
@ -273,6 +274,87 @@ int board_early_init_f(void)
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
/*----------------------------------------------------------------------------+
| nand_reset.
| Reset Nand flash
| This routine will abort previous cmd
+----------------------------------------------------------------------------*/
int nand_reset(ulong addr)
{
int wait=0, stat=0;
out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
while ((stat != 0xc0) && (wait != 0xffff)) {
stat = in8(addr + NAND_DATA_REG);
wait++;
}
if (stat == 0xc0) {
return 0;
} else {
printf("NAND Reset timeout.\n");
return -1;
}
}
void board_nand_set_device(int cs, ulong addr)
{
/* Set NandFlash Core Configuration Register */
out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
switch (cs) {
case 1:
/* -------
* NAND0
* -------
* K9F1208U0A : 4 addr cyc, 1 col + 3 Row
* Set NDF1CR - Enable External CS1 in NAND FLASH controller
*/
out32(addr + NAND_CR1_REG, 0x80002222);
break;
case 2:
/* -------
* NAND1
* -------
* K9K2G0B : 5 addr cyc, 2 col + 3 Row
* Set NDF2CR : Enable External CS2 in NAND FLASH controller
*/
out32(addr + NAND_CR2_REG, 0xC0007777);
break;
}
/* Perform Reset Command */
if (nand_reset(addr) != 0)
return;
}
void nand_init(void)
{
board_nand_set_device(1, CFG_NAND_ADDR);
nand_probe(CFG_NAND_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#if 0 /* NAND1 not supported yet */
board_nand_set_device(2, CFG_NAND2_ADDR);
nand_probe(CFG_NAND2_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#endif
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
int checkboard(void)
{
sys_info_t sysinfo;
@ -585,7 +667,11 @@ int is_powerpc440ep_pass1(void)
+----------------------------------------------------------------------------*/
int is_nand_selected(void)
{
return FALSE; /* test-only */
#ifdef CONFIG_BAMBOO_NAND
return TRUE;
#else
return FALSE;
#endif
}
/*----------------------------------------------------------------------------+
@ -829,12 +915,8 @@ void ext_bus_cntlr_init(void)
/* NAND Flash */
ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
/*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
ebc0_cs2_bnap_value = 0;
ebc0_cs2_bncr_value = 0;
ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
ebc0_cs3_bnap_value = 0;
ebc0_cs3_bncr_value = 0;
} else {
@ -985,7 +1067,7 @@ void ext_bus_cntlr_init(void)
+----------------------------------------------------------------------------*/
uart_config_nb_t get_uart_configuration(void)
{
return (L4); /* test-only */
return (L4);
}
/*----------------------------------------------------------------------------+
@ -1132,8 +1214,7 @@ void ndfc_selection_in_fpga(void)
fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
/*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
/*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
}
@ -1725,11 +1806,15 @@ void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t
*(core_select_P+UIC_0_3) = CORE_SELECTED;
*(core_select_P+UIC_4_9) = CORE_SELECTED;
*(core_select_P+SCP_CORE) = CORE_SELECTED;
*(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
*(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
*(core_select_P+SCP_CORE) = CORE_SELECTED;
*(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
*(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
*(core_select_P+USB1_DEVICE) = CORE_SELECTED;
if (is_nand_selected()) {
*(core_select_P+NAND_FLASH) = CORE_SELECTED;
}
*config_val_P = CONFIG_IS_VALID;
}
@ -1901,9 +1986,8 @@ void configure_ppc440ep_pins(void)
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 );
/*SDR0_CUST0_CHIPSELGAT_EN2 ); */
/*SDR0_CUST0_CHIPSELGAT_EN3 ); */
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
ndfc_selection_in_fpga();
}

11
board/amcc/bamboo/flash.c
View File

@ -50,15 +50,16 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
*/
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
{0x87800000, 0x87880000, 0xFF800001}, /* 3:boot from big flash 33*/
{0x87800000, 0x87880000, 0xFF800001}, /* 4:boot from big flash 66*/
{0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
{0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
{0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
};
/*
@ -117,6 +118,10 @@ unsigned long flash_init(void)
index = 2;
break;
}
} else if (index == 0) {
if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
index = 8; /* sram below op code flash -> new index 8 */
}
}
DEBUGF("\n");

24
board/amcc/bamboo/init.S
View File

@ -86,14 +86,20 @@
tlbtab:
tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the
dcache as stack. It is patched after relocation to enable SA_I
*/
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
@ -102,6 +108,6 @@ tlbtab:
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end

1
board/amcc/yosemite/Makefile
View File

@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)

571
board/amcc/yosemite/flash.c
View File

@ -1,571 +0,0 @@
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
/*
* Ported to XPedite1000, 1/2 mb boot flash only
* Travis B. Sawyer, <travis.sawyer@sandburst.com>
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
unsigned long flash_addr_table[512][CFG_MAX_FLASH_BANKS] = {
{0xfe000000}
};
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_word(flash_info_t * info, ulong dest, ulong data);
#define ADDR0 0xaaaa
#define ADDR1 0x5554
#define FLASH_WORD_SIZE unsigned short
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned short index = 0;
int i;
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *)
flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
total_b += flash_info[i].size;
}
/* FLASH protect Monitor */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE, 0xFFFFFFFF, &flash_info[0]);
return total_b;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_SST:
printf("SST ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMD016:
printf("AM29F016D (16 Mbit, uniform sector size)\n");
break;
case FLASH_AM040:
printf("AM29F040 (512 Kbit, uniform sector size)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
case FLASH_SST800A:
printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
break;
case FLASH_SST160A:
printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count - 1))
size = info->start[i + 1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) {
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s%s",
info->start[i],
erased ? " E" : " ", info->protect[i] ? "RO " : " ");
}
printf("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong) addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */
udelay(10000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x00AA;
udelay(1000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = (FLASH_WORD_SIZE) 0x0055;
udelay(1000);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x0090;
udelay(1000);
value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) {
case (FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
#ifdef CONFIG_ADCIOP
value = addr2[0]; /* device ID */
debug("\ndev_code=%x\n", value);
#else
value = addr2[1]; /* device ID */
#endif
DEBUGF("\nFLASH DEVICEID: %x\n", value);
info->flash_id = 0;
info->sector_count = CFG_MAX_FLASH_SECT;
info->size = 0x02000000;
/* set up sector start address table */
for (i = 0; i < info->sector_count; i++) {
info->start[i] = (int)base + (i * 0x00020000);
info->protect[i] = 0;
}
*(FLASH_WORD_SIZE *) ((int)addr) = (FLASH_WORD_SIZE) 0x00F0; /* reset bank */
return (info->size);
}
int wait_for_DQ7(flash_info_t * info, int sect)
{
ulong start, now, last;
volatile FLASH_WORD_SIZE *addr =
(FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
(FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return -1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
printf("Erasing sector %p\n", addr2);
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x0080;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
asm("sync");
asm("isync");
l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
#if 0
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
wait_for_DQ7(info, l_sect);
DONE:
#endif
/* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
ulong status_value = 0;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
/*print status if needed */
if ((wp >= (status_value + 0x20000))
&& (status_value < 0xFFFE0000)) {
status_value = wp;
printf("writing to sector 0x%X\n", status_value);
}
data = 0;
for (i = 0; i < 4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word(flash_info_t * info, ulong dest, ulong data)
{
vu_long *addr2 = (vu_long *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
ulong start;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *)dest) &
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2);
}
for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) {
int flag;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00AA;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR1) =
(FLASH_WORD_SIZE) 0x0055;
asm("sync");
asm("isync");
*(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) =
(FLASH_WORD_SIZE) 0x00A0;
asm("sync");
asm("isync");
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

21
board/amcc/yosemite/init.S
View File

@ -86,14 +86,19 @@
tlbtab:
tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the
dcache as stack. It is patched after relocation to enable SA_I
*/
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )

55
board/amcc/yosemite/yosemite.c
View File

@ -20,9 +20,12 @@
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
int board_early_init_f(void)
{
register uint reg;
@ -35,7 +38,7 @@ int board_early_init_f(void)
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
@ -122,6 +125,54 @@ int board_early_init_f(void)
return 0;
}
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
uint pbcr;
int size_val = 0;
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
return 0;
}
int checkboard(void)
{
sys_info_t sysinfo;
@ -135,6 +186,8 @@ int checkboard(void)
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
return (0);
}

4
board/tqm5200/tqm5200.c
View File

@ -250,6 +250,10 @@ long int initdram (int board_type)
int checkboard (void)
{
#if defined (CONFIG_AEVFIFO)
puts ("Board: AEVFIFO\n");
return 0;
#endif
#if defined (CONFIG_TQM5200_AA)
puts ("Board: TQM5200-AA (TQ-Components GmbH)\n");
#elif defined (CONFIG_TQM5200_AB)

2
common/cmd_ace.c
View File

@ -31,7 +31,7 @@
* available to cmd_fat.c:get_dev and filling in a block device
* description that has all the bits needed for FAT support to
* read sectors.
*
*
* According to Xilinx technical support, before accessing the
* SystemACE CF you need to set the following control bits:
* FORCECFGMODE : 1

8
common/cmd_bdinfo.c
View File

@ -62,14 +62,14 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_num ("bootflags", bd->bi_bootflags );
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR)
print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
defined(CONFIG_440EP) || defined(CONFIG_440GR)
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440_EP CONFIG_440_GR */
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_CPM2)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
@ -80,7 +80,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440_EP CONFIG_440_GR */
#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
#if defined(CONFIG_MPC8220)
print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq));
print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq));

27
common/cmd_flash.c
View File

@ -534,7 +534,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return rcode;
}
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
/* protect on/off <part-id> */
if ((argc == 3) && (id_parse(argv[2], NULL, &dev_type, &dev_num) == 0)) {
@ -664,6 +664,15 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
/**************************************************/
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
# define TMP_ERASE "erase <part-id>\n - erase partition\n"
# define TMP_PROT_ON "protect on <part-id>\n - protect partition\n"
# define TMP_PROT_OFF "protect off <part-id>\n - make partition writable\n"
#else
# define TMP_ERASE /* empty */
# define TMP_PROT_ON /* empty */
# define TMP_PROT_OFF /* empty */
#endif
U_BOOT_CMD(
flinfo, 2, 1, do_flinfo,
@ -682,9 +691,7 @@ U_BOOT_CMD(
"w/addr 'start'+'len'-1\n"
"erase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n"
"erase bank N\n - erase FLASH bank # N\n"
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
"erase <part-id>\n - erase partition\n"
#endif
TMP_ERASE
"erase all\n - erase all FLASH banks\n"
);
@ -699,9 +706,7 @@ U_BOOT_CMD(
"protect on N:SF[-SL]\n"
" - protect sectors SF-SL in FLASH bank # N\n"
"protect on bank N\n - protect FLASH bank # N\n"
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
"protect on <part-id>\n - protect partition\n"
#endif
TMP_PROT_ON
"protect on all\n - protect all FLASH banks\n"
"protect off start end\n"
" - make FLASH from addr 'start' to addr 'end' writable\n"
@ -711,10 +716,12 @@ U_BOOT_CMD(
"protect off N:SF[-SL]\n"
" - make sectors SF-SL writable in FLASH bank # N\n"
"protect off bank N\n - make FLASH bank # N writable\n"
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
"protect off <part-id>\n - make partition writable\n"
#endif
TMP_PROT_OFF
"protect off all\n - make all FLASH banks writable\n"
);
#undef TMP_ERASE
#undef TMP_PROT_ON
#undef TMP_PROT_OFF
#endif /* CFG_CMD_FLASH */

8
common/cmd_fpga.c
View File

@ -137,9 +137,9 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
__FUNCTION__);
return FPGA_FAIL;
}
swapsize = ((unsigned int) *dataptr <<24) +
((unsigned int) *(dataptr+1) <<16) +
((unsigned int) *(dataptr+2) <<8 ) +
swapsize = ((unsigned int) *dataptr <<24) +
((unsigned int) *(dataptr+1) <<16) +
((unsigned int) *(dataptr+2) <<8 ) +
((unsigned int) *(dataptr+3) ) ;
dataptr+=4;
printf(" bytes in bitstream = %d\n", swapsize);
@ -217,7 +217,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
/* FIXME - this is a really weak test */
if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
PRINTF ("%s: Assuming buffer pointer in arg 3\n",
PRINTF ("%s: Assuming buffer pointer in arg 3\n",
__FUNCTION__);
fpga_data = (void *) dev;
PRINTF ("%s: fpga_data = 0x%x\n",

65
common/cmd_jffs2.c
View File

@ -45,7 +45,7 @@
* partition := <part-id>
* <part-id> := <dev-id>,part_num
*
*
*
* 'mtdids' - linux kernel mtd device id <-> u-boot device id mapping
*
* mtdids=<idmap>[,<idmap>,...]
@ -403,7 +403,7 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
return device_del(dev);
/* otherwise just delete this partition */
if (dev == current_dev) {
/* we are modyfing partitions for the current device,
* update current */
@ -416,7 +416,7 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
current_partnum = 0;
current_save();
} else if (part->offset <= curr_pi->offset) {
current_partnum--;
current_partnum--;
current_save();
}
}
@ -471,7 +471,7 @@ static int part_sort_add(struct mtd_device *dev, struct part_info *part)
list_add(&part->link, &dev->parts);
return 0;
}
new_pi = list_entry(&part->link, struct part_info, link);
/* get current partition info if we are updating current device */
@ -492,7 +492,7 @@ static int part_sort_add(struct mtd_device *dev, struct part_info *part)
if (new_pi->offset <= pi->offset) {
list_add_tail(&part->link, entry);
if (curr_pi && (pi->offset <= curr_pi->offset)) {
/* we are modyfing partitions for the current
* device, update current */
@ -516,7 +516,7 @@ static int part_sort_add(struct mtd_device *dev, struct part_info *part)
*/
static int part_add(struct mtd_device *dev, struct part_info *part)
{
/* verify alignment and size */
/* verify alignment and size */
if (part_validate(dev->id, part) != 0)
return 1;
@ -565,14 +565,14 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
}
}
/* check for offset */
/* check for offset */
offset = OFFSET_NOT_SPECIFIED;
if (*p == '@') {
p++;
offset = memsize_parse(p, &p);
}
/* now look for the name */
/* now look for the name */
if (*p == '(') {
name = ++p;
if ((p = strchr(name, ')')) == NULL) {
@ -591,7 +591,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
name = NULL;
}
/* test for options */
/* test for options */
mask_flags = 0;
if (strncmp(p, "ro", 2) == 0) {
mask_flags |= MTD_WRITEABLE;
@ -823,8 +823,8 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
printf("invalid mtd device '%.*s'\n", mtd_id_len - 1, mtd_id);
return 1;
}
DEBUGF("dev type = %d (%s), dev num = %d, mtd-id = %s\n",
DEBUGF("dev type = %d (%s), dev num = %d, mtd-id = %s\n",
id->type, MTD_DEV_TYPE(id->type),
id->num, id->mtd_id);
pend = strchr(p, ';');
@ -836,7 +836,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
offset = 0;
if ((dev = device_find(id->type, id->num)) != NULL) {
/* if device already exists start at the end of the last partition */
/* if device already exists start at the end of the last partition */
part = list_entry(dev->parts.prev, struct part_info, link);
offset = part->offset + part->size;
}
@ -852,7 +852,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
else
offset = part->offset;
/* verify alignment and size */
/* verify alignment and size */
if (part_validate(id, part) != 0)
break;
@ -885,7 +885,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
} else {
printf("unexpected character '%c' at the end of device\n", *p);
*ret = NULL;
return 1;
return 1;
}
}
@ -939,7 +939,7 @@ static struct mtdids* id_find(u8 type, u8 num)
{
struct list_head *entry;
struct mtdids *id;
list_for_each(entry, &mtdids) {
id = list_entry(entry, struct mtdids, link);
@ -951,7 +951,7 @@ static struct mtdids* id_find(u8 type, u8 num)
}
/**
* Search global mtdids list and find id of a requested mtd_id.
* Search global mtdids list and find id of a requested mtd_id.
*
* Note: first argument is not null terminated.
*
@ -963,7 +963,7 @@ static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_
{
struct list_head *entry;
struct mtdids *id;
DEBUGF("--- id_find_by_mtd_id: '%.*s' (len = %d)\n",
mtd_id_len, mtd_id, mtd_id_len);
@ -1045,13 +1045,13 @@ static int generate_mtdparts(char *buf, u32 buflen)
buf[0] = '\0';
return 0;
}
sprintf(p, "mtdparts=");
p += 9;
list_for_each(dentry, &devices) {
dev = list_entry(dentry, struct mtd_device, link);
/* copy mtd_id */
len = strlen(dev->id->mtd_id) + 1;
if (len > maxlen)
@ -1078,8 +1078,8 @@ static int generate_mtdparts(char *buf, u32 buflen)
memcpy(p, tmpbuf, len);
p += len;
maxlen -= len;
/* add offset only when there is a gap between
* partitions */
if ((!prev_part && (offset != 0)) ||
@ -1107,7 +1107,7 @@ static int generate_mtdparts(char *buf, u32 buflen)
*(p++) = ')';
maxlen -= len;
}
/* ro mask flag */
if (part->mask_flags && MTD_WRITEABLE) {
len = 2;
@ -1188,7 +1188,7 @@ static void list_partitions(void)
MTD_DEV_TYPE(dev->id->type), dev->id->num,
dev->id->mtd_id, dev->num_parts);
printf(" #: name\t\t\tsize\t\toffset\t\tmask_flags\n");
/* list partitions for given device */
part_num = 0;
list_for_each(pentry, &dev->parts) {
@ -1256,7 +1256,7 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
printf("unexpected trailing character '%c'\n", *p);
return 1;
}
if ((*dev = device_find(type, dnum)) == NULL) {
printf("no such device %s%d\n", MTD_DEV_TYPE(type), dnum);
return 1;
@ -1328,7 +1328,7 @@ static int parse_mtdparts(const char *const mtdparts)
/* re-read 'mtdparts' variable, devices_init may be updating env */
p = getenv("mtdparts");
if (strncmp(p, "mtdparts=", 9) != 0) {
printf("mtdparts variable doesn't start with 'mtdparts='\n");
return err;
@ -1615,7 +1615,7 @@ int mtdparts_init(void)
/**
* Parse and initialize global mtdids mapping and create global
* device/partition list.
* device/partition list.
*
* @return 0 on success, 1 otherwise
*/
@ -1627,6 +1627,9 @@ int mtdparts_init(void)
DEBUGF("\n---mtdparts_init---\n");
if (!initialized) {
struct mtdids *id;
struct part_info *part;
initialized = 1;
current_dev = (struct mtd_device *)
malloc(sizeof(struct mtd_device) +
@ -1639,8 +1642,8 @@ int mtdparts_init(void)
memset(current_dev, 0, sizeof(struct mtd_device) +
sizeof(struct part_info) + sizeof(struct mtdids));
struct mtdids *id = (struct mtdids *)(current_dev + 1);
struct part_info *part = (struct part_info *)(id + 1);
id = (struct mtdids *)(current_dev + 1);
part = (struct part_info *)(id + 1);
/* id */
id->mtd_id = "single part";
@ -1867,7 +1870,7 @@ int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* make sure we are in sync with env variables */
if (mtdparts_init() !=0)
return 1;
if ((part = jffs2_part_info(current_dev, current_partnum))){
/* check partition type for cramfs */
@ -1965,7 +1968,7 @@ int do_jffs2_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
list_partitions();
return 0;
}
/* mtdparts add <mtd-dev> <size>[@<offset>] <name> [ro] */
if (((argc == 5) || (argc == 6)) && (strcmp(argv[1], "add") == 0)) {
#define PART_ADD_DESC_MAXLEN 64
@ -1995,7 +1998,7 @@ int do_jffs2_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
sprintf(tmpbuf, "%s:%s(%s)%s",
id->mtd_id, argv[3], argv[4], argv[5] ? argv[5] : "");
id->mtd_id, argv[3], argv[4], argv[5] ? argv[5] : "");
DEBUGF("add tmpbuf: %s\n", tmpbuf);
if ((device_parse(tmpbuf, NULL, &dev) != 0) || (!dev))

2
common/lynxkdi.c
View File

@ -20,7 +20,7 @@
#if defined(CONFIG_LYNXKDI)
#include <lynxkdi.h>
#if defined(CONFIG_MPC8260) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
void lynxkdi_boot ( image_header_t *hdr )
{
void (*lynxkdi)(void) = (void(*)(void))hdr->ih_ep;

4
cpu/ppc4xx/405gp_enet.c
View File

@ -227,7 +227,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
while (mfdcr (malmcr) & MAL_CR_MMSR) {
};
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
out32 (ZMII_FER, 0);
udelay(100);
/* set RII mode */
@ -464,7 +464,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
else
out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
/* set speed */
if (speed == _100BASET) {

6
cpu/ppc4xx/405gp_pci.c
View File

@ -437,7 +437,7 @@ void pci_440_init (struct pci_controller *hose)
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
#if defined (CONFIG_440_GX) || defined (CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_sdstp1,strap);
if ( (strap & 0x00010000) == 0 ){
printf("PCI: SDR0_STRP1[PISE] not set.\n");
@ -495,7 +495,7 @@ void pci_440_init (struct pci_controller *hose)
out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
#elif defined(PCIX0_BRDGOPT1)
@ -531,7 +531,7 @@ void pci_440_init (struct pci_controller *hose)
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
hose->last_busno = pci_hose_scan(hose);

56
cpu/ppc4xx/440gx_enet.c
View File

@ -175,7 +175,7 @@ static void ppc_440x_eth_halt (struct eth_device *dev)
extern int phy_setup_aneg (unsigned char addr);
extern int miiphy_reset (unsigned char addr);
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long pfc1;
@ -279,7 +279,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
unsigned short devnum;
unsigned short reg_short;
sys_info_t sysinfo;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
int ethgroup;
#endif
@ -323,7 +323,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* MAL Channel RESET */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
@ -362,9 +362,9 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
out32 (ZMII_FER, 0);
udelay (100);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440_GX)
#elif defined(CONFIG_440GX)
ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
#else
if ((devnum == 0) || (devnum == 1)) {
@ -375,8 +375,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
(RGMII_FER_RGMII << RGMII_FER_V (3))));
}
#endif
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
__asm__ volatile ("eieio");
@ -391,7 +391,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
failsafe--;
}
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
@ -406,7 +406,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440_GX) */
#endif /* defined(CONFIG_440GX) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
@ -418,7 +418,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
case 1:
reg = CONFIG_PHY1_ADDR;
break;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
case 2:
reg = CONFIG_PHY2_ADDR;
break;
@ -441,7 +441,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
if (hw_p->first_init == 0) {
miiphy_reset (reg);
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
@ -512,7 +512,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
@ -521,13 +521,13 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
mtsdr(sdr_mfr, reg);
#endif
/* Set ZMII/RGMII speed according to the phy link speed */
reg = in32 (ZMII_SSR);
if ( (speed == 100) || (speed == 1000) )
out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
else
out32 (ZMII_SSR,
reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
if ((devnum == 2) || (devnum == 3)) {
if (speed == 1000)
@ -541,7 +541,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
/* set the Mal configuration reg */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
@ -642,7 +642,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_440_EP) || defined (CONFIG_440_GR)
#if defined (CONFIG_440EP) || defined (CONFIG_440GR)
mtdcr (maltxctp2r, hw_p->tx);
#else
mtdcr (maltxctp1r, hw_p->tx);
@ -653,7 +653,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
break;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
case 2:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
@ -672,7 +672,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* set RX buffer size */
mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
break;
#endif /*CONFIG_440_GX */
#endif /* CONFIG_440GX */
case 0:
default:
/* setup MAL tx & rx channel pointers */
@ -686,7 +686,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
/* Enable MAL transmit and receive channels */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
@ -836,7 +836,7 @@ int enetInt (struct eth_device *dev)
unsigned long mal_rx_eob;
unsigned long my_uic0msr, my_uic1msr;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
unsigned long my_uic2msr;
#endif
EMAC_440GX_HW_PST hw_p;
@ -856,7 +856,7 @@ int enetInt (struct eth_device *dev)
my_uic0msr = mfdcr (uic0msr);
my_uic1msr = mfdcr (uic1msr);
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
my_uic2msr = mfdcr (uic2msr);
#endif
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
@ -866,7 +866,7 @@ int enetInt (struct eth_device *dev)
/* not for us */
return (rc);
}
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
&& !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
/* not for us */
@ -922,7 +922,7 @@ int enetInt (struct eth_device *dev)
return (rc); /* we had errors so get out */
}
}
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
if (hw_p->devnum == 2) {
if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
@ -958,7 +958,7 @@ int enetInt (struct eth_device *dev)
return (rc); /* we had errors so get out */
}
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/* handle MAX TX EOB interrupt from a tx */
if (my_uic0msr & UIC_MTE) {
mal_rx_eob = mfdcr (maltxeobisr);
@ -987,14 +987,14 @@ int enetInt (struct eth_device *dev)
case 1:
mtdcr (uic1sr, UIC_ETH1);
break;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
case 2:
mtdcr (uic2sr, UIC_ETH2);
break;
case 3:
mtdcr (uic2sr, UIC_ETH3);
break;
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
default:
break;
}
@ -1184,7 +1184,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
int eth_num = 0;
EMAC_440GX_HW_PST hw = NULL;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
unsigned long pfc1;
mfsdr (sdr_pfc1, pfc1);
@ -1197,7 +1197,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
#if defined(CONFIG_PHY1_ADDR)
bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[0] = 0;
@ -1205,7 +1205,7 @@ int ppc_440x_eth_initialize (bd_t * bis)
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
ppc_440x_eth_setup_bridge(0, bis);
#endif
#endif

2
cpu/ppc4xx/cpu.c
View File

@ -178,7 +178,7 @@ int checkcpu (void)
case PVR_440GX_RC:
puts("GX Rev. C");
break;
#if defined(CONFIG_440_GR)
#if defined(CONFIG_440GR)
case PVR_440EP_RA:
puts("GR Rev. A");
break;

2
cpu/ppc4xx/cpu_init.c
View File

@ -188,7 +188,7 @@ cpu_init_f (void)
unsigned long val;
val = mfspr(tcr);
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */

44
cpu/ppc4xx/interrupts.c
View File

@ -54,12 +54,12 @@ static struct irq_action irq_vecs1[32]; /* For UIC1 */
void uic1_interrupt( void * parms); /* UIC1 handler */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
static struct irq_action irq_vecs2[32]; /* For UIC2 */
void uic0_interrupt( void * parms); /* UIC0 handler */
void uic2_interrupt( void * parms); /* UIC2 handler */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
@ -115,11 +115,11 @@ int interrupt_init_cpu (unsigned *decrementer_count)
irq_vecs1[vec].handler = NULL;
irq_vecs1[vec].arg = NULL;
irq_vecs1[vec].count = 0;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
irq_vecs2[vec].handler = NULL;
irq_vecs2[vec].arg = NULL;
irq_vecs2[vec].count = 0;
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif
}
@ -162,14 +162,14 @@ int interrupt_init_cpu (unsigned *decrementer_count)
set_evpr(0x00000000);
#if defined(CONFIG_440)
#if !defined(CONFIG_440_GX)
#if !defined(CONFIG_440GX)
/* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
#endif
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Take the GX out of compatibility mode
* Travis Sawyer, 9 Mar 2004
* NOTE: 440gx user manual inconsistency here
@ -195,7 +195,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
/*
* Handle external interrupts
*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
void external_interrupt(struct pt_regs *regs)
{
ulong uic_msr;
@ -219,7 +219,7 @@ void external_interrupt(struct pt_regs *regs)
return;
} /* external_interrupt CONFIG_440_GX */
} /* external_interrupt CONFIG_440GX */
#else
@ -266,7 +266,7 @@ void external_interrupt(struct pt_regs *regs)
}
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Handler for UIC0 interrupt */
void uic0_interrupt( void * parms)
{
@ -310,7 +310,7 @@ void uic0_interrupt( void * parms)
}
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#if defined(CONFIG_440)
/* Handler for UIC1 interrupt */
@ -357,7 +357,7 @@ void uic1_interrupt( void * parms)
}
#endif /* defined(CONFIG_440) */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* Handler for UIC1 interrupt */
void uic2_interrupt( void * parms)
{
@ -400,7 +400,7 @@ void uic2_interrupt( void * parms)
vec++;
}
}
#endif /* defined(CONFIG_440_GX) */
#endif /* defined(CONFIG_440GX) */
/****************************************************************************/
@ -414,7 +414,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
i = vec - 32;
irqa = irq_vecs1;
@ -422,12 +422,12 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
i = vec - 64;
irqa = irq_vecs2;
}
#else /* CONFIG_440_GX */
#else /* CONFIG_440GX */
if (vec > 31) {
i = vec - 32;
irqa = irq_vecs1;
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif /* CONFIG_440 */
/*
@ -441,13 +441,13 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
irqa[i].arg = arg;
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
else
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
else
@ -464,7 +464,7 @@ void irq_free_handler (int vec)
int i = vec;
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64)) {
irqa = irq_vecs1;
i = vec - 32;
@ -472,7 +472,7 @@ void irq_free_handler (int vec)
irqa = irq_vecs2;
i = vec - 64;
}
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
if (vec > 31) {
irqa = irq_vecs1;
i = vec - 32;
@ -485,13 +485,13 @@ void irq_free_handler (int vec)
#endif
#if defined(CONFIG_440)
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
if ((vec > 31) && (vec < 64))
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else if (vec > 63)
mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
else
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
if (vec > 31)
mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
else
@ -553,7 +553,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("\n");
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
printf ("\nUIC 2\n");
printf ("Nr Routine Arg Count\n");

8
cpu/ppc4xx/miiphy_440.c
View File

@ -165,13 +165,13 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
}
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_READ;
#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
@ -225,13 +225,13 @@ int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
sta_reg = 0;
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
sta_reg |= EMAC_STACR_WRITE;
#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX)
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */

20
cpu/ppc4xx/serial.c
View File

@ -269,14 +269,14 @@ int serial_tstc ()
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
#else
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
@ -284,7 +284,7 @@ int serial_tstc ()
#define CR0_MASK 0x3fff0000
#define CR0_EXTCLK_ENA 0x00600000
#define CR0_UDIV_POS 16
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#elif defined(CONFIG_405EP)
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
@ -306,17 +306,17 @@ int serial_tstc ()
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#endif
#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
@ -436,7 +436,7 @@ int serial_init(void)
unsigned long tmp;
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
@ -451,7 +451,7 @@ int serial_init(void)
#endif
#else
reg = mfdcr(cntrl0) & ~CR0_MASK;
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
@ -465,7 +465,7 @@ int serial_init(void)
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {

2
cpu/ppc4xx/spd_sdram.c
View File

@ -734,7 +734,7 @@ long int spd_sdram(void) {
*/
check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/*
* Soft-reset SDRAM controller.
*/

4
cpu/ppc4xx/speed.c
View File

@ -195,7 +195,7 @@ ulong get_PCI_freq (void)
#elif defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
void get_sys_info (sys_info_t *sysInfo)
{
unsigned long temp;
@ -283,7 +283,7 @@ ulong get_PCI_freq (void)
return sys_info.freqPCI;
}
#elif !defined(CONFIG_440_GX)
#elif !defined(CONFIG_440GX)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;

18
cpu/ppc4xx/start.S
View File

@ -166,7 +166,7 @@ _start_440:
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */
#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1, mcsr
@ -340,11 +340,11 @@ _start:
mtspr tcr,r0 /* disable all */
mtspr esr,r0 /* clear exception syndrome register */
mtxer r0 /* clear integer exception register */
#if !defined(CONFIG_440_GX)
#if !defined(CONFIG_440GX)
lis r1,0x0002 /* set CE bit (Critical Exceptions) */
ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */
mtmsr r1 /* change MSR */
#elif !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
bl __440gx_msr_set
b __440gx_msr_continue
@ -377,7 +377,7 @@ __440gx_msr_continue:
/* Setup the internal SRAM */
/*----------------------------------------------------------------*/
li r0,0
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* Clear Dcache to use as RAM */
addis r3,r0,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
@ -394,7 +394,7 @@ __440gx_msr_continue:
addi r3,r3,32
bdnz ..d_ag
#else
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
@ -409,7 +409,7 @@ __440gx_msr_continue:
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
ori r1,r1,0x0980 /* first 64k */
mtdcr isram0_sb0cr,r1
lis r1,0x8001
@ -975,7 +975,7 @@ invalidate_icache:
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
#else
@ -1001,7 +1001,7 @@ flush_dcache:
mtdccr r10
/* do loop for # of congruence classes. */
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
@ -1228,7 +1228,7 @@ ppcSync:
*/
.globl relocate_code
relocate_code:
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
addi r1,r0,0x0000 /* Tlb entry #0 */

2
cpu/ppc4xx/usb_ohci.c
View File

@ -76,7 +76,7 @@
#define m16_swap(x) swap_16(x)
#define m32_swap(x) swap_32(x)
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
#define ohci_cpu_to_le16(x) (x)
#define ohci_cpu_to_le32(x) (x)
#else

4
cpu/ppc4xx/usbdev.c
View File

@ -3,7 +3,7 @@
#include <common.h>
#include <asm/processor.h>
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
#include <usb.h>
#include "usbdev.h"
@ -211,4 +211,4 @@ void usb_dev_init()
NULL);
}
#endif /*CONFIG_440_EP */
#endif /*CONFIG_440EP */

2
drivers/pci_indirect.c
View File

@ -52,7 +52,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \

6
fs/jffs2/jffs2_1pass.c
View File

@ -278,13 +278,13 @@ static inline void *get_node_mem_nor(u32 off)
/*
* Generic jffs2 raw memory and node read routines.
* Generic jffs2 raw memory and node read routines.
*
*/
static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf)
{
struct mtdids *id = current_part->dev->id;
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
if (id->type == MTD_DEV_TYPE_NOR)
return get_fl_mem_nor(off);
@ -302,7 +302,7 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf)
static inline void *get_node_mem(u32 off)
{
struct mtdids *id = current_part->dev->id;
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
if (id->type == MTD_DEV_TYPE_NOR)
return get_node_mem_nor(off);

4
include/405gp_enet.h
View File

@ -67,7 +67,7 @@ struct arp_entry {
/*Register addresses */
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
@ -81,7 +81,7 @@ struct arp_entry {
#endif /* CONFIG_440 */
#if defined(CONFIG_440)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)

4
include/440_i2c.h
View File

@ -1,11 +1,11 @@
#ifndef _440_i2c_h_
#define _440_i2c_h_
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
#else
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
#endif /*CONFIG_440_EP CONFIG_440_GR*/
#endif /*CONFIG_440EP CONFIG_440GR*/
#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)

22
include/440gx_enet.h
View File

@ -130,9 +130,9 @@ typedef struct emac_440gx_hw_st {
} EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST;
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define EMAC_NUM_DEV 4
#elif defined(CONFIG_440) && !defined(CONFIG_440_GX)
#elif defined(CONFIG_440) && !defined(CONFIG_440GX)
#define EMAC_NUM_DEV 2
#else
#warning Bad configuration
@ -140,7 +140,7 @@ typedef struct emac_440gx_hw_st {
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
#else
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
@ -212,7 +212,7 @@ typedef struct emac_440gx_hw_st {
/*---------------------------------------------------------------------------+
| TCP/IP Acceleration Hardware (TAH) 440GX Only
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50)
#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
@ -272,11 +272,11 @@ typedef struct emac_440gx_hw_st {
#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/* Ethernet MAC Regsiter Addresses */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
#else
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
@ -319,7 +319,7 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
@ -349,7 +349,7 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M1_OBCI_83 (0x00000010)
#define EMAC_M1_OBCI_66 (0x00000008)
#define EMAC_M1_RSVD1 (0x00000007)
#else /* defined(CONFIG_440_GX) */
#else /* defined(CONFIG_440GX) */
/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
#define EMAC_M1_FDE 0x80000000
#define EMAC_M1_ILE 0x40000000
@ -369,10 +369,10 @@ typedef struct emac_440gx_hw_st {
#define EMAC_M1_TR0_MULTI 0x00008000
#define EMAC_M1_TR1_DEPEND 0x00004000
#define EMAC_M1_TR1_MULTI 0x00002000
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define EMAC_M1_JUMBO_ENABLE 0x00001000
#endif /* defined(CONFIG_440_EP) || defined(CONFIG_440_GR) */
#endif /* defined(CONFIG_440_GX) */
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#endif /* defined(CONFIG_440GX) */
/* Transmit Mode Register 0 */
#define EMAC_TXM0_GNP0 (0x80000000)

8
include/asm-ppc/u-boot.h
View File

@ -101,19 +101,19 @@ typedef struct bd_info {
unsigned char bi_enet3addr[6];
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440_GX) || \
defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
unsigned int bi_opbfreq; /* OPB clock in Hz */
int bi_iic_fast[2]; /* Use fast i2c mode */
#endif
#if defined(CONFIG_NX823)
unsigned char bi_sernum[8];
#endif
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
int bi_phynum[2]; /* Determines phy mapping */
int bi_phymode[2]; /* Determines phy mode */
#endif
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
int bi_phynum[4]; /* Determines phy mapping */
int bi_phymode[4]; /* Determines phy mode */
#endif

2
include/configs/NETTA.h
View File

@ -694,7 +694,7 @@
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_SIZE 0x00100000
#define CONFIG_JFFS2_PART_SIZE 0x00100000
#define CONFIG_JFFS2_PART_OFFSET 0x00200000
/* mtdparts command line support */

2
include/configs/XPEDITE1K.h
View File

@ -36,7 +36,7 @@
#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440_GX 1 /* 440 GX */
#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */

401
include/configs/aev.h Normal file
View File

@ -0,0 +1,401 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2005
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
#define CONFIG_AEVFIFO 1
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#ifdef CONFIG_AEVFIFO
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif /* CONFIG_AEVFIFO */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_I2C)
#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#else
#define CFG_CMD_POST_DIAG 0
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
ADD_BMP_CMD | \
CFG_CMD_PCI | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_NFS | \
CFG_CMD_PING | \
CFG_CMD_POST_DIAG | \
CFG_CMD_REGINFO | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_TIMESTAMP /* display image timestamps */
#if (TEXT_BASE == 0xFC000000) /* Boot low */
# define CFG_LOWBOOT 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath) " \
"console=ttyS0,$(baudrate)\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"flash_self=run ramargs addip;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"flash_nfs=run nfsargs addip;" \
"bootm $(kernel_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"load=tftp 200000 $(u-boot)\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 $(filesize);" \
"protect on FC000000 FC05FFFF\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#ifdef CONFIG_TQM5200_REV100
#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
#else
#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
#endif
/*
* I2C clock frequency
*
* Please notice, that the resulting clock frequency could differ from the
* configured value. This is because the I2C clock is derived from system
* clock over a frequency divider with only a few divider values. U-boot
* calculates the best approximation for CFG_I2C_SPEED. However the calculated
* approximation allways lies below the configured value, never above.
*/
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
* also). For other EEPROMs configuration should be verified. On Mini-FAP the
* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
* same configuration could be used.
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
/*
* Flash configuration
*/
#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
#else /* CFG_LOWBOOT */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
#endif /* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Memory map
*/
#define CFG_MBAR 0xF0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_DEFAULT_MBAR 0x80000000
/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
*
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
* Bit 0 (mask: 0x80000000): 1
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
* Use for REV200 STK52XX boards. Do not use with REV100 modules
* (because, there I2C1 is used as I2C bus)
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
* 000 -> All PSC2 pins are GIOPs
* 001 -> CAN1/2 on PSC2 pins
* Use for REV100 STK52xx boards
* use PSC6:
* on STK52xx:
* use as UART. Pins PSC6_0 to PSC6_3 are used.
* Bits 9:11 (mask: 0x00700000):
* 101 -> PSC6 : Extended POST test is not available
* on MINI-FAP and TQM5200_IB:
* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
* 000 -> PSC6 could not be used as UART, CODEC or IrDA
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
* tests.
*/
#define CFG_GPS_PORT_CONFIG 0x81500014
/*
* RTC configuration
*/
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
*/
#define CONFIG_LOOPW
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
/* automatic configuration of chip selects */
#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#define CFG_CS2_START 0xE5000000
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
#define CFG_CS2_CFG 0x0004D930
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
#define CFG_RESET_ADDRESS 0xff000000
#endif /* __CONFIG_H */

144
include/configs/bamboo.h
View File

@ -31,12 +31,19 @@
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/*
* Please note that, if NAND support is enabled, the 2nd ethernet port
* can't be used because of pin multiplexing. So, if you want to use the
* 2nd ethernet port you have to "undef" the following define.
*/
#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
@ -58,13 +65,15 @@
#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_NAND_ADDR 0x90000000
#define CFG_NAND2_ADDR 0x94000000
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x1000
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@ -88,7 +97,7 @@
* The DS1558 code assumes this condition
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*-----------------------------------------------------------------------
@ -118,21 +127,80 @@
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#if 0 /* test-only */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* NAND-FLASH related
*----------------------------------------------------------------------*/
#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
#define NAND0_CMD_READ2 0x50
#define NAND0_CMD_READ_ID 0x90
#define NAND0_CMD_READ_STATUS 0x70
#define NAND0_CMD_RESET 0xFF
#define NAND0_CMD_PAGE_PROG 0x80
#define NAND0_CMD_PAGE_PROG_TRUE 0x10
#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
#define NAND0_CMD_BLOCK_ERASE 0x60
#define NAND0_CMD_BLOCK_ERASE_END 0xD0
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
/* not needed with 440EP NAND controller */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------------- */
@ -206,10 +274,14 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#ifndef CONFIG_BAMBOO_NAND
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#endif /* CONFIG_BAMBOO_NAND */
#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
@ -219,17 +291,24 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#endif /*CONFIG_440EP*/
#ifdef CONFIG_BAMBOO_NAND
#define _CFG_CMD_NAND CFG_CMD_NAND
#else
#define _CFG_CMD_NAND 0
#endif /* CONFIG_BAMBOO_NAND */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_EEPROM | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
@ -244,6 +323,7 @@
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_USB | \
_CFG_CMD_NAND | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@ -253,42 +333,42 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
@ -300,7 +380,7 @@
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */

6
include/configs/bubinga.h
View File

@ -127,6 +127,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
@ -199,8 +203,6 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------

2
include/configs/hmi1001.h
View File

@ -287,6 +287,8 @@
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA

2
include/configs/ocotea.h
View File

@ -40,7 +40,7 @@
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_OCOTEA 1 /* Board is ebony */
#define CONFIG_440_GX 1 /* Specifc GX support */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */

548
include/configs/spieval.h Normal file
View File

@ -0,0 +1,548 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2005
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_STK52XX
#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
#define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_STK52XX */
/*
* PCI Mapping:
* 0x40000000 - 0x4fffffff - PCI Memory
* 0x50000000 - 0x50ffffff - PCI IO Space
*/
#ifdef CONFIG_STK52XX
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x50000000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
#ifdef CONFIG_PCI
#define ADD_PCI_CMD CFG_CMD_PCI
#else
#define ADD_PCI_CMD 0
#endif
/*
* Video console
*/
#if 1
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
#endif
#ifdef CONFIG_VIDEO
#define ADD_BMP_CMD CFG_CMD_BMP
#else
#define ADD_BMP_CMD 0
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
/* USB */
#ifdef CONFIG_STK52XX
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD 0
#endif
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_I2C)
#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#else
#define CFG_CMD_POST_DIAG 0
#endif
/* IDE */
#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
#else
#define ADD_IDE_CMD 0
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
ADD_BMP_CMD | \
ADD_IDE_CMD | \
ADD_PCI_CMD | \
ADD_USB_CMD | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_MII | \
CFG_CMD_NFS | \
CFG_CMD_PING | \
CFG_CMD_POST_DIAG | \
CFG_CMD_REGINFO | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_TIMESTAMP /* display image timestamps */
#if (TEXT_BASE == 0xFC000000) /* Boot low */
# define CFG_LOWBOOT 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#if defined (CONFIG_TQM5200_AA)
# define CONFIG_U_BOOT_SUFFIX "-AA\0"
#elif defined (CONFIG_TQM5200_AB)
# define CONFIG_U_BOOT_SUFFIX "-AB\0"
#elif defined (CONFIG_TQM5200_AC)
# define CONFIG_U_BOOT_SUFFIX "-AC\0"
#else
# define CONFIG_U_BOOT_SUFFIX "\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"flash_self=run ramargs addip;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"flash_nfs=run nfsargs addip;" \
"bootm $(kernel_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"load=tftp 200000 $(u-boot)\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 $(filesize);" \
"protect on FC000000 FC05FFFF\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#ifdef CONFIG_TQM5200_REV100
#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
#else
#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
#endif
/*
* I2C clock frequency
*
* Please notice, that the resulting clock frequency could differ from the
* configured value. This is because the I2C clock is derived from system
* clock over a frequency divider with only a few divider values. U-boot
* calculates the best approximation for CFG_I2C_SPEED. However the calculated
* approximation allways lies below the configured value, never above.
*/
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
* also). For other EEPROMs configuration should be verified. On Mini-FAP the
* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
* same configuration could be used.
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
/*
* HW-Monitor configuration on Mini-FAP
*/
#if defined (CONFIG_MINIFAP)
#define CFG_I2C_HWMON_ADDR 0x2C
#endif
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
CFG_I2C_SLAVE }
#elif defined (CONFIG_TQM5200_AC)
#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
#endif
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
CFG_I2C_HWMON_ADDR, \
CFG_I2C_SLAVE }
#endif
/*
* Flash configuration
*/
#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
#else /* CFG_LOWBOOT */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
#endif /* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Memory map
*/
#define CFG_MBAR 0xF0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_DEFAULT_MBAR 0x80000000
/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
*
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
* Bit 0 (mask: 0x80000000): 1
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
* Use for REV200 STK52XX boards. Do not use with REV100 modules
* (because, there I2C1 is used as I2C bus)
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
* 000 -> All PSC2 pins are GIOPs
* 001 -> CAN1/2 on PSC2 pins
* Use for REV100 STK52xx boards
* use PSC6:
* on STK52xx:
* use as UART. Pins PSC6_0 to PSC6_3 are used.
* Bits 9:11 (mask: 0x00700000):
* 101 -> PSC6 : Extended POST test is not available
* on MINI-FAP and TQM5200_IB:
* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
* 000 -> PSC6 could not be used as UART, CODEC or IrDA
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
* tests.
*/
#if defined (CONFIG_MINIFAP)
# define CFG_GPS_PORT_CONFIG 0x91000004
#elif defined (CONFIG_STK52XX)
# if defined (CONFIG_STK52XX_REV100)
# define CFG_GPS_PORT_CONFIG 0x81500014
# else /* STK52xx REV200 and above */
# if defined (CONFIG_TQM5200_REV100)
# error TQM5200 REV100 not supported on STK52XX REV200 or above
# else/* TQM5200 REV200 and above */
# define CFG_GPS_PORT_CONFIG 0x91500004
# endif
# endif
#else /* TMQ5200 Inbetriebnahme-Board */
# define CFG_GPS_PORT_CONFIG 0x81000004
#endif
/*
* RTC configuration
*/
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
*/
#define CONFIG_LOOPW
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
/* automatic configuration of chip selects */
#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
#else /* CONFIG_CS_AUTOCONF */
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#endif
#define CFG_CS2_CFG 0x0004D930
#endif
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
#define CFG_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#endif /* __CONFIG_H */

8
include/configs/yellowstone.h
View File

@ -29,7 +29,7 @@
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */
#define CONFIG_440_GR 1 /* Specific PPC440GR support */
#define CONFIG_440GR 1 /* Specific PPC440GR support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
@ -161,14 +161,14 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#endif /*CONFIG_440EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
@ -176,7 +176,7 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \

276
include/configs/yosemite.h
View File

@ -1,4 +1,6 @@
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -28,56 +30,53 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */
#define CONFIG_YOSEMITE 1 /* Board is Yosemite */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_BOOT_BASE_ADDR 0xf0000000
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 9600
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
@ -85,26 +84,21 @@
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
* The DS1558 code assumes this condition
*
* Environment
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*
* Define here the location of the environment variables (FLASH or EEPROM).
* Note: DENX encourages to use redundant environment in FLASH.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#if 1 /* test-only */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
#else
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
@ -116,12 +110,24 @@
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#endif
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
/*-----------------------------------------------------------------------
* I2C
@ -131,58 +137,84 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CFG_I2C_MULTI_EEPROMS
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
#define CONFIG_BOOTDELAY 3 /* disable autoboot */
#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#endif /* CFG_ENV_IS_IN_EEPROM */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=yosemite\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):$(netdev):off panic=1\0" \
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yosemite/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc100000\0" \
"load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 100000 fff80000 80000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.4.251
#define CONFIG_ETHADDR 00:10:EC:00:12:34
#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_SERVERIP 10.0.4.115
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440_EP
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440_EP*/
#endif /*CONFIG_440EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
@ -190,53 +222,21 @@
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#ifdef CONFIG_440_EP
/* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS)
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS)
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_USB )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -245,42 +245,42 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
@ -288,10 +288,11 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
@ -309,4 +310,5 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

34
include/linux/list.h
View File

@ -30,7 +30,7 @@ struct list_head {
} while (0)
/*
* Insert a new entry between two known consecutive entries.
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
@ -103,7 +103,7 @@ static inline void list_del(struct list_head *entry)
static inline void list_del_init(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
INIT_LIST_HEAD(entry);
INIT_LIST_HEAD(entry);
}
/**
@ -113,8 +113,8 @@ static inline void list_del_init(struct list_head *entry)
*/
static inline void list_move(struct list_head *list, struct list_head *head)
{
__list_del(list->prev, list->next);
list_add(list, head);
__list_del(list->prev, list->next);
list_add(list, head);
}
/**
@ -125,8 +125,8 @@ static inline void list_move(struct list_head *list, struct list_head *head)
static inline void list_move_tail(struct list_head *list,
struct list_head *head)
{
__list_del(list->prev, list->next);
list_add_tail(list, head);
__list_del(list->prev, list->next);
list_add_tail(list, head);
}
/**
@ -195,7 +195,7 @@ static inline void list_splice_init(struct list_head *list,
*/
#define list_for_each(pos, head) \
for (pos = (head)->next, prefetch(pos->next); pos != (head); \
pos = pos->next, prefetch(pos->next))
pos = pos->next, prefetch(pos->next))
/**
* list_for_each_prev - iterate over a list backwards
* @pos: the &struct list_head to use as a loop counter.
@ -203,8 +203,8 @@ static inline void list_splice_init(struct list_head *list,
*/
#define list_for_each_prev(pos, head) \
for (pos = (head)->prev, prefetch(pos->prev); pos != (head); \
pos = pos->prev, prefetch(pos->prev))
pos = pos->prev, prefetch(pos->prev))
/**
* list_for_each_safe - iterate over a list safe against removal of list entry
* @pos: the &struct list_head to use as a loop counter.
@ -224,7 +224,7 @@ static inline void list_splice_init(struct list_head *list,
#define list_for_each_entry(pos, head, member) \
for (pos = list_entry((head)->next, typeof(*pos), member), \
prefetch(pos->member.next); \
&pos->member != (head); \
&pos->member != (head); \
pos = list_entry(pos->member.next, typeof(*pos), member), \
prefetch(pos->member.next))
@ -237,16 +237,16 @@ static inline void list_splice_init(struct list_head *list,
*/
#define list_for_each_entry_safe(pos, n, head, member) \
for (pos = list_entry((head)->next, typeof(*pos), member), \
n = list_entry(pos->member.next, typeof(*pos), member); \
&pos->member != (head); \
n = list_entry(pos->member.next, typeof(*pos), member); \
&pos->member != (head); \
pos = n, n = list_entry(n->member.next, typeof(*n), member))
/**
* list_for_each_entry_continue - iterate over list of given type
* continuing after existing point
* @pos: the type * to use as a loop counter.
* @head: the head for your list.
* @member: the name of the list_struct within the struct.
* list_for_each_entry_continue - iterate over list of given type
* continuing after existing point
* @pos: the type * to use as a loop counter.
* @head: the head for your list.
* @member: the name of the list_struct within the struct.
*/
#define list_for_each_entry_continue(pos, head, member) \
for (pos = list_entry(pos->member.next, typeof(*pos), member), \

44
include/ppc440.h
View File

@ -78,7 +78,7 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@ -241,7 +241,7 @@
#define xbcfg 0x23 /* external bus configuration reg */
#define xbcid 0x23 /* external bus core id reg */
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* PLB4 to PLB3 Bridge OUT */
#define P4P3_DCR_BASE 0x020
@ -504,7 +504,7 @@
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
@ -515,8 +515,8 @@
#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
#endif /* CONFIG_440_GX */
#endif /* !CONFIG_440_EP !CONFIG_440_GR*/
#endif /* CONFIG_440GX */
#endif /* !CONFIG_440EP !CONFIG_440GR*/
/*-----------------------------------------------------------------------------
| On-Chip Buses
@ -527,7 +527,7 @@
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
#if defined (CONFIG_440_GX)
#if defined (CONFIG_440GX)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
@ -573,7 +573,7 @@
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define UIC2_DCR_BASE 0x210
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
@ -594,7 +594,7 @@
#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/* The following is for compatibility with 405 code */
#define uicsr uic0sr
@ -673,16 +673,16 @@
#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
@ -770,7 +770,7 @@
/*---------------------------------------------------------------------------+
| Universal interrupt controller 2 interrupts (UIC2)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define UIC_ETH2 0x80000000 /* Ethernet 2 */
#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
#define UIC_ETH3 0x20000000 /* Ethernet 3 */
@ -803,12 +803,12 @@
#define UIC_RSVD29 0x00000004 /* Reserved */
#define UIC_RSVD30 0x00000002 /* Reserved */
#define UIC_RSVD31 0x00000001 /* Reserved */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller Base 0 interrupts (UICB0)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440_GX)
#if defined(CONFIG_440GX)
#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
@ -818,7 +818,7 @@
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*-----------------------------------------------------------------------------+
| External Bus Controller Bit Settings
@ -1194,7 +1194,7 @@
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
#if !defined (CONFIG_440_GX) && !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR)
#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
@ -1212,7 +1212,7 @@
#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
#else /* !CONFIG_440_GX or CONFIG_440_EP or CONFIG_440_GR */
#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
@ -1260,7 +1260,7 @@
#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
#endif /* CONFIG_440_GX */
#endif /* CONFIG_440GX */
/*-----------------------------------------------------------------------------
| IIC Register Offsets
@ -1303,7 +1303,7 @@
#define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
#define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
/* PCI Local Configuration Registers
--------------------------------- */
@ -1387,12 +1387,12 @@
#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
#endif /* !defined(CONFIG_440_EP) !defined(CONFIG_440_GR) */
#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
/******************************************************************************
* GPIO macro register defines
******************************************************************************/
#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define GPIO_BASE0 (CFG_PERIPHERAL_BASE+0x00000B00)
#define GPIO_BASE1 (CFG_PERIPHERAL_BASE+0x00000C00)

2
lib_ppc/board.c
View File

@ -547,7 +547,7 @@ void board_init_f (ulong bootflag)
bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
bd->bi_plb_busfreq = gd->bus_clk;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
bd->bi_pci_busfreq = get_PCI_freq ();
bd->bi_opbfreq = get_OPB_freq ();
#elif defined(CONFIG_XILINX_ML300)