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Merge git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini
2018-01-11 11:18:49 -05:00
parent 2ff1da9453 1cabeb88eb
commit 6bf634223a
47 changed files with 641 additions and 390 deletions
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29
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@@ -23,6 +23,8 @@
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
@@ -41,6 +43,33 @@
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
CONFIG_SYS_BMAN_MEM_BASE)
#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \
CONFIG_SYS_QMAN_MEM_BASE)
#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)

2
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View File

@@ -88,6 +88,8 @@ struct cpu_type {
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
#define AHCI_PORT_PHY2_CFG 0x28184d1f
#define AHCI_PORT_PHY3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff

3
arch/arm/include/asm/arch-fsl-layerscape/speed.h
View File

@@ -7,4 +7,7 @@
#ifndef _FSL_LAYERSCAPE_SPEED_H
#define _FSL_LAYERSCAPE_SPEED_H
void get_sys_info(struct sys_info *sys_info);
#ifdef CONFIG_SYS_DPAA_QBMAN
unsigned long get_qman_freq(void);
#endif
#endif /* _FSL_LAYERSCAPE_SPEED_H */

16
arch/arm/include/asm/fsl_secure_boot.h
View File

@@ -26,6 +26,14 @@
#define CONFIG_KEY_REVOCATION
#if defined(CONFIG_FSL_LAYERSCAPE)
/*
* For fsl layerscape based platforms, ESBC image Address in Header
* is 64 bit.
*/
#define CONFIG_ESBC_ADDR_64BIT
#endif
#ifndef CONFIG_SPL_BUILD
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
@@ -42,14 +50,6 @@
#endif
#if defined(CONFIG_FSL_LAYERSCAPE)
/*
* For fsl layerscape based platforms, ESBC image Address in Header
* is 64 bit.
*/
#define CONFIG_ESBC_ADDR_64BIT
#endif
#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xa0000000;" \