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Merge git://git.denx.de/u-boot-socfpga

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This commit is contained in:
Tom Rini 2018-01-11 11:18:41 -05:00
commit 2ff1da9453
14 changed files with 23 additions and 6 deletions
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4
arch/arm/mach-socfpga/clock_manager.c
View File

@ -59,7 +59,8 @@ int set_cpu_clk_info(void)
return 0;
}
int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifndef CONFIG_SPL_BUILD
static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
cm_print_clock_quick_summary();
return 0;
@ -70,3 +71,4 @@ U_BOOT_CMD(
"display clocks",
""
);
#endif

13
arch/arm/mach-socfpga/misc_gen5.c
View File

@ -30,14 +30,10 @@ static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
/*
* DesignWare Ethernet initialization
@ -292,6 +288,12 @@ int arch_early_init_r(void)
return 0;
}
#ifndef CONFIG_SPL_BUILD
static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
static void socfpga_sdram_apply_static_cfg(void)
{
const u32 applymask = 0x8;
@ -321,7 +323,7 @@ static void socfpga_sdram_apply_static_cfg(void)
: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
}
int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
if (argc != 2)
return CMD_RET_USAGE;
@ -357,3 +359,4 @@ U_BOOT_CMD(
"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
""
);
#endif

1
configs/socfpga_arria10_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_DOS_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/socfpga_arria5_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_cyclone5_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_de0_nano_soc_defconfig
View File

@ -37,6 +37,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_de10_nano_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y

1
configs/socfpga_de1_soc_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y

1
configs/socfpga_is1_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_mcvevk_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_sockit_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_socrates_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_sr1500_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_CMD_UBI=y

1
configs/socfpga_vining_fpga_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_PART=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);"
CONFIG_CMD_UBI=y