arm64: add better and more generic spin-table support

There are two enable methods supported by ARM64 Linux; psci and
spin-table.  The latter is simpler and helpful for quick SoC bring
up.  My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.

Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:

  - We must hard-code CPU_RELEASE_ADDR so that it matches the
    "cpu-release-addr" property in the DT that comes from the
    kernel tree.

  - The Documentation/arm64/booting.txt in Linux requires that
    the release address must be zero-initialized, but it is not
    cared by the common code in U-Boot.  We must do it in a board
    function.

  - There is no systematic way to protect the spin-table code from
    the kernel.  We are supposed to do it in a board specific manner,
    but it is difficult to predict where the spin-table code will be
    located after the relocation.  So, it also makes difficult to
    hard-code /memreserve/ in the DT of the kernel.

So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
2016-06-27 19:31:05 +09:00
committed by Tom Rini
parent 3a592a1349
commit 6b6024eadb
7 changed files with 134 additions and 4 deletions

View File

@@ -21,6 +21,7 @@
#include <asm/armv7.h>
#endif
#include <asm/psci.h>
#include <asm/spin_table.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -45,6 +46,12 @@ int arch_fixup_fdt(void *blob)
if (ret)
return ret;
#ifdef CONFIG_ARMV8_SPIN_TABLE
ret = spin_table_update_dt(blob);
if (ret)
return ret;
#endif
#ifdef CONFIG_ARMV7_NONSEC
ret = psci_update_dt(blob);
if (ret)