arm64: add better and more generic spin-table support
There are two enable methods supported by ARM64 Linux; psci and spin-table. The latter is simpler and helpful for quick SoC bring up. My main motivation for this patch is to improve the spin-table support, which allows us to boot an ARMv8 system without the ARM Trusted Firmware. Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S and the spin-table is supported in a really ad-hoc way, and I see some problems: - We must hard-code CPU_RELEASE_ADDR so that it matches the "cpu-release-addr" property in the DT that comes from the kernel tree. - The Documentation/arm64/booting.txt in Linux requires that the release address must be zero-initialized, but it is not cared by the common code in U-Boot. We must do it in a board function. - There is no systematic way to protect the spin-table code from the kernel. We are supposed to do it in a board specific manner, but it is difficult to predict where the spin-table code will be located after the relocation. So, it also makes difficult to hard-code /memreserve/ in the DT of the kernel. So, here is a patch to solve those problems; the DT is run-time modified to reserve the spin-table code (+ cpu-release-addr). Also, the "cpu-release-addr" property is set to an appropriate address after the relocation, which means we no longer need the hard-coded CPU_RELEASE_ADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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3a592a1349
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@ -3,4 +3,22 @@ if ARM64
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config ARMV8_MULTIENTRY
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boolean "Enable multiple CPUs to enter into U-Boot"
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config ARMV8_SPIN_TABLE
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bool "Support spin-table enable method"
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depends on ARMV8_MULTIENTRY && OF_LIBFDT
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help
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Say Y here to support "spin-table" enable method for booting Linux.
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To use this feature, you must do:
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- Specify enable-method = "spin-table" in each CPU node in the
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Device Tree you are using to boot the kernel
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- Let secondary CPUs in U-Boot (in a board specific manner)
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before the master CPU jumps to the kernel
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U-Boot automatically does:
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- Set "cpu-release-addr" property of each CPU node
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(overwrites it if already exists).
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- Reserve the code for the spin-table and the release address
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via a /memreserve/ region in the Device Tree.
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endif
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@ -15,6 +15,9 @@ obj-y += cache.o
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obj-y += tlb.o
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obj-y += transition.o
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obj-y += fwcall.o
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ifndef CONFIG_SPL_BUILD
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obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
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endif
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obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
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obj-$(CONFIG_S32V234) += s32v234/
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63
arch/arm/cpu/armv8/spin_table.c
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63
arch/arm/cpu/armv8/spin_table.c
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@ -0,0 +1,63 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <asm/spin_table.h>
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int spin_table_update_dt(void *fdt)
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{
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int cpus_offset, offset;
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const char *prop;
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int ret;
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unsigned long rsv_addr = (unsigned long)&spin_table_reserve_begin;
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unsigned long rsv_size = &spin_table_reserve_end -
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&spin_table_reserve_begin;
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cpus_offset = fdt_path_offset(fdt, "/cpus");
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if (cpus_offset < 0)
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return -ENODEV;
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for (offset = fdt_first_subnode(fdt, cpus_offset);
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offset >= 0;
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offset = fdt_next_subnode(fdt, offset)) {
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prop = fdt_getprop(fdt, offset, "device_type", NULL);
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if (!prop || strcmp(prop, "cpu"))
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continue;
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/*
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* In the first loop, we check if every CPU node specifies
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* spin-table. Otherwise, just return successfully to not
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* disturb other methods, like psci.
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*/
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prop = fdt_getprop(fdt, offset, "enable-method", NULL);
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if (!prop || strcmp(prop, "spin-table"))
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return 0;
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}
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for (offset = fdt_first_subnode(fdt, cpus_offset);
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offset >= 0;
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offset = fdt_next_subnode(fdt, offset)) {
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prop = fdt_getprop(fdt, offset, "device_type", NULL);
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if (!prop || strcmp(prop, "cpu"))
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continue;
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ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr",
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(unsigned long)&spin_table_cpu_release_addr);
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if (ret)
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return -ENOSPC;
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}
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ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
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if (ret)
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return -ENOSPC;
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printf(" Reserved memory region for spin-table: addr=%lx size=%lx\n",
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rsv_addr, rsv_size);
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return 0;
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}
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23
arch/arm/cpu/armv8/spin_table_v8.S
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23
arch/arm/cpu/armv8/spin_table_v8.S
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@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/linkage.h>
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ENTRY(spin_table_secondary_jump)
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.globl spin_table_reserve_begin
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spin_table_reserve_begin:
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0: wfe
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ldr x0, spin_table_cpu_release_addr
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cbz x0, 0b
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br x0
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.globl spin_table_cpu_release_addr
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.align 3
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spin_table_cpu_release_addr:
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.quad 0
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.globl spin_table_reserve_end
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spin_table_reserve_end:
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ENDPROC(spin_table_secondary_jump)
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@ -94,7 +94,11 @@ reset:
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/* Processor specific initialization */
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bl lowlevel_init
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#ifdef CONFIG_ARMV8_MULTIENTRY
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#if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE)
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branch_if_master x0, x1, master_cpu
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b spin_table_secondary_jump
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/* never return */
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#elif defined(CONFIG_ARMV8_MULTIENTRY)
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branch_if_master x0, x1, master_cpu
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/*
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@ -106,10 +110,8 @@ slave_cpu:
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ldr x0, [x1]
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cbz x0, slave_cpu
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br x0 /* branch to the given address */
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master_cpu:
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/* On the master CPU */
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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master_cpu:
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bl _main
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#ifdef CONFIG_SYS_RESET_SCTRL
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14
arch/arm/include/asm/spin_table.h
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14
arch/arm/include/asm/spin_table.h
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@ -0,0 +1,14 @@
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/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_SPIN_TABLE_H__
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#define __ASM_SPIN_TABLE_H__
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extern u64 spin_table_cpu_release_addr;
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extern char spin_table_reserve_begin;
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extern char spin_table_reserve_end;
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int spin_table_update_dt(void *fdt);
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#endif /* __ASM_SPIN_TABLE_H__ */
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@ -21,6 +21,7 @@
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#include <asm/armv7.h>
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#endif
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#include <asm/psci.h>
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#include <asm/spin_table.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -45,6 +46,12 @@ int arch_fixup_fdt(void *blob)
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if (ret)
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return ret;
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#ifdef CONFIG_ARMV8_SPIN_TABLE
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ret = spin_table_update_dt(blob);
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if (ret)
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return ret;
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#endif
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#ifdef CONFIG_ARMV7_NONSEC
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ret = psci_update_dt(blob);
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if (ret)
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