ppc: Zap IDS8247 board
This board is old and is using CONFIG_I2C_X, which is wrong. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de>
This commit is contained in:
Marek Vasut
Wolfgang Denk
parent
4109cb023f
commit
6afb3574c9
@ -52,9 +52,6 @@ config TARGET_MPC8266ADS
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config TARGET_VOVPN_GW
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bool "Support VoVPN-GW"
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config TARGET_IDS8247
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bool "Support IDS8247"
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config TARGET_KM82XX
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bool "Support km82xx"
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@ -75,7 +72,6 @@ source "board/ep82xxm/Kconfig"
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source "board/freescale/mpc8266ads/Kconfig"
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source "board/funkwerk/vovpn-gw/Kconfig"
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source "board/gw8260/Kconfig"
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source "board/ids/ids8247/Kconfig"
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source "board/iphase4539/Kconfig"
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source "board/keymile/km82xx/Kconfig"
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source "board/muas3001/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_IDS8247
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config SYS_BOARD
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default "ids8247"
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config SYS_VENDOR
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default "ids"
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config SYS_CONFIG_NAME
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default "IDS8247"
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endif
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@ -1,6 +0,0 @@
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IDS8247 BOARD
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M: Heiko Schocher <hs@denx.de>
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S: Maintained
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F: board/ids/ids8247/
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F: include/configs/IDS8247.h
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F: configs/IDS8247_defconfig
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@ -1,11 +0,0 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2005
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# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = ids8247.o
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@ -1,390 +0,0 @@
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/*
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* (C) Copyright 2005
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* Heiko Schocher, DENX Software Engineering, <hs@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <libfdt_env.h>
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#include <fdt_support.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
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/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
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/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
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/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
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/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
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/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
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/* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
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#if defined(CONFIG_SYS_I2C_SOFT)
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/* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
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/* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
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#else /* normal I/O port pins */
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/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
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/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
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#endif
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/* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
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/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
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/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
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/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
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/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
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/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
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/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
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/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
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/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
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/* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
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/* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
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/* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
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/* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
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/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
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/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
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/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
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/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
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/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
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/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
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/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
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/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
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/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
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/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
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/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
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/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
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/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
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/* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
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/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
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/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
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/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
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/* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
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/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
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/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
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/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
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/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
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/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
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/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
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/* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
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/* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
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/* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
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/* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
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/* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
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/* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
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/* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
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/* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
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/* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
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#if defined(CONFIG_HARD_I2C)
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
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#else /* normal I/O port pins */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
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/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
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#endif
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
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/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
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/* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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/* ------------------------------------------------------------------------- */
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/* Check Board Identity:
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*/
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int checkboard (void)
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{
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puts ("Board: IDS 8247\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
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*
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* This routine performs standard 8260 initialization sequence
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* and calculates the available memory size. It may be called
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* several times to try different SDRAM configurations on both
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* 60x and local buses.
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*/
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static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
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ulong orx, volatile uchar * base)
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{
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volatile uchar c = 0xff;
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volatile uint *sdmr_ptr;
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volatile uint *orx_ptr;
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ulong maxsize, size;
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int i;
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/* We must be able to test a location outsize the maximum legal size
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* to find out THAT we are outside; but this address still has to be
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* mapped by the controller. That means, that the initial mapping has
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* to be (at least) twice as large as the maximum expected size.
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*/
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maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
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sdmr_ptr = &memctl->memc_psdmr;
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orx_ptr = &memctl->memc_or2;
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*orx_ptr = orx;
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/*
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* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
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*
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* "At system reset, initialization software must set up the
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* programmable parameters in the memory controller banks registers
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* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
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* system software should execute the following initialization sequence
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* for each SDRAM device.
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*
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* 1. Issue a PRECHARGE-ALL-BANKS command
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* 2. Issue eight CBR REFRESH commands
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* 3. Issue a MODE-SET command to initialize the mode register
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*
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* The initial commands are executed by setting P/LSDMR[OP] and
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* accessing the SDRAM with a single-byte transaction."
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*
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* The appropriate BRx/ORx registers have already been set when we
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* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
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*/
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*sdmr_ptr = sdmr | PSDMR_OP_PREA;
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*base = c;
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*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++)
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*base = c;
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*sdmr_ptr = sdmr | PSDMR_OP_MRW;
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*(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
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*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
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*base = c;
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size = get_ram_size((long *)base, maxsize);
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*orx_ptr = orx | ~(size - 1);
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return (size);
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}
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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long psize;
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psize = 16 * 1024 * 1024;
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memctl->memc_psrt = CONFIG_SYS_PSRT;
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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#ifndef CONFIG_SYS_RAMBOOT
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/* 60x SDRAM setup:
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*/
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psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
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(uchar *) CONFIG_SYS_SDRAM_BASE);
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#endif /* CONFIG_SYS_RAMBOOT */
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icache_enable ();
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return (psize);
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}
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int misc_init_r (void)
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{
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gd->bd->bi_flashstart = 0xff800000;
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return 0;
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}
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#include <linux/mtd/mtd.h>
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#include <asm/io.h>
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static u8 hwctl;
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static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE ) {
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hwctl |= 0x1;
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writeb(0x00, (this->IO_ADDR_W + 0x0a));
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} else {
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hwctl &= ~0x1;
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writeb(0x00, (this->IO_ADDR_W + 0x08));
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}
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if ( ctrl & NAND_ALE ) {
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hwctl |= 0x2;
|
||||
writeb(0x00, (this->IO_ADDR_W + 0x09));
|
||||
} else {
|
||||
hwctl &= ~0x2;
|
||||
writeb(0x00, (this->IO_ADDR_W + 0x08));
|
||||
}
|
||||
if ( (ctrl & NAND_NCE) != NAND_NCE)
|
||||
writeb(0x00, (this->IO_ADDR_W + 0x0c));
|
||||
else
|
||||
writeb(0x00, (this->IO_ADDR_W + 0x08));
|
||||
}
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
|
||||
}
|
||||
|
||||
static u_char ids_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
return readb(this->IO_ADDR_R);
|
||||
}
|
||||
|
||||
static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand = mtd->priv;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (hwctl & 0x1)
|
||||
writeb(buf[i], (nand->IO_ADDR_W + 0x02));
|
||||
else if (hwctl & 0x2)
|
||||
writeb(buf[i], (nand->IO_ADDR_W + 0x01));
|
||||
else
|
||||
writeb(buf[i], nand->IO_ADDR_W);
|
||||
}
|
||||
}
|
||||
|
||||
static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
buf[i] = readb(this->IO_ADDR_R);
|
||||
}
|
||||
}
|
||||
|
||||
static int ids_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
/* constant delay (see also tR in the datasheet) */
|
||||
udelay(12);
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
|
||||
/* Reference hardware control function */
|
||||
nand->cmd_ctrl = ids_nand_hwctrl;
|
||||
nand->read_byte = ids_nand_read_byte;
|
||||
nand->write_buf = ids_nand_write_buf;
|
||||
nand->read_buf = ids_nand_read_buf;
|
||||
nand->dev_ready = ids_nand_dev_ready;
|
||||
nand->chip_delay = 12;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NAND */
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup( blob, bd);
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
||||
@ -1,3 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC8260=y
|
||||
CONFIG_TARGET_IDS8247=y
|
||||
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
IDS8247 powerpc mpc8260 - - Heiko Schocher <hs@denx.de>
|
||||
HWW1U1A powerpc mpc85xx - - Kyle Moffett <Kyle.D.Moffett@boeing.com>
|
||||
hymod powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>
|
||||
MHPC powerpc mpc8xx - - Frank Gottschling <fgottschling@eltec.de>
|
||||
|
||||
@ -1,462 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Heiko Schocher, DENX Software Engineering, <hs@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC8272_FAMILY 1
|
||||
#define CONFIG_IDS8247 1
|
||||
#define CPU_ID_STR "MPC8247"
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfff00000
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw " \
|
||||
"console=ttyS0,115200\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"bootfile=/tftpboot/IDS8247/uImage\0" \
|
||||
"kernel_addr=ff800000\0" \
|
||||
"ramdisk_addr=ffa00000\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
|
||||
#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00000080)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
|
||||
#define I2C_READ ((iop->pdat & 0x00000080) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
|
||||
else iop->pdat &= ~0x00000080
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
|
||||
else iop->pdat &= ~0x00000100
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
#if 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
#define CONFIG_I2C_X
|
||||
#endif
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
* use the extern UART for the console
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
|
||||
#define CONFIG_SYS_NS16550_CLK 14745600
|
||||
|
||||
#define CONFIG_SYS_UART_BASE 0xE0000000
|
||||
#define CONFIG_SYS_UART_SIZE 0x10000
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000)
|
||||
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000"
|
||||
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC)
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
|
||||
#define CONFIG_ETHER_ON_FCC1
|
||||
#define FCC_ENET
|
||||
|
||||
/*
|
||||
* - Rx-CLK is CLK10
|
||||
* - Tx-CLK is CLK9
|
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
||||
* - Enable Full Duplex in FSMR
|
||||
*/
|
||||
# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
|
||||
# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
|
||||
# define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
|
||||
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
|
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
#define CONFIG_RTC_PCF8563
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 }
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
/* What should the base address of the main FLASH be and how big is
|
||||
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
|
||||
* The main FLASH is whichever is connected to *CS0.
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
|
||||
#define CONFIG_SYS_FLASH0_SIZE 8
|
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
/* Environment in flash */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000)
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND-FLASH stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
|
||||
#define CONFIG_SYS_NAND0_BASE 0xE1000000
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
|
||||
#endif /* CONFIG_CMD_NAND */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*
|
||||
* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
|
||||
* defines for the various registers affected by the HRCW e.g. changing
|
||||
* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
|
||||
*/
|
||||
#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
|
||||
|
||||
/* no slaves so just fill with zeros */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*
|
||||
* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control - initially enable both caches and
|
||||
* invalidate contents, then the final state leaves only the instruction
|
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
||||
* but Soft reset does not.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
|
||||
#define CONFIG_SYS_HID0_FINAL 0
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5
|
||||
*-----------------------------------------------------------------------
|
||||
* turn on Checkstop Reset Enable
|
||||
*/
|
||||
#define CONFIG_SYS_RMR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_BCR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*/
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
* Ensure DFBRG is Divide by 16
|
||||
*/
|
||||
#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Device
|
||||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 16 bit FLASH
|
||||
* 1 60x GPCM 8 bit NAND
|
||||
* 2 60x SDRAM 32 bit SDRAM
|
||||
* 3 60x GPCM 8 bit UART
|
||||
*
|
||||
*/
|
||||
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
|
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2]
|
||||
*/
|
||||
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x6600
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_MRS_OFFS 0x00000110
|
||||
|
||||
|
||||
/* Bank 0 - FLASH
|
||||
*/
|
||||
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
|
||||
ORxG_SCY_6_CLK )
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
/* Bank 1 - NAND Flash
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE
|
||||
#define CONFIG_SYS_NAND_SIZE 0x8000
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_NAND 0x000036
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
|
||||
#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
|
||||
#endif
|
||||
|
||||
/* Bank 2 - 60x bus SDRAM
|
||||
*/
|
||||
#define CONFIG_SYS_PSRT 0x20
|
||||
#define CONFIG_SYS_LSRT 0x20
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_32 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2
|
||||
|
||||
|
||||
/* SDRAM initialization values
|
||||
*/
|
||||
#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
|
||||
PSDMR_BSMA_A15_A17 |\
|
||||
PSDMR_SDA10_PBI0_A10 |\
|
||||
PSDMR_RFRC_5_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_BL |\
|
||||
PSDMR_LDOTOPRE_2C |\
|
||||
PSDMR_WRC_3C |\
|
||||
PSDMR_CL_3)
|
||||
|
||||
/* Bank 3 - UART
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
|
||||
#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user