OMAP3: Add SPL support to omap3_evm
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini <trini@ti.com>
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@@ -123,6 +123,32 @@ enum {
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V_MCFG_BANKALLOCATION_RBC | \
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V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
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/* Hynix part of AM/DM37xEVM (200MHz optimized) */
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#define HYNIX_TDAL_200 6
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#define HYNIX_TDPL_200 3
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#define HYNIX_TRRD_200 2
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#define HYNIX_TRCD_200 4
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#define HYNIX_TRP_200 3
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#define HYNIX_TRAS_200 8
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#define HYNIX_TRC_200 11
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#define HYNIX_TRFC_200 18
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#define HYNIX_V_ACTIMA_200 \
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ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \
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HYNIX_TRAS_200, HYNIX_TRP_200, \
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HYNIX_TRCD_200, HYNIX_TRRD_200, \
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HYNIX_TDPL_200, HYNIX_TDAL_200)
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#define HYNIX_TWTR_200 2
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#define HYNIX_TCKE_200 1
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#define HYNIX_TXP_200 1
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#define HYNIX_XSR_200 28
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#define HYNIX_V_ACTIMB_200 \
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ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \
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HYNIX_TXP_200, HYNIX_XSR_200)
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#define HYNIX_RASWIDTH_200 0x3
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#define HYNIX_V_MCFG_200(size) MCFG((size), HYNIX_RASWIDTH_200)
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/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
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#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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