OMAP3: Add SPL support to Beagleboard
This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to 0x80100000. Cc: Dirk Behme <dirk.behme@gmail.com> Beagleboard rev C5, xM rev A: Tested-by: Tom Rini <trini@ti.com> Beagleboard xM rev C: Tested-by: Matt Ranostay <mranostay@gmail.com> Beagleboard rev B7, C2, xM rev B: Tested-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini
Albert ARIBAUD
parent
4e647e1207
commit
75c57a3570
@ -186,6 +186,32 @@ enum {
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(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
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(MICRON_BL_165))
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/* Micron part (200MHz optimized) 5 ns */
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#define MICRON_TDAL_200 6
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#define MICRON_TDPL_200 3
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#define MICRON_TRRD_200 2
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#define MICRON_TRCD_200 3
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#define MICRON_TRP_200 3
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#define MICRON_TRAS_200 8
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#define MICRON_TRC_200 11
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#define MICRON_TRFC_200 15
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#define MICRON_V_ACTIMA_200 \
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ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200, \
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MICRON_TRAS_200, MICRON_TRP_200, \
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MICRON_TRCD_200, MICRON_TRRD_200, \
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MICRON_TDPL_200, MICRON_TDAL_200)
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#define MICRON_TWTR_200 2
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#define MICRON_TCKE_200 4
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#define MICRON_TXP_200 2
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#define MICRON_XSR_200 23
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#define MICRON_V_ACTIMB_200 \
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ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200, \
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MICRON_TXP_200, MICRON_XSR_200)
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#define MICRON_RASWIDTH_200 0x3
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#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
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/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
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#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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@ -212,6 +238,9 @@ enum {
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ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
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NUMONYX_TXP_165, NUMONYX_XSR_165)
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#define NUMONYX_RASWIDTH_165 0x4
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#define NUMONYX_V_MCFG_165(size) MCFG((size), NUMONYX_RASWIDTH_165)
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/*
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* GPMC settings -
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* Definitions is as per the following format
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2004-2008
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* (C) Copyright 2004-2011
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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@ -34,9 +34,11 @@
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#include <status_led.h>
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#endif
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#include <twl4030.h>
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#include <linux/mtd/nand.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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@ -135,6 +137,69 @@ int get_board_revision(void)
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return revision;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
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u32 *mr)
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{
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int pop_mfr, pop_id;
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/*
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* We need to identify what PoP memory is on the board so that
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* we know what timings to use. If we can't identify it then
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* we know it's an xM. To map the ID values please see nand_ids.c
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*/
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identify_nand_chip(&pop_mfr, &pop_id);
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*mr = MICRON_V_MR_165;
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switch (get_board_revision()) {
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case REVISION_C4:
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if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
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/* 512MB DDR */
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*mcfg = NUMONYX_V_MCFG_165(512 << 20);
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*ctrla = NUMONYX_V_ACTIMA_165;
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*ctrlb = NUMONYX_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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break;
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} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
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/* Beagleboard Rev C5, 256MB DDR */
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*mcfg = MICRON_V_MCFG_200(256 << 20);
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*ctrla = MICRON_V_ACTIMA_200;
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*ctrlb = MICRON_V_ACTIMB_200;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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break;
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}
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case REVISION_XM_A:
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case REVISION_XM_B:
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case REVISION_XM_C:
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if (pop_mfr == 0) {
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/* 256MB DDR */
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*mcfg = MICRON_V_MCFG_200(256 << 20);
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*ctrla = MICRON_V_ACTIMA_200;
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*ctrlb = MICRON_V_ACTIMB_200;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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} else {
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/* 512MB DDR */
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*mcfg = NUMONYX_V_MCFG_165(512 << 20);
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*ctrla = NUMONYX_V_ACTIMA_165;
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*ctrlb = NUMONYX_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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break;
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default:
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/* Assume 128MB and Micron/165MHz timings to be safe */
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*mcfg = MICRON_V_MCFG_165(128 << 20);
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*ctrla = MICRON_V_ACTIMA_165;
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*ctrlb = MICRON_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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}
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#endif
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/*
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* Routine: get_expansion_id
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* Description: This function checks for expansion board by checking I2C
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@ -367,7 +432,7 @@ void set_muxconf_regs(void)
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MUX_BEAGLE();
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}
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#ifdef CONFIG_GENERIC_MMC
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0);
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@ -476,6 +541,7 @@ int ehci_hcd_init(void)
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#endif /* CONFIG_USB_EHCI */
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#ifndef CONFIG_SPL_BUILD
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/*
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* This command returns the status of the user button on beagle xM
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* Input - none
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@ -528,3 +594,4 @@ U_BOOT_CMD(
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"Return the status of the BeagleBoard USER button",
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""
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);
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#endif
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@ -1,33 +0,0 @@
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#
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# (C) Copyright 2006
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# Texas Instruments, <www.ti.com>
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#
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# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
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# see http://www.ti.com/ for more information on Texas Instruments
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# Physical Address:
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# 8000'0000 (bank0)
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# A000/0000 (bank1)
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# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
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# (mem base + reserved)
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# For use with external or internal boots.
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CONFIG_SYS_TEXT_BASE = 0x80008000
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@ -110,9 +110,6 @@
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#define STATUS_LED_BOOT STATUS_LED_BIT
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#define STATUS_LED_GREEN STATUS_LED_BIT1
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/* DDR - I use Micron DDR */
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#define CONFIG_OMAP3_MICRON_DDR 1
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/* Enable Multi Bus support for I2C */
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#define CONFIG_I2C_MULTI_BUS 1
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@ -342,7 +339,6 @@
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*-----------------------------------------------------------------------
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@ -384,4 +380,59 @@
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/* Defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (45 * 1024)
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_POWER_SUPPORT
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#define CONFIG_SPL_OMAP3_ID_NAND
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#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
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CONFIG_SYS_NAND_ECCSIZE)
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#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
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CONFIG_SYS_NAND_ECCSTEPS)
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#endif /* __CONFIG_H */
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