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arm: bcmbca: add bcm63158 SoC support under CONFIG_ARCH_BCMBCA

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BCM63158 is a Broadcom B53 based DSL Gateway SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family. Like other
Broadband SoC, this patch adds it under CONFIG_BCM63158 chip
config and CONFIG_ARCH_BCMBCA platform config.

This initial support includes a bare-bone implementation and dts with
CPU subsystem, memory and ARM PL011 uart. This SoC is supported in the
linux-next git repository so the dts and dtsi files are copied from
linux.

The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there to the console.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
This commit is contained in:
William Zhang 2022-08-22 11:19:44 -07:00 committed by Tom Rini
parent e5703df262
commit 61546e7cda
12 changed files with 240 additions and 197 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -223,6 +223,7 @@ N: bcm[9]?4912
N: bcm[9]?63138
N: bcm[9]?63146
N: bcm[9]?63148
N: bcm[9]?63158
N: bcm[9]?63178
N: bcm[9]?6756
N: bcm[9]?6813

2
arch/arm/dts/Makefile
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@ -1192,6 +1192,8 @@ dtb-$(CONFIG_BCM63146) += \
bcm963146.dtb
dtb-$(CONFIG_BCM63148) += \
bcm963148.dtb
dtb-$(CONFIG_BCM63158) += \
bcm963158.dtb
dtb-$(CONFIG_BCM63178) += \
bcm963178.dtb
dtb-$(CONFIG_BCM6756) += \

209
arch/arm/dts/bcm63158.dtsi
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@ -1,122 +1,167 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm63158";
compatible = "brcm,bcm63158", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
aliases {
spi0 = &hsspi;
};
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&l2>;
u-boot,dm-pre-reloc;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
l2: l2-cache0 {
L2_0: l2-cache0 {
compatible = "cache";
u-boot,dm-pre-reloc;
};
};
clocks {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
periph_osc: periph-osc {
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks {
u-boot,dm-pre-reloc;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0xbebc200>;
u-boot,dm-pre-reloc;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_osc>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
refclk50mhz: refclk50mhz {
compatible = "fixed-clock";
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
ubus {
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
u-boot,dm-pre-reloc;
uart0: serial@ff812000 {
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xff812000 0x0 0x1000>;
clock = <50000000>;
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
leds: led-controller@ff800800 {
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x0 0xff800800 0x0 0xe4>;
reg = <0x800 0xe4>;
status = "disabled";
};
wdt1: watchdog@ff800480 {
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff800480 0x0 0x14>;
clocks = <&refclk50mhz>;
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@ff8004c0 {
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x0 0xff8004c0 0x0 0x14>;
clocks = <&refclk50mhz>;
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
@ -124,91 +169,91 @@
wdt = <&wdt1>;
};
gpio0: gpio-controller@0xff800500 {
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff800500 0x0 0x4>,
<0x0 0xff800520 0x0 0x4>;
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@0xff800504 {
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff800504 0x0 0x4>,
<0x0 0xff800524 0x0 0x4>;
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@0xff800508 {
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff800508 0x0 0x4>,
<0x0 0xff800528 0x0 0x4>;
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@0xff80050c {
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff80050c 0x0 0x4>,
<0x0 0xff80052c 0x0 0x4>;
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@0xff800510 {
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff800510 0x0 0x4>,
<0x0 0xff800530 0x0 0x4>;
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@0xff800514 {
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff800514 0x0 0x4>,
<0x0 0xff800534 0x0 0x4>;
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@0xff800518 {
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff800518 0x0 0x4>,
<0x0 0xff800538 0x0 0x4>;
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@0xff80051c {
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x0 0xff80051c 0x0 0x4>,
<0x0 0xff80053c 0x0 0x4>;
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@ff801000 {
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0xff801000 0x0 0x600>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
@ -217,14 +262,14 @@
status = "disabled";
};
nand: nand-controller@ff801800 {
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm63158",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x0 0xff801800 0x0 0x180>,
<0x0 0xff802000 0x0 0x10>,
<0x0 0xff801c00 0x0 0x200>;
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";

121
arch/arm/dts/bcm963158.dts
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
@ -8,8 +8,8 @@
#include "bcm63158.dtsi"
/ {
model = "Broadcom bcm963158";
compatible = "broadcom,bcm963158", "brcm,bcm63158";
model = "Broadcom BCM963158 Reference Board";
compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
aliases {
serial0 = &uart0;
@ -19,121 +19,12 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&gpio6 {
status = "okay";
};
&gpio7 {
status = "okay";
};
&nand {
status = "okay";
write-protect = <0>;
#address-cells = <1>;
#size-cells = <0>;
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
brcm,nand-oob-sector-size = <16>;
};
};
&leds {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcm,serial-led-en-pol;
brcm,serial-led-data-ppol;
led@16 {
reg = <16>;
label = "red:dsl2";
};
led@17 {
reg = <17>;
label = "green:dsl1";
};
led@18 {
reg = <18>;
label = "green:fxs2";
};
led@19 {
reg = <19>;
label = "green:fxs1";
};
led@26 {
reg = <26>;
label = "green:wan1_act";
};
led@27 {
reg = <27>;
label = "green:wps";
};
led@28 {
reg = <28>;
active-low;
label = "green:aggregate_act";
};
led@29 {
reg = <29>;
label = "green:aggregate_link";
};
};
&hsspi {
status = "okay";
flash: mt25@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <25000000>;
};
};

8
arch/arm/mach-bcmbca/Kconfig
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@ -48,6 +48,13 @@ config BCM63148
select DM_SERIAL
select BCM6345_SERIAL
config BCM63158
bool "Support for Broadcom 63158 Family"
select ARM64
select SYS_ARCH_TIMER
select DM_SERIAL
select PL01X_SERIAL
config BCM63178
bool "Support for Broadcom 63178 Family"
select SYS_ARCH_TIMER
@ -89,6 +96,7 @@ source "arch/arm/mach-bcmbca/bcm4912/Kconfig"
source "arch/arm/mach-bcmbca/bcm63138/Kconfig"
source "arch/arm/mach-bcmbca/bcm63146/Kconfig"
source "arch/arm/mach-bcmbca/bcm63148/Kconfig"
source "arch/arm/mach-bcmbca/bcm63158/Kconfig"
source "arch/arm/mach-bcmbca/bcm63178/Kconfig"
source "arch/arm/mach-bcmbca/bcm6756/Kconfig"
source "arch/arm/mach-bcmbca/bcm6813/Kconfig"

1
arch/arm/mach-bcmbca/Makefile
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@ -9,6 +9,7 @@ obj-$(CONFIG_BCM4912) += bcm4912/
obj-$(CONFIG_BCM63138) += bcm63138/
obj-$(CONFIG_BCM63146) += bcm63146/
obj-$(CONFIG_BCM63148) += bcm63148/
obj-$(CONFIG_BCM63158) += bcm63158/
obj-$(CONFIG_BCM63178) += bcm63178/
obj-$(CONFIG_BCM6756) += bcm6756/
obj-$(CONFIG_BCM6813) += bcm6813/

17
arch/arm/mach-bcmbca/bcm63158/Kconfig Normal file
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@ -0,0 +1,17 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2022 Broadcom Ltd
#
if BCM63158
config TARGET_BCM963158
bool "Broadcom 63158 Reference Board"
depends on ARCH_BCMBCA
config SYS_SOC
default "bcm63158"
source "board/broadcom/bcmbca/Kconfig"
endif

5
arch/arm/mach-bcmbca/bcm63158/Makefile Normal file
View File

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2022 Broadcom Ltd
#
obj-y += mmu_table.o

32
arch/arm/mach-bcmbca/bcm63158/mmu_table.c Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <common.h>
#include <asm/armv8/mmu.h>
#include <linux/sizes.h>
static struct mm_region bcm963158_mem_map[] = {
{
.virt = 0x00000000UL,
.phys = 0x00000000UL,
.size = 1UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
{
/* SoC peripheral */
.virt = 0xff800000UL,
.phys = 0xff800000UL,
.size = 0x100000,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{
/* List terminator */
0,
}
};
struct mm_region *mem_map = bcm963158_mem_map;

7
board/broadcom/bcmbca/Kconfig
View File

@ -51,6 +51,13 @@ config SYS_CONFIG_NAME
endif
if TARGET_BCM963158
config SYS_CONFIG_NAME
default "bcm963158"
endif
if TARGET_BCM963178
config SYS_CONFIG_NAME

23
configs/bcm963158_defconfig Normal file
View File

@ -0,0 +1,23 @@
CONFIG_ARM=y
CONFIG_COUNTER_FREQUENCY=50000000
CONFIG_ARCH_BCMBCA=y
CONFIG_SYS_TEXT_BASE=0x01000000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_BCM63158=y
CONFIG_TARGET_BCM963158=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
CONFIG_IDENT_STRING=" Broadcom BCM63158"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y

11
include/configs/bcm963158.h Normal file
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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2022 Broadcom Ltd.
*/
#ifndef __BCM963158_H
#define __BCM963158_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#endif