Merge branch 'master' of git://git.denx.de/u-boot-i2c
This pull request contains bugfixes for rcar_i2c, rcar_ii2c and i2c_cdns driver. Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek is a bugfix for arm64 builds, as discussed with Marek on list.
This commit is contained in:
Tom Rini
commit
606b239a6c
@ -64,12 +64,24 @@ struct cdns_i2c_regs {
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#define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
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#define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
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#define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
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CDNS_I2C_INTERRUPT_DATA | \
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CDNS_I2C_INTERRUPT_NACK | \
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CDNS_I2C_INTERRUPT_TO | \
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CDNS_I2C_INTERRUPT_SLVRDY | \
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CDNS_I2C_INTERRUPT_RXOVF | \
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CDNS_I2C_INTERRUPT_TXOVF | \
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CDNS_I2C_INTERRUPT_RXUNF | \
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CDNS_I2C_INTERRUPT_ARBLOST)
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#define CDNS_I2C_FIFO_DEPTH 16
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#define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
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#define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
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#define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
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#define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
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#ifdef DEBUG
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static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
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{
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@ -224,11 +236,17 @@ static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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return 0;
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}
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static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
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{
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return (readl(®s->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
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}
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static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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u32 len)
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{
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u8 *cur_data = data;
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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u32 ret;
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/* Set the controller in Master transmit mode and clear FIFO */
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setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
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@ -241,29 +259,42 @@ static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Clear the interrupts in status register */
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writel(0xFF, ®s->interrupt_status);
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writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status);
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writel(addr, ®s->address);
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while (len--) {
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while (len-- && !is_arbitration_lost(regs)) {
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writel(*(cur_data++), ®s->data);
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if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
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if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
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/* Release the bus */
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clrbits_le32(®s->control,
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CDNS_I2C_CONTROL_HOLD);
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return -ETIMEDOUT;
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}
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ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_ARBLOST);
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if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
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return -EAGAIN;
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if (ret & CDNS_I2C_INTERRUPT_COMP)
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continue;
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/* Release the bus */
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clrbits_le32(®s->control,
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CDNS_I2C_CONTROL_HOLD);
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return -ETIMEDOUT;
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}
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}
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if (len && is_arbitration_lost(regs))
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return -EAGAIN;
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/* All done... release the bus */
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if (!i2c_bus->hold_flag)
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clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
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/* Wait for the address and data to be sent */
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if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
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ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_ARBLOST);
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if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
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CDNS_I2C_INTERRUPT_COMP)))
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return -ETIMEDOUT;
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if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
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return -EAGAIN;
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return 0;
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}
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@ -279,6 +310,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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struct cdns_i2c_regs *regs = i2c_bus->regs;
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int curr_recv_count;
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int updatetx, hold_quirk;
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u32 ret;
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/* Check the hardware can handle the requested bytes */
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if ((recv_count < 0))
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@ -307,7 +339,7 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
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while (recv_count) {
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while (recv_count && !is_arbitration_lost(regs)) {
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while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
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if (recv_count < CDNS_I2C_FIFO_DEPTH &&
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!i2c_bus->hold_flag) {
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@ -356,8 +388,13 @@ static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
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}
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/* Wait for the address and data to be sent */
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if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
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ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
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CDNS_I2C_INTERRUPT_ARBLOST);
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if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
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CDNS_I2C_INTERRUPT_COMP)))
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return -ETIMEDOUT;
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if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
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return -EAGAIN;
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return 0;
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}
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@ -366,8 +403,11 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
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int ret, count;
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int ret = 0;
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int count;
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bool hold_quirk;
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struct i2c_msg *message = msg;
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int num_msgs = nmsgs;
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hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
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@ -393,7 +433,8 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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}
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
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nmsgs > 0; nmsgs--, msg++) {
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD) {
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ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
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@ -402,13 +443,22 @@ static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
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msg->len);
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}
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if (ret == -EAGAIN) {
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msg = message;
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nmsgs = num_msgs;
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retry++;
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printf("%s,arbitration lost, retrying:%d\n", __func__,
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retry);
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continue;
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}
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if (ret) {
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debug("i2c_write: error sending\n");
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return -EREMOTEIO;
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}
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}
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return 0;
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return ret;
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}
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static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
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@ -18,39 +18,52 @@
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#include <asm/io.h>
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#include <wait_bit.h>
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#define RCAR_I2C_ICSCR 0x00
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#define RCAR_I2C_ICMCR 0x04
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#define RCAR_I2C_ICMCR_MDBS BIT(7)
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#define RCAR_I2C_ICMCR_FSCL BIT(6)
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#define RCAR_I2C_ICMCR_FSDA BIT(5)
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#define RCAR_I2C_ICMCR_OBPC BIT(4)
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#define RCAR_I2C_ICMCR_MIE BIT(3)
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#define RCAR_I2C_ICSCR 0x00 /* slave ctrl */
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#define RCAR_I2C_ICMCR 0x04 /* master ctrl */
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#define RCAR_I2C_ICMCR_MDBS BIT(7) /* non-fifo mode switch */
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#define RCAR_I2C_ICMCR_FSCL BIT(6) /* override SCL pin */
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#define RCAR_I2C_ICMCR_FSDA BIT(5) /* override SDA pin */
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#define RCAR_I2C_ICMCR_OBPC BIT(4) /* override pins */
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#define RCAR_I2C_ICMCR_MIE BIT(3) /* master if enable */
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#define RCAR_I2C_ICMCR_TSBE BIT(2)
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#define RCAR_I2C_ICMCR_FSB BIT(1)
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#define RCAR_I2C_ICMCR_ESG BIT(0)
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#define RCAR_I2C_ICSSR 0x08
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#define RCAR_I2C_ICMSR 0x0c
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#define RCAR_I2C_ICMCR_FSB BIT(1) /* force stop bit */
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#define RCAR_I2C_ICMCR_ESG BIT(0) /* enable start bit gen */
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#define RCAR_I2C_ICSSR 0x08 /* slave status */
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#define RCAR_I2C_ICMSR 0x0c /* master status */
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#define RCAR_I2C_ICMSR_MASK 0x7f
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#define RCAR_I2C_ICMSR_MNR BIT(6)
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#define RCAR_I2C_ICMSR_MAL BIT(5)
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#define RCAR_I2C_ICMSR_MST BIT(4)
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#define RCAR_I2C_ICMSR_MNR BIT(6) /* Nack */
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#define RCAR_I2C_ICMSR_MAL BIT(5) /* Arbitration lost */
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#define RCAR_I2C_ICMSR_MST BIT(4) /* Stop */
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#define RCAR_I2C_ICMSR_MDE BIT(3)
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#define RCAR_I2C_ICMSR_MDT BIT(2)
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#define RCAR_I2C_ICMSR_MDR BIT(1)
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#define RCAR_I2C_ICMSR_MAT BIT(0)
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#define RCAR_I2C_ICSIER 0x10
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#define RCAR_I2C_ICMIER 0x14
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#define RCAR_I2C_ICCCR 0x18
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#define RCAR_I2C_ICSIER 0x10 /* slave irq enable */
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#define RCAR_I2C_ICMIER 0x14 /* master irq enable */
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#define RCAR_I2C_ICCCR 0x18 /* clock dividers */
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#define RCAR_I2C_ICCCR_SCGD_OFF 3
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#define RCAR_I2C_ICSAR 0x1c
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#define RCAR_I2C_ICMAR 0x20
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#define RCAR_I2C_ICRXD_ICTXD 0x24
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#define RCAR_I2C_ICSAR 0x1c /* slave address */
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#define RCAR_I2C_ICMAR 0x20 /* master address */
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#define RCAR_I2C_ICRXD_ICTXD 0x24 /* data port */
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/*
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* First Bit Setup Cycle (Gen3).
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* Defines 1st bit delay between SDA and SCL.
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*/
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#define RCAR_I2C_ICFBSCR 0x38
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#define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
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enum rcar_i2c_type {
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RCAR_I2C_TYPE_GEN2,
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RCAR_I2C_TYPE_GEN3,
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};
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struct rcar_i2c_priv {
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void __iomem *base;
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struct clk clk;
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u32 intdelay;
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u32 icccr;
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enum rcar_i2c_type type;
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};
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static int rcar_i2c_finish(struct udevice *dev)
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@ -68,12 +81,13 @@ static int rcar_i2c_finish(struct udevice *dev)
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return ret;
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}
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static void rcar_i2c_recover(struct udevice *dev)
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static int rcar_i2c_recover(struct udevice *dev)
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{
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
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u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
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int i;
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u32 mstat;
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/* Send 9 SCL pulses */
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for (i = 0; i < 9; i++) {
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@ -93,6 +107,9 @@ static void rcar_i2c_recover(struct udevice *dev)
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udelay(5);
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writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
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udelay(5);
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mstat = readl(priv->base + RCAR_I2C_ICMSR);
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return mstat & RCAR_I2C_ICMCR_FSDA ? -EBUSY : 0;
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}
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static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
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@ -100,7 +117,6 @@ static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
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struct rcar_i2c_priv *priv = dev_get_priv(dev);
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u32 mask = RCAR_I2C_ICMSR_MAT |
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(read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
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u32 val;
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int ret;
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writel(0, priv->base + RCAR_I2C_ICMIER);
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@ -108,21 +124,22 @@ static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
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writel(0, priv->base + RCAR_I2C_ICMSR);
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writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
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/* Wait for the bus */
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
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RCAR_I2C_ICMCR_FSDA, false, 2, true);
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if (ret) {
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rcar_i2c_recover(dev);
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val = readl(priv->base + RCAR_I2C_ICMSR);
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if (val & RCAR_I2C_ICMCR_FSDA) {
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if (rcar_i2c_recover(dev)) {
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dev_err(dev, "Bus busy, aborting\n");
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return ret;
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}
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}
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writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
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writel(0, priv->base + RCAR_I2C_ICMSR);
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/* Reset */
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writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
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priv->base + RCAR_I2C_ICMCR);
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/* Clear Status */
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writel(0, priv->base + RCAR_I2C_ICMSR);
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
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true, 100, true);
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@ -142,16 +159,12 @@ static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
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u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
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int i, ret = -EREMOTEIO;
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ret = rcar_i2c_set_addr(dev, msg->addr, 1);
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if (ret)
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return ret;
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for (i = 0; i < msg->len; i++) {
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if (msg->len - 1 == i)
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icmcr |= RCAR_I2C_ICMCR_FSB;
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writel(icmcr, priv->base + RCAR_I2C_ICMCR);
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writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
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writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
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RCAR_I2C_ICMSR_MDR, true, 100, true);
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@ -161,7 +174,7 @@ static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
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msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
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}
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writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
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writel((u32)~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
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return rcar_i2c_finish(dev);
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}
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@ -172,14 +185,10 @@ static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
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u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
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int i, ret = -EREMOTEIO;
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ret = rcar_i2c_set_addr(dev, msg->addr, 0);
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if (ret)
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return ret;
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for (i = 0; i < msg->len; i++) {
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writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
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writel(icmcr, priv->base + RCAR_I2C_ICMCR);
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writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
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writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
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ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
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RCAR_I2C_ICMSR_MDE, true, 100, true);
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@ -187,7 +196,7 @@ static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
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return ret;
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}
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writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
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writel((u32)~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
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icmcr |= RCAR_I2C_ICMCR_FSB;
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writel(icmcr, priv->base + RCAR_I2C_ICMCR);
|
||||
|
||||
@ -199,16 +208,20 @@ static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
|
||||
int ret;
|
||||
|
||||
for (; nmsgs > 0; nmsgs--, msg++) {
|
||||
ret = rcar_i2c_set_addr(dev, msg->addr, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (msg->flags & I2C_M_RD)
|
||||
ret = rcar_i2c_read_common(dev, msg);
|
||||
else
|
||||
ret = rcar_i2c_write_common(dev, msg);
|
||||
|
||||
if (ret)
|
||||
return -EREMOTEIO;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
|
||||
@ -293,6 +306,11 @@ scgd_find:
|
||||
priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
|
||||
writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
|
||||
|
||||
if (priv->type == RCAR_I2C_TYPE_GEN3) {
|
||||
/* Set SCL/SDA delay */
|
||||
writel(RCAR_I2C_ICFBSCR_TCYC17, priv->base + RCAR_I2C_ICFBSCR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -304,6 +322,7 @@ static int rcar_i2c_probe(struct udevice *dev)
|
||||
priv->base = dev_read_addr_ptr(dev);
|
||||
priv->intdelay = dev_read_u32_default(dev,
|
||||
"i2c-scl-internal-delay-ns", 5);
|
||||
priv->type = dev_get_driver_data(dev);
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||
if (ret)
|
||||
@ -339,7 +358,8 @@ static const struct dm_i2c_ops rcar_i2c_ops = {
|
||||
};
|
||||
|
||||
static const struct udevice_id rcar_i2c_ids[] = {
|
||||
{ .compatible = "renesas,rcar-gen2-i2c" },
|
||||
{ .compatible = "renesas,rcar-gen2-i2c", .data = RCAR_I2C_TYPE_GEN2 },
|
||||
{ .compatible = "renesas,rcar-gen3-i2c", .data = RCAR_I2C_TYPE_GEN3 },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
@ -58,12 +58,14 @@ static void sh_irq_dte(struct udevice *dev)
|
||||
static int sh_irq_dte_with_tack(struct udevice *dev)
|
||||
{
|
||||
struct rcar_iic_priv *priv = dev_get_priv(dev);
|
||||
u8 icsr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < IRQ_WAIT; i++) {
|
||||
if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR))
|
||||
icsr = readb(priv->base + RCAR_IIC_ICSR);
|
||||
if (RCAR_IC_DTE & icsr)
|
||||
break;
|
||||
if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR))
|
||||
if (RCAR_IC_TACK & icsr)
|
||||
return -ETIMEDOUT;
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user