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Merge branch 'master' of git://git.denx.de/u-boot-spi

Browse Source 
- dw spi include file fix
- Allwinner A31 spi, been in ML in many releases.
This commit is contained in:
Tom Rini 2019-03-06 20:25:09 -05:00
commit f18b7b2798
15 changed files with 413 additions and 137 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/clk/sunxi/clk_a10.c
View File

@ -22,6 +22,10 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
[CLK_AHB_SPI3] = GATE(0x060, BIT(23)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
@ -32,9 +36,15 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_APB1_UART6] = GATE(0x06c, BIT(22)),
[CLK_APB1_UART7] = GATE(0x06c, BIT(23)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
[CLK_USB_OHCI0] = GATE(0x0cc, BIT(6)),
[CLK_USB_OHCI1] = GATE(0x0cc, BIT(7)),
[CLK_USB_PHY] = GATE(0x0cc, BIT(8)),
[CLK_SPI3] = GATE(0x0d4, BIT(31)),
};
static struct ccu_reset a10_resets[] = {

7
drivers/clk/sunxi/clk_a10s.c
View File

@ -19,12 +19,19 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
[CLK_APB1_UART3] = GATE(0x06c, BIT(19)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
[CLK_USB_OHCI] = GATE(0x0cc, BIT(6)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),

7
drivers/clk/sunxi/clk_a23.c
View File

@ -16,6 +16,8 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
@ -26,6 +28,9 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
[CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
@ -41,6 +46,8 @@ static struct ccu_reset a23_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),

13
drivers/clk/sunxi/clk_a31.c
View File

@ -17,6 +17,10 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
[CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
[CLK_AHB1_SPI3] = GATE(0x060, BIT(23)),
[CLK_AHB1_OTG] = GATE(0x060, BIT(24)),
[CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)),
[CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)),
@ -31,6 +35,11 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_APB2_UART4] = GATE(0x06c, BIT(20)),
[CLK_APB2_UART5] = GATE(0x06c, BIT(21)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
[CLK_SPI3] = GATE(0x0ac, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
[CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
@ -48,6 +57,10 @@ static struct ccu_reset a31_resets[] = {
[RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
[RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
[RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
[RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
[RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
[RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)),
[RST_AHB1_SPI3] = RESET(0x2c0, BIT(23)),
[RST_AHB1_OTG] = RESET(0x2c0, BIT(24)),
[RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)),
[RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)),

7
drivers/clk/sunxi/clk_a64.c
View File

@ -16,6 +16,8 @@ static const struct ccu_clk_gate a64_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
[CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
[CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
@ -28,6 +30,9 @@ static const struct ccu_clk_gate a64_gates[] = {
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
[CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
@ -44,6 +49,8 @@ static const struct ccu_reset a64_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
[RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),

13
drivers/clk/sunxi/clk_a80.c
View File

@ -13,7 +13,16 @@
#include <dt-bindings/reset/sun9i-a80-ccu.h>
static const struct ccu_clk_gate a80_gates[] = {
[CLK_SPI0] = GATE(0x430, BIT(31)),
[CLK_SPI1] = GATE(0x434, BIT(31)),
[CLK_SPI2] = GATE(0x438, BIT(31)),
[CLK_SPI3] = GATE(0x43c, BIT(31)),
[CLK_BUS_MMC] = GATE(0x580, BIT(8)),
[CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
@ -25,6 +34,10 @@ static const struct ccu_clk_gate a80_gates[] = {
static const struct ccu_reset a80_resets[] = {
[RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
[RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),

7
drivers/clk/sunxi/clk_a83t.c
View File

@ -16,6 +16,8 @@ static struct ccu_clk_gate a83t_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
[CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
@ -27,6 +29,9 @@ static struct ccu_clk_gate a83t_gates[] = {
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
[CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
@ -42,6 +47,8 @@ static struct ccu_reset a83t_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),

7
drivers/clk/sunxi/clk_h3.c
View File

@ -16,6 +16,8 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
[CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
[CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
@ -31,6 +33,9 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
[CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
@ -50,6 +55,8 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
[RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),

9
drivers/clk/sunxi/clk_h6.c
View File

@ -20,6 +20,12 @@ static struct ccu_clk_gate h6_gates[] = {
[CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
[CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
};
static struct ccu_reset h6_resets[] = {
@ -30,6 +36,9 @@ static struct ccu_reset h6_resets[] = {
[RST_BUS_UART1] = RESET(0x90c, BIT(17)),
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
};
static const struct ccu_desc h6_ccu_desc = {

13
drivers/clk/sunxi/clk_r40.c
View File

@ -17,6 +17,10 @@ static struct ccu_clk_gate r40_gates[] = {
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
[CLK_BUS_OTG] = GATE(0x060, BIT(25)),
[CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
@ -34,6 +38,11 @@ static struct ccu_clk_gate r40_gates[] = {
[CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
[CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
[CLK_SPI2] = GATE(0x0a8, BIT(31)),
[CLK_SPI3] = GATE(0x0ac, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
[CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
@ -51,6 +60,10 @@ static struct ccu_reset r40_resets[] = {
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x2c0, BIT(23)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(25)),
[RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),

4
drivers/clk/sunxi/clk_v3s.c
View File

@ -16,12 +16,15 @@ static struct ccu_clk_gate v3s_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
};
@ -31,6 +34,7 @@ static struct ccu_reset v3s_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),

12
drivers/spi/Kconfig
View File

@ -213,6 +213,13 @@ config SANDBOX_SPI
};
};
config SPI_SUNXI
bool "Allwinner SoC SPI controllers"
help
Enable the Allwinner SoC SPi controller driver.
Same controller driver can reuse in all Allwinner SoC variants.
config STM32_QSPI
bool "STM32F7 QSPI driver"
depends on STM32F7
@ -222,11 +229,6 @@ config STM32_QSPI
used to access the SPI NOR flash chips on platforms embedding
this ST IP core.
config SUN4I_SPI
bool "Allwinner A10 SoCs SPI controller"
help
SPI driver for Allwinner sun4i, sun5i and sun7i SoCs
config TEGRA114_SPI
bool "nVidia Tegra114 SPI driver"
help

2
drivers/spi/Makefile
View File

@ -48,10 +48,10 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o
obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o

2
drivers/spi/designware_spi.c
View File

@ -9,8 +9,8 @@
* Copyright (c) 2009, Intel Corporation.
*/
#include <asm-generic/gpio.h>
#include <common.h>
#include <asm-generic/gpio.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>

437
drivers/spi/sun4i_spi.c → drivers/spi/spi-sunxi.c
View File

@ -19,101 +19,117 @@
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <spi.h>
#include <errno.h>
#include <fdt_support.h>
#include <reset.h>
#include <wait_bit.h>
#include <asm/bitops.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <linux/iopoll.h>
#define SUN4I_FIFO_DEPTH 64
DECLARE_GLOBAL_DATA_PTR;
#define SUN4I_RXDATA_REG 0x00
/* sun4i spi registers */
#define SUN4I_RXDATA_REG 0x00
#define SUN4I_TXDATA_REG 0x04
#define SUN4I_CTL_REG 0x08
#define SUN4I_CLK_CTL_REG 0x1c
#define SUN4I_BURST_CNT_REG 0x20
#define SUN4I_XMIT_CNT_REG 0x24
#define SUN4I_FIFO_STA_REG 0x28
#define SUN4I_TXDATA_REG 0x04
/* sun6i spi registers */
#define SUN6I_GBL_CTL_REG 0x04
#define SUN6I_TFR_CTL_REG 0x08
#define SUN6I_FIFO_CTL_REG 0x18
#define SUN6I_FIFO_STA_REG 0x1c
#define SUN6I_CLK_CTL_REG 0x24
#define SUN6I_BURST_CNT_REG 0x30
#define SUN6I_XMIT_CNT_REG 0x34
#define SUN6I_BURST_CTL_REG 0x38
#define SUN6I_TXDATA_REG 0x200
#define SUN6I_RXDATA_REG 0x300
#define SUN4I_CTL_REG 0x08
/* sun spi bits */
#define SUN4I_CTL_ENABLE BIT(0)
#define SUN4I_CTL_MASTER BIT(1)
#define SUN4I_CTL_CPHA BIT(2)
#define SUN4I_CTL_CPOL BIT(3)
#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
#define SUN4I_CTL_LMTF BIT(6)
#define SUN4I_CTL_TF_RST BIT(8)
#define SUN4I_CTL_RF_RST BIT(9)
#define SUN4I_CTL_XCH_MASK 0x0400
#define SUN4I_CTL_XCH BIT(10)
#define SUN4I_CTL_CS_MASK 0x3000
#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
#define SUN4I_CTL_DHB BIT(15)
#define SUN4I_CTL_CS_MANUAL BIT(16)
#define SUN4I_CTL_CS_LEVEL BIT(17)
#define SUN4I_CTL_TP BIT(18)
#define SUN4I_INT_CTL_REG 0x0c
#define SUN4I_INT_CTL_RF_F34 BIT(4)
#define SUN4I_INT_CTL_TF_E34 BIT(12)
#define SUN4I_INT_CTL_TC BIT(16)
#define SUN4I_INT_STA_REG 0x10
#define SUN4I_DMA_CTL_REG 0x14
#define SUN4I_WAIT_REG 0x18
#define SUN4I_CLK_CTL_REG 0x1c
#define SUN4I_CLK_CTL_CDR2_MASK 0xff
#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
#define SUN4I_CLK_CTL_CDR1_MASK 0xf
#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
#define SUN4I_CLK_CTL_DRS BIT(12)
#define SUN4I_MAX_XFER_SIZE 0xffffff
#define SUN4I_BURST_CNT_REG 0x20
#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
#define SUN4I_XMIT_CNT_REG 0x24
#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
#define SUN4I_FIFO_STA_REG 0x28
#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
#define SUN4I_FIFO_STA_RF_CNT_BITS 0
#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
#define SUN4I_FIFO_STA_TF_CNT_BITS 16
#define SUN4I_SPI_MAX_RATE 24000000
#define SUN4I_SPI_MIN_RATE 3000
#define SUN4I_SPI_DEFAULT_RATE 1000000
#define SUN4I_SPI_TIMEOUT_US 1000000
#define SUN4I_SPI_MAX_RATE 24000000
#define SUN4I_SPI_MIN_RATE 3000
#define SUN4I_SPI_DEFAULT_RATE 1000000
#define SUN4I_SPI_TIMEOUT_US 1000000
/* sun4i spi register set */
struct sun4i_spi_regs {
u32 rxdata;
u32 txdata;
u32 ctl;
u32 intctl;
u32 st;
u32 dmactl;
u32 wait;
u32 cctl;
u32 bc;
u32 tc;
u32 fifo_sta;
#define SPI_REG(priv, reg) ((priv)->base + \
(priv)->variant->regs[reg])
#define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
#define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
SPI_BIT(priv, SPI_TCR_CS_MASK))
/* sun spi register set */
enum sun4i_spi_regs {
SPI_GCR,
SPI_TCR,
SPI_FCR,
SPI_FSR,
SPI_CCR,
SPI_BC,
SPI_TC,
SPI_BCTL,
SPI_TXD,
SPI_RXD,
};
/* sun spi register bits */
enum sun4i_spi_bits {
SPI_GCR_TP,
SPI_GCR_SRST,
SPI_TCR_CPHA,
SPI_TCR_CPOL,
SPI_TCR_CS_ACTIVE_LOW,
SPI_TCR_CS_SEL,
SPI_TCR_CS_MASK,
SPI_TCR_XCH,
SPI_TCR_CS_MANUAL,
SPI_TCR_CS_LEVEL,
SPI_FCR_TF_RST,
SPI_FCR_RF_RST,
SPI_FSR_RF_CNT_MASK,
};
struct sun4i_spi_variant {
const unsigned long *regs;
const u32 *bits;
u32 fifo_depth;
bool has_soft_reset;
bool has_burst_ctl;
};
struct sun4i_spi_platdata {
u32 base_addr;
struct sun4i_spi_variant *variant;
u32 base;
u32 max_hz;
};
struct sun4i_spi_priv {
struct sun4i_spi_regs *regs;
struct sun4i_spi_variant *variant;
struct clk clk_ahb, clk_mod;
struct reset_ctl reset;
u32 base;
u32 freq;
u32 mode;
@ -121,14 +137,12 @@ struct sun4i_spi_priv {
u8 *rx_buf;
};
DECLARE_GLOBAL_DATA_PTR;
static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
{
u8 byte;
while (len--) {
byte = readb(&priv->regs->rxdata);
byte = readb(SPI_REG(priv, SPI_RXD));
if (priv->rx_buf)
*priv->rx_buf++ = byte;
}
@ -140,7 +154,7 @@ static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
while (len--) {
byte = priv->tx_buf ? *priv->tx_buf++ : 0;
writeb(byte, &priv->regs->txdata);
writeb(byte, SPI_REG(priv, SPI_TXD));
}
}
@ -149,17 +163,17 @@ static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
struct sun4i_spi_priv *priv = dev_get_priv(bus);
u32 reg;
reg = readl(&priv->regs->ctl);
reg = readl(SPI_REG(priv, SPI_TCR));
reg &= ~SUN4I_CTL_CS_MASK;
reg |= SUN4I_CTL_CS(cs);
reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
reg |= SPI_CS(priv, cs);
if (enable)
reg &= ~SUN4I_CTL_CS_LEVEL;
reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
else
reg |= SUN4I_CTL_CS_LEVEL;
reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
writel(reg, &priv->regs->ctl);
writel(reg, SPI_REG(priv, SPI_TCR));
}
static int sun4i_spi_parse_pins(struct udevice *dev)
@ -231,7 +245,10 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
if (pin < 0)
break;
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
if (IS_ENABLED(CONFIG_MACH_SUN50I))
sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
else
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
sunxi_gpio_set_drv(pin, drive);
sunxi_gpio_set_pull(pin, pull);
}
@ -239,63 +256,77 @@ static int sun4i_spi_parse_pins(struct udevice *dev)
return 0;
}
static inline void sun4i_spi_enable_clock(void)
static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
struct sun4i_spi_priv *priv = dev_get_priv(dev);
int ret;
setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
writel((1 << 31), &ccm->spi0_clk_cfg);
}
if (!enable) {
clk_disable(&priv->clk_ahb);
clk_disable(&priv->clk_mod);
if (reset_valid(&priv->reset))
reset_assert(&priv->reset);
return 0;
}
static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
int node = dev_of_offset(bus);
ret = clk_enable(&priv->clk_ahb);
if (ret) {
dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
return ret;
}
plat->base_addr = devfdt_get_addr(bus);
plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
"spi-max-frequency",
SUN4I_SPI_DEFAULT_RATE);
ret = clk_enable(&priv->clk_mod);
if (ret) {
dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
goto err_ahb;
}
if (plat->max_hz > SUN4I_SPI_MAX_RATE)
plat->max_hz = SUN4I_SPI_MAX_RATE;
if (reset_valid(&priv->reset)) {
ret = reset_deassert(&priv->reset);
if (ret) {
dev_err(dev, "failed to deassert reset\n");
goto err_mod;
}
}
return 0;
}
static int sun4i_spi_probe(struct udevice *bus)
{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
struct sun4i_spi_priv *priv = dev_get_priv(bus);
sun4i_spi_enable_clock();
sun4i_spi_parse_pins(bus);
priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr;
priv->freq = plat->max_hz;
return 0;
err_mod:
clk_disable(&priv->clk_mod);
err_ahb:
clk_disable(&priv->clk_ahb);
return ret;
}
static int sun4i_spi_claim_bus(struct udevice *dev)
{
struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
int ret;
ret = sun4i_spi_set_clock(dev->parent, true);
if (ret)
return ret;
setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
if (priv->variant->has_soft_reset)
setbits_le32(SPI_REG(priv, SPI_GCR),
SPI_BIT(priv, SPI_GCR_SRST));
setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP |
SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW,
&priv->regs->ctl);
return 0;
}
static int sun4i_spi_release_bus(struct udevice *dev)
{
struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
u32 reg;
reg = readl(&priv->regs->ctl);
reg &= ~SUN4I_CTL_ENABLE;
writel(reg, &priv->regs->ctl);
clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
sun4i_spi_set_clock(dev->parent, false);
return 0;
}
@ -308,7 +339,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
u32 len = bitlen / 8;
u32 reg;
u32 rx_fifocnt;
u8 nbytes;
int ret;
@ -323,30 +354,37 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
if (flags & SPI_XFER_BEGIN)
sun4i_spi_set_cs(bus, slave_plat->cs, true);
reg = readl(&priv->regs->ctl);
/* Reset FIFOs */
writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl);
setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
SPI_BIT(priv, SPI_FCR_TF_RST));
while (len) {
/* Setup the transfer now... */
nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1));
nbytes = min(len, (priv->variant->fifo_depth - 1));
/* Setup the counters */
writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc);
writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc);
writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
if (priv->variant->has_burst_ctl)
writel(SUN4I_BURST_CNT(nbytes),
SPI_REG(priv, SPI_BCTL));
/* Fill the TX FIFO */
sun4i_spi_fill_fifo(priv, nbytes);
/* Start the transfer */
reg = readl(&priv->regs->ctl);
writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl);
setbits_le32(SPI_REG(priv, SPI_TCR),
SPI_BIT(priv, SPI_TCR_XCH));
/* Wait transfer to complete */
ret = wait_for_bit_le32(&priv->regs->ctl, SUN4I_CTL_XCH_MASK,
false, SUN4I_SPI_TIMEOUT_US, false);
if (ret) {
/* Wait till RX FIFO to be empty */
ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
rx_fifocnt,
(((rx_fifocnt &
SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >>
SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
SUN4I_SPI_TIMEOUT_US);
if (ret < 0) {
printf("ERROR: sun4i_spi: Timeout transferring data\n");
sun4i_spi_set_cs(bus, slave_plat->cs, false);
return ret;
@ -392,7 +430,7 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
*/
div = SUN4I_SPI_MAX_RATE / (2 * speed);
reg = readl(&priv->regs->cctl);
reg = readl(SPI_REG(priv, SPI_CCR));
if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
if (div > 0)
@ -407,7 +445,7 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
}
priv->freq = speed;
writel(reg, &priv->regs->cctl);
writel(reg, SPI_REG(priv, SPI_CCR));
return 0;
}
@ -417,17 +455,17 @@ static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
struct sun4i_spi_priv *priv = dev_get_priv(dev);
u32 reg;
reg = readl(&priv->regs->ctl);
reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA);
reg = readl(SPI_REG(priv, SPI_TCR));
reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
if (mode & SPI_CPOL)
reg |= SUN4I_CTL_CPOL;
reg |= SPI_BIT(priv, SPI_TCR_CPOL);
if (mode & SPI_CPHA)
reg |= SUN4I_CTL_CPHA;
reg |= SPI_BIT(priv, SPI_TCR_CPHA);
priv->mode = mode;
writel(reg, &priv->regs->ctl);
writel(reg, SPI_REG(priv, SPI_TCR));
return 0;
}
@ -440,9 +478,148 @@ static const struct dm_spi_ops sun4i_spi_ops = {
.set_mode = sun4i_spi_set_mode,
};
static int sun4i_spi_probe(struct udevice *bus)
{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
struct sun4i_spi_priv *priv = dev_get_priv(bus);
int ret;
ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
if (ret) {
dev_err(dev, "failed to get ahb clock\n");
return ret;
}
ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
if (ret) {
dev_err(dev, "failed to get mod clock\n");
return ret;
}
ret = reset_get_by_index(bus, 0, &priv->reset);
if (ret && ret != -ENOENT) {
dev_err(dev, "failed to get reset\n");
return ret;
}
sun4i_spi_parse_pins(bus);
priv->variant = plat->variant;
priv->base = plat->base;
priv->freq = plat->max_hz;
return 0;
}
static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
{
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
int node = dev_of_offset(bus);
plat->base = devfdt_get_addr(bus);
plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
"spi-max-frequency",
SUN4I_SPI_DEFAULT_RATE);
if (plat->max_hz > SUN4I_SPI_MAX_RATE)
plat->max_hz = SUN4I_SPI_MAX_RATE;
return 0;
}
static const unsigned long sun4i_spi_regs[] = {
[SPI_GCR] = SUN4I_CTL_REG,
[SPI_TCR] = SUN4I_CTL_REG,
[SPI_FCR] = SUN4I_CTL_REG,
[SPI_FSR] = SUN4I_FIFO_STA_REG,
[SPI_CCR] = SUN4I_CLK_CTL_REG,
[SPI_BC] = SUN4I_BURST_CNT_REG,
[SPI_TC] = SUN4I_XMIT_CNT_REG,
[SPI_TXD] = SUN4I_TXDATA_REG,
[SPI_RXD] = SUN4I_RXDATA_REG,
};
static const u32 sun4i_spi_bits[] = {
[SPI_GCR_TP] = BIT(18),
[SPI_TCR_CPHA] = BIT(2),
[SPI_TCR_CPOL] = BIT(3),
[SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
[SPI_TCR_XCH] = BIT(10),
[SPI_TCR_CS_SEL] = 12,
[SPI_TCR_CS_MASK] = 0x3000,
[SPI_TCR_CS_MANUAL] = BIT(16),
[SPI_TCR_CS_LEVEL] = BIT(17),
[SPI_FCR_TF_RST] = BIT(8),
[SPI_FCR_RF_RST] = BIT(9),
[SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0),
};
static const unsigned long sun6i_spi_regs[] = {
[SPI_GCR] = SUN6I_GBL_CTL_REG,
[SPI_TCR] = SUN6I_TFR_CTL_REG,
[SPI_FCR] = SUN6I_FIFO_CTL_REG,
[SPI_FSR] = SUN6I_FIFO_STA_REG,
[SPI_CCR] = SUN6I_CLK_CTL_REG,
[SPI_BC] = SUN6I_BURST_CNT_REG,
[SPI_TC] = SUN6I_XMIT_CNT_REG,
[SPI_BCTL] = SUN6I_BURST_CTL_REG,
[SPI_TXD] = SUN6I_TXDATA_REG,
[SPI_RXD] = SUN6I_RXDATA_REG,
};
static const u32 sun6i_spi_bits[] = {
[SPI_GCR_TP] = BIT(7),
[SPI_GCR_SRST] = BIT(31),
[SPI_TCR_CPHA] = BIT(0),
[SPI_TCR_CPOL] = BIT(1),
[SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
[SPI_TCR_CS_SEL] = 4,
[SPI_TCR_CS_MASK] = 0x30,
[SPI_TCR_CS_MANUAL] = BIT(6),
[SPI_TCR_CS_LEVEL] = BIT(7),
[SPI_TCR_XCH] = BIT(31),
[SPI_FCR_RF_RST] = BIT(15),
[SPI_FCR_TF_RST] = BIT(31),
[SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0),
};
static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
.regs = sun4i_spi_regs,
.bits = sun4i_spi_bits,
.fifo_depth = 64,
};
static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
.regs = sun6i_spi_regs,
.bits = sun6i_spi_bits,
.fifo_depth = 128,
.has_soft_reset = true,
.has_burst_ctl = true,
};
static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
.regs = sun6i_spi_regs,
.bits = sun6i_spi_bits,
.fifo_depth = 64,
.has_soft_reset = true,
.has_burst_ctl = true,
};
static const struct udevice_id sun4i_spi_ids[] = {
{ .compatible = "allwinner,sun4i-a10-spi" },
{ }
{
.compatible = "allwinner,sun4i-a10-spi",
.data = (ulong)&sun4i_a10_spi_variant,
},
{
.compatible = "allwinner,sun6i-a31-spi",
.data = (ulong)&sun6i_a31_spi_variant,
},
{
.compatible = "allwinner,sun8i-h3-spi",
.data = (ulong)&sun8i_h3_spi_variant,
},
{ /* sentinel */ }
};
U_BOOT_DRIVER(sun4i_spi) = {