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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

Browse Source 
- Armada 38x DDR3 fixes, enhancements (Chris)
- Armada 38x UTMI PHY SerDes fix (Chris)
- Helios4 update - sync with clearfog (Dennis)
- LaCie Kirkwood board rework - enable DM (Simon)
- net/mvpp2 memory init fix (Sven)
This commit is contained in:
Tom Rini 2020-07-09 08:21:26 -04:00
commit 5fb70639cc
26 changed files with 298 additions and 139 deletions
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15
arch/arm/dts/armada-388-helios4-u-boot.dtsi
View File

@ -14,6 +14,9 @@
&spi1 {
u-boot,dm-spl;
spi-flash@0 {
u-boot,dm-spl;
};
};
&w25q32 {
@ -21,6 +24,18 @@
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
&ahci0 {
u-boot,dm-spl;
};
&ahci1 {
u-boot,dm-spl;
};
&sdhci {
u-boot,dm-spl;
};

16
arch/arm/dts/armada-388-helios4.dts
View File

@ -140,11 +140,6 @@
soc {
internal-regs {
i2c@11000 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-Board Revision bit 0 #
@ -187,8 +182,7 @@
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
input;
line-name =
"usb-overcurrent-status";
line-name = "usb-overcurrent-status";
};
};
@ -248,7 +242,7 @@
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
pinctrl-0 = <&microsom_sdhci_pins
pinctrl-0 = <&helios_sdhci_pins
&helios_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
@ -286,6 +280,12 @@
marvell,pins = "mpp20";
marvell,function = "gpio";
};
helios_sdhci_pins: helios-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
helios_led_pins: helios-led-pins {
marvell,pins = "mpp24", "mpp25",
"mpp49", "mpp50",

7
arch/arm/dts/kirkwood-d2net-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
spi0 = &spi0;
};
};

7
arch/arm/dts/kirkwood-is2-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
spi0 = &spi0;
};
};

7
arch/arm/dts/kirkwood-net2big-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
spi0 = &spi0;
};
};

7
arch/arm/dts/kirkwood-ns2-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
spi0 = &spi0;
};
};

7
arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
spi0 = &spi0;
};
};

7
arch/arm/dts/kirkwood-ns2max-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
spi0 = &spi0;
};
};

7
arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi Normal file
View File

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/ {
aliases {
spi0 = &spi0;
};
};

27
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
View File

@ -533,7 +533,7 @@ struct op_params pex_and_usb3_tx_config_params3[] = {
struct op_params pex_by4_config_params[] = {
/* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
{GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0},
/* Lane Alignement enable */
/* Lane Alignment enable */
{LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0},
/* Max PLL phy config */
{CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000},
@ -672,12 +672,29 @@ struct op_params usb2_power_up_params[] = {
{0xc200c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
/* Phy0 register 3 - TX Channel control 0 */
{0xc400c, 0x0 /*NA*/, 0x1000000, {0x1000000}, 0, 0},
/* check PLLCAL_DONE is set and IMPCAL_DONE is set */
/* Decrease the amplitude of the low speed eye to meet the spec */
{0xc000c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
{0xc200c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
{0xc400c, 0x0 /*NA*/, 0xf000, {0x1000}, 0, 0},
/* Change the High speed impedance threshold */
{0xc0008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
{0xc2008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
{0xc4008, 0x0 /*NA*/, 0x700, {0x600}, 0, 0},
/* Change the squelch level of the receiver to meet the receiver electrical measurements (squelch and receiver sensitivity tests) */
{0xc0014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
{0xc2014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
{0xc4014, 0x0 /*NA*/, 0xf, {0x8}, 0, 0},
/* Check PLLCAL_DONE is set and IMPCAL_DONE is set */
{0xc0008, 0x0 /*NA*/, 0x80800000, {0x80800000}, 1, 1000},
/* check REG_SQCAL_DONE is set */
/* Check REG_SQCAL_DONE is set */
{0xc0018, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
/* check PLL_READY is set */
{0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000}
/* Check PLL_READY is set */
{0xc0000, 0x0 /*NA*/, 0x80000000, {0x80000000}, 1, 1000},
/* Start calibrate of high seed impedance */
{0xc0008, 0x0 /*NA*/, 0x2000, {0x2000}, 0, 0},
{0x0, 0x0 /*NA*/, 0x0, {0x0}, 10, 0},
/* De-assert the calibration signal */
{0xc0008, 0x0 /*NA*/, 0x2000, {0x0}, 0, 0},
};
/*

6
board/LaCie/net2big_v2/MAINTAINERS
View File

@ -1,6 +1,12 @@
NET2BIG_V2 BOARD
M: Simon Guinot <simon.guinot@sequanux.org>
S: Maintained
F: arch/arm/dts/kirkwood-d2net.dts
F: arch/arm/dts/kirkwood-d2net-u-boot.dtsi
F: arch/arm/dts/kirkwood-d2net.dtsi
F: arch/arm/dts/kirkwood-net2big.dts
F: arch/arm/dts/kirkwood-net2big-u-boot.dtsi
F: arch/arm/dts/kirkwood-netxbig.dtsi
F: board/LaCie/net2big_v2/
F: include/configs/lacie_kw.h
F: configs/d2net_v2_defconfig

2
board/LaCie/net2big_v2/net2big_v2.c
View File

@ -239,7 +239,7 @@ int misc_init_r(void)
/* Configure and initialize PHY */
void reset_phy(void)
{
mv_phy_88e1116_init("egiga0", 8);
mv_phy_88e1116_init("ethernet-controller@72000", 8);
}
#endif

21
board/LaCie/netspace_v2/MAINTAINERS
View File

@ -1,14 +1,21 @@
NETSPACE_V2 BOARD
NETSPACE_V2 BOARDS
M: Simon Guinot <simon.guinot@sequanux.org>
S: Maintained
F: arch/arm/dts/kirkwood-is2.dts
F: arch/arm/dts/kirkwood-is2-u-boot.dtsi
F: arch/arm/dts/kirkwood-ns2-common.dtsi
F: arch/arm/dts/kirkwood-ns2.dts
F: arch/arm/dts/kirkwood-ns2lite.dts
F: arch/arm/dts/kirkwood-ns2lite-u-boot.dtsi
F: arch/arm/dts/kirkwood-ns2max.dts
F: arch/arm/dts/kirkwood-ns2max-u-boot.dtsi
F: arch/arm/dts/kirkwood-ns2mini.dts
F: arch/arm/dts/kirkwood-ns2mini-u-boot.dtsi
F: arch/arm/dts/kirkwood-ns2-u-boot.dtsi
F: board/LaCie/netspace_v2/
F: include/configs/lacie_kw.h
F: configs/inetspace_v2_defconfig
F: configs/netspace_max_v2_defconfig
F: configs/netspace_v2_defconfig
NETSPACE_LITE_V2 BOARD
#M: -
S: Maintained
F: configs/netspace_lite_v2_defconfig
F: configs/netspace_max_v2_defconfig
F: configs/netspace_mini_v2_defconfig
F: configs/netspace_v2_defconfig

4
board/LaCie/netspace_v2/netspace_v2.c
View File

@ -100,9 +100,9 @@ int misc_init_r(void)
void reset_phy(void)
{
#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
mv_phy_88e1318_init("egiga0", 0);
mv_phy_88e1318_init("ethernet-controller@72000", 0);
#else
mv_phy_88e1116_init("egiga0", 8);
mv_phy_88e1116_init("ethernet-controller@72000", 8);
#endif
}
#endif

13
configs/d2net_v2_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" D2 v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="d2v2> "
CONFIG_CMD_EEPROM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_MVSATA_IDE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

20
configs/helios4_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
@ -24,40 +25,47 @@ CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0x1
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_TLV_EEPROM=y
CONFIG_SPL_CMD_TLV_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-388-helios4"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_MVEBU=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=104000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SCSI=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y

13
configs/inetspace_v2_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" IS v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_MVSATA_IDE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

13
configs/net2big_v2_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" 2Big v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="2big2> "
CONFIG_CMD_EEPROM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_MVSATA_IDE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

14
configs/netspace_lite_v2_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" NS v2 Lite"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -39,15 +39,21 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_MVSATA_IDE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE=y

14
configs/netspace_max_v2_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" NS Max v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -39,15 +39,21 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_MVSATA_IDE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE=y

12
configs/netspace_mini_v2_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" NS v2 Mini"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SATA=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@ -37,12 +37,16 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_MVSATA_IDE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y

13
configs/netspace_v2_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_IDENT_STRING=" NS v2"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
@ -20,9 +21,8 @@ CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ns2> "
CONFIG_CMD_EEPROM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -39,15 +39,20 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=20000000
CONFIG_ENV_ADDR=0x70000
CONFIG_MVSATA_IDE=y
CONFIG_DM=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

6
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
View File

@ -11,7 +11,7 @@
#define VREF_MAX_INDEX 7
#define MAX_VALUE (1024 - 1)
#define MIN_VALUE (-MAX_VALUE)
#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0xf)
#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
u32 ca_delay;
int ddr3_tip_centr_skip_min_win_check = 0;
@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
min_read_sample = read_sample[cs_num];
}
min_read_sample = min_read_sample - 1;
max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
min_read_sample = min_read_sample + 2;
max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1;
if (min_read_sample >= 0xf)
min_read_sample = 0xf;
if (max_read_sample >= 0x1f)

61
drivers/net/mvpp2.c
View File

@ -1263,6 +1263,7 @@ struct buffer_location {
* can be enabled at once
*/
static struct buffer_location buffer_loc;
static int buffer_loc_init;
/*
* Page table entries are set to 1MB, or multiples of 1MB
@ -5247,40 +5248,44 @@ static int mvpp2_base_probe(struct udevice *dev)
* be active. Make this area DMA-safe by disabling the D-cache
*/
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
mmu_set_region_dcache_behaviour((unsigned long)bd_space,
BD_SPACE, DCACHE_OFF);
if (!buffer_loc_init) {
/* Align buffer area for descs and rx_buffers to 1MiB */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
mmu_set_region_dcache_behaviour((unsigned long)bd_space,
BD_SPACE, DCACHE_OFF);
buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
buffer_loc.tx_descs =
(struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
buffer_loc.tx_descs =
(struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
buffer_loc.rx_descs =
(struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
buffer_loc.rx_descs =
(struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
buffer_loc.bm_pool[i] =
(unsigned long *)((unsigned long)bd_space + size);
if (priv->hw_version == MVPP21)
size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
else
size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
buffer_loc.bm_pool[i] =
(unsigned long *)((unsigned long)bd_space + size);
if (priv->hw_version == MVPP21)
size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
else
size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
}
for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
buffer_loc.rx_buffer[i] =
(unsigned long *)((unsigned long)bd_space + size);
size += RX_BUFFER_SIZE;
}
/* Clear the complete area so that all descriptors are cleared */
memset(bd_space, 0, size);
buffer_loc_init = 1;
}
for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
buffer_loc.rx_buffer[i] =
(unsigned long *)((unsigned long)bd_space + size);
size += RX_BUFFER_SIZE;
}
/* Clear the complete area so that all descriptors are cleared */
memset(bd_space, 0, size);
/* Save base addresses for later use */
priv->base = (void *)devfdt_get_addr_index(dev, 0);
if (IS_ERR(priv->base))

99
include/configs/helios4.h
View File

@ -6,7 +6,6 @@
#ifndef _CONFIG_HELIOS4_H
#define _CONFIG_HELIOS4_H
#include <linux/sizes.h>
#include <linux/stringify.h>
/*
@ -30,49 +29,37 @@
#define CONFIG_ENV_MIN_ENTRIES 128
/*
* SATA/SCSI/AHCI configuration
*/
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
#define CONFIG_SYS_SCSI_MAX_LUN 2
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
/* Environment in SPI NOR flash */
#endif
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
/* Environment in MMC */
#define CONFIG_SYS_MMC_ENV_DEV 0
/* stay within first 1M */
#endif
/*
* For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
* boot image starts @ LBA-0.
* As result in MMC/eMMC case it will be a 1 sector gap between u-boot
* image and environment
*/
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_SCAN_SHOW
#endif
/* SATA support */
#ifdef CONFIG_SCSI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#endif
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define RELOCATION_LIMITS_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
"initrd_high=0x10000000\0"
/* SPL */
/*
* Select the boot device here
*
* Currently supported are:
* SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
* SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
*/
#define SPL_BOOT_SPI_NOR_FLASH 1
#define SPL_BOOT_SDIO_MMC_CARD 2
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
#endif
#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD
#endif
/* Defines for SPL */
#define CONFIG_SPL_SIZE (140 << 10)
@ -88,11 +75,10 @@
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
/* SPL related SPI defines */
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
#endif
#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
/* SPL related MMC defines */
#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
@ -100,6 +86,7 @@
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
#endif
#endif
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@ -121,16 +108,46 @@
#define BOOT_TARGET_DEVICES_USB(func)
#endif
#ifdef CONFIG_SATA
#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0)
#ifndef CONFIG_SCSI
#define BOOT_TARGET_DEVICES_SCSI_BUS0(func)
#define BOOT_TARGET_DEVICES_SCSI_BUS1(func)
#define BOOT_TARGET_DEVICES_SCSI_BUS2(func)
#else
#define BOOT_TARGET_DEVICES_SATA(func)
/*
* With SCSI enabled, M.2 SATA is always located on bus 0
*/
#define BOOT_TARGET_DEVICES_SCSI_BUS0(func) func(SCSI, scsi, 0)
/*
* Either one or both mPCIe slots may be configured as mSATA interfaces. The
* SCSI bus ids are assigned based on sequence of hardware present, not always
* tied to hardware slot ids. As such, use second SCSI bus if either slot is
* set for SATA, and only use third SCSI bus if both slots are SATA enabled.
*/
#if defined (CONFIG_HELIOS4_CON2_SATA) || defined (CONFIG_HELIOS4_CON3_SATA)
#define BOOT_TARGET_DEVICES_SCSI_BUS1(func) func(SCSI, scsi, 1)
#else
#define BOOT_TARGET_DEVICES_SCSI_BUS1(func)
#endif
#if defined (CONFIG_HELIOS4_CON2_SATA) && defined (CONFIG_HELIOS4_CON3_SATA)
#define BOOT_TARGET_DEVICES_SCSI_BUS2(func) func(SCSI, scsi, 2)
#else
#define BOOT_TARGET_DEVICES_SCSI_BUS2(func)
#endif
#endif /* CONFIG_SCSI */
/*
* The SCSI buses are attempted in increasing bus order, there is no current
* mechanism to alter the default bus priority order for booting.
*/
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_SATA(func) \
BOOT_TARGET_DEVICES_SCSI_BUS0(func) \
BOOT_TARGET_DEVICES_SCSI_BUS1(func) \
BOOT_TARGET_DEVICES_SCSI_BUS2(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)

19
include/configs/lacie_kw.h
View File

@ -83,18 +83,17 @@
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#ifdef CONFIG_SATA
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_LBA48
#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
defined(CONFIG_NET2BIG_V2)
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_IDE_MAXDEVICE 2
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#else
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#endif
#endif /* CONFIG_MVSATA_IDE */
#endif /* CONFIG_SATA */
/*
* Enable GPI0 support
@ -144,8 +143,8 @@
"set stdin $stdin,nc; " \
"set stdout $stdout,nc; " \
"set stderr $stderr,nc;\0" \
"diskload=ide reset && " \
"ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
"diskload=sata init && " \
"ext2load sata 0:1 $loadaddr /boot/$bootfile\0" \
"usbload=usb start && " \
"fatload usb 0:1 $loadaddr /boot/$bootfile\0"