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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

Browse Source 
Conflicts:

	include/asm-ppc/fsl_lbc.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
2008-06-11 21:33:16 +02:00
parent 2395db4886 ba04f70109
commit 5ea67393b8
103 changed files with 3228 additions and 1568 deletions
Download Patch File Download Diff File Expand all files Collapse all files

154
cpu/mpc85xx/cpu.c
View File

@@ -29,42 +29,46 @@
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
struct cpu_type {
char name[15];
u32 soc_ver;
};
#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8533),
CPU_TYPE_ENTRY(8533_E),
CPU_TYPE_ENTRY(8540),
CPU_TYPE_ENTRY(8541),
CPU_TYPE_ENTRY(8541_E),
CPU_TYPE_ENTRY(8543),
CPU_TYPE_ENTRY(8543_E),
CPU_TYPE_ENTRY(8544),
CPU_TYPE_ENTRY(8544_E),
CPU_TYPE_ENTRY(8545),
CPU_TYPE_ENTRY(8545_E),
CPU_TYPE_ENTRY(8547_E),
CPU_TYPE_ENTRY(8548),
CPU_TYPE_ENTRY(8548_E),
CPU_TYPE_ENTRY(8555),
CPU_TYPE_ENTRY(8555_E),
CPU_TYPE_ENTRY(8560),
CPU_TYPE_ENTRY(8567),
CPU_TYPE_ENTRY(8567_E),
CPU_TYPE_ENTRY(8568),
CPU_TYPE_ENTRY(8568_E),
CPU_TYPE_ENTRY(8572),
CPU_TYPE_ENTRY(8572_E),
CPU_TYPE_ENTRY(8533, 8533),
CPU_TYPE_ENTRY(8533, 8533_E),
CPU_TYPE_ENTRY(8540, 8540),
CPU_TYPE_ENTRY(8541, 8541),
CPU_TYPE_ENTRY(8541, 8541_E),
CPU_TYPE_ENTRY(8543, 8543),
CPU_TYPE_ENTRY(8543, 8543_E),
CPU_TYPE_ENTRY(8544, 8544),
CPU_TYPE_ENTRY(8544, 8544_E),
CPU_TYPE_ENTRY(8545, 8545),
CPU_TYPE_ENTRY(8545, 8545_E),
CPU_TYPE_ENTRY(8547, 8547_E),
CPU_TYPE_ENTRY(8548, 8548),
CPU_TYPE_ENTRY(8548, 8548_E),
CPU_TYPE_ENTRY(8555, 8555),
CPU_TYPE_ENTRY(8555, 8555_E),
CPU_TYPE_ENTRY(8560, 8560),
CPU_TYPE_ENTRY(8567, 8567),
CPU_TYPE_ENTRY(8567, 8567_E),
CPU_TYPE_ENTRY(8568, 8568),
CPU_TYPE_ENTRY(8568, 8568_E),
CPU_TYPE_ENTRY(8572, 8572),
CPU_TYPE_ENTRY(8572, 8572_E),
};
struct cpu_type *identify_cpu(uint ver)
{
int i;
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if (cpu_type_list[i].soc_ver == ver)
return &cpu_type_list[i];
return NULL;
}
int checkcpu (void)
{
sys_info_t sysinfo;
@@ -74,9 +78,13 @@ int checkcpu (void)
uint fam;
uint ver;
uint major, minor;
int i;
u32 ddr_ratio;
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
#else
u32 ddr_ratio = 0;
#endif
svr = get_svr();
ver = SVR_SOC_VER(svr);
@@ -85,14 +93,15 @@ int checkcpu (void)
puts("CPU: ");
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if (cpu_type_list[i].soc_ver == ver) {
puts(cpu_type_list[i].name);
break;
}
cpu = identify_cpu(ver);
if (cpu) {
puts(cpu->name);
if (i == ARRAY_SIZE(cpu_type_list))
if (svr & 0x80000)
puts("E");
} else {
puts("Unknown");
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
@@ -118,7 +127,7 @@ int checkcpu (void)
puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
@@ -159,7 +168,7 @@ int checkcpu (void)
}
#ifdef CONFIG_CPM2
printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
@@ -279,3 +288,68 @@ int dma_xfer(void *dest, uint count, void *src) {
return dma_check();
}
#endif
/*
* Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
* are hardcoded as "1"."size" is the number or entries, not a sizeof.
*/
void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
int loopval = 0x00004440;
volatile u32 *brp,*orp;
volatile u8* dummy = NULL;
int upmmask;
switch (upm) {
case UPMA:
mxmr = &lbc->mamr;
upmmask = BR_MS_UPMA;
break;
case UPMB:
mxmr = &lbc->mbmr;
upmmask = BR_MS_UPMB;
break;
case UPMC:
mxmr = &lbc->mcmr;
upmmask = BR_MS_UPMC;
break;
default:
printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
hang();
}
/* Find the address for the dummy write transaction */
for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
break;
}
}
if (i == 8) {
printf("Error: %s() could not find matching BR\n", __FUNCTION__);
hang();
}
for (i = 0; i < size; i++) {
/* 1 */
out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
/* 2 */
out_be32(&lbc->mdr, table[i]);
/* 3 */
mdr = in_be32(&lbc->mdr);
/* 4 */
*(volatile u8 *)dummy = 0;
/* 5 */
do {
mad = in_be32(mxmr) & 0x3f;
} while (mad <= old_mad && !(!mad && i == (size-1)));
old_mad = mad;
}
out_be32(mxmr, loopval); /* OP_NORMAL */
}

39
cpu/mpc85xx/cpu_init.c
View File

@@ -148,6 +148,12 @@ void cpu_init_early_f(void)
}
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
init_laws();
invalidate_tlb(0);
init_tlbs();
@@ -168,12 +174,6 @@ void cpu_init_f (void)
disable_tlb(14);
disable_tlb(15);
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#ifdef CONFIG_CPM2
config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
#endif
@@ -254,16 +254,7 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
#ifdef CONFIG_CLEAR_LAW0
#ifdef CONFIG_FSL_LAW
disable_law(0);
#else
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#endif
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
@@ -281,17 +272,17 @@ int cpu_init_r(void)
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
ver == SVR_8544 || ver == SVR_8568_E) {
printf ("L2 cache 512KB:");
puts ("512 KB ");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
} else {
printf ("L2 cache 256KB:");
puts("256 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
cache_ctl = 0xc8000000;
}
break;
case 0x10000000:
printf ("L2 cache 256KB:");
puts("256 KB ");
if (ver == SVR_8544 || ver == SVR_8544_E) {
cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
}
@@ -299,18 +290,18 @@ int cpu_init_r(void)
case 0x30000000:
case 0x00000000:
default:
printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
printf(" unknown size (0x%08x)\n", cache_ctl);
return -1;
}
if (l2cache->l2ctl & 0x80000000) {
printf(" already enabled.");
puts("already enabled");
l2srbar = l2cache->l2srbar0;
#ifdef CFG_INIT_L2_ADDR
if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
l2srbar = CFG_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
}
#endif /* CFG_INIT_L2_ADDR */
puts("\n");
@@ -318,10 +309,10 @@ int cpu_init_r(void)
asm("msync;isync");
l2cache->l2ctl = cache_ctl; /* invalidate & enable */
asm("msync;isync");
printf(" enabled\n");
puts("enabled\n");
}
#else
printf("L2 cache: disabled\n");
puts("disabled\n");
#endif
#ifdef CONFIG_QE
uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */

128
cpu/mpc85xx/fdt.c
View File

@@ -26,6 +26,7 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
extern void ft_qe_setup(void *blob);
#ifdef CONFIG_MP
@@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
}
#endif
#ifdef CONFIG_L2_CACHE
/* return size in kilobytes */
static inline u32 l2cache_size(void)
{
volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
u32 ver = SVR_SOC_VER(get_svr());
switch (l2siz_field) {
case 0x0:
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E)
return 128;
else
return 256;
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E)
return 256;
else
return 512;
break;
case 0x3:
return 1024;
break;
}
return 0;
}
static inline void ft_fixup_l2cache(void *blob)
{
int len, off;
u32 *ph;
struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
char compat_buf[38];
const u32 line_size = 32;
const u32 num_ways = 8;
const u32 size = l2cache_size() * 1024;
const u32 num_sets = size / (line_size * num_ways);
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
if (off < 0) {
debug("no cpu node fount\n");
return;
}
ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
if (ph == NULL) {
debug("no next-level-cache property\n");
return ;
}
off = fdt_node_offset_by_phandle(blob, *ph);
if (off < 0) {
printf("%s: %s\n", __func__, fdt_strerror(off));
return ;
}
if (cpu) {
len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
cpu->name);
sprintf(&compat_buf[len + 1], "cache");
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-line-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
}
#else
#define ft_fixup_l2cache(x)
#endif
static inline void ft_fixup_cache(void *blob)
{
int off;
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
u32 l1cfg0 = mfspr(SPRN_L1CFG0);
u32 l1cfg1 = mfspr(SPRN_L1CFG1);
u32 isize, iline_size, inum_sets, inum_ways;
u32 dsize, dline_size, dnum_sets, dnum_ways;
/* d-side config */
dsize = (l1cfg0 & 0x7ff) * 1024;
dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
dnum_sets = dsize / (dline_size * dnum_ways);
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
/* i-side config */
isize = (l1cfg1 & 0x7ff) * 1024;
inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
inum_sets = isize / (iline_size * inum_ways);
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-size", isize);
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
off = fdt_node_offset_by_prop_value(blob, off,
"device_type", "cpu", 4);
}
ft_fixup_l2cache(blob);
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
@@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_MP
ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
#endif
ft_fixup_cache(blob);
}

2
cpu/mpc85xx/spd_sdram.c
View File

@@ -1090,7 +1090,7 @@ setup_laws_and_tlbs(unsigned int memsize)
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
#endif
/*

8
cpu/mpc85xx/traps.c
View File

@@ -50,10 +50,12 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0;
extern unsigned long search_exception_table(unsigned long);
/*
* End of memory as shown by board info and determined by DDR setup.
* End of addressable memory. This may be less than the actual
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
extern ulong get_effective_memsize(void);
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
static __inline__ void set_tsr(unsigned long val)
{

3
cpu/mpc86xx/cpu_init.c
View File

@@ -119,8 +119,5 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
#ifdef CONFIG_FSL_LAW
disable_law(0);
#endif
return 0;
}

6
cpu/mpc86xx/spd_sdram.c
View File

@@ -1183,7 +1183,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 1 space.
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
#endif
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
@@ -1238,7 +1238,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 1 space.
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
#endif
}
@@ -1265,7 +1265,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 2 space.
*/
#ifdef CONFIG_FSL_LAW
set_law(8,
set_next_law(
(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
law_size_ddr2, LAW_TRGT_IF_DDR_2);
#endif