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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

Browse Source 
Conflicts:

	include/asm-ppc/fsl_lbc.h

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2008-06-11 21:33:16 +02:00
commit 5ea67393b8
103 changed files with 3228 additions and 1568 deletions
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1
MAKEALL
View File

@ -361,6 +361,7 @@ LIST_85xx=" \
stxssa \
TQM8540 \
TQM8541 \
TQM8548 \
TQM8555 \
TQM8560 \
"

34
Makefile
View File

@ -486,7 +486,7 @@ PATI_config: unconfig
#########################################################################
aev_config: unconfig
@$(MKCONFIG) -a aev ppc mpc5xxx tqm5200
@$(MKCONFIG) -a aev ppc mpc5xxx tqm5200 tqc
BC3450_config: unconfig
@$(MKCONFIG) -a BC3450 ppc mpc5xxx bc3450
@ -640,13 +640,13 @@ PM520_ROMBOOT_DDR_config: unconfig
@$(MKCONFIG) -a PM520 ppc mpc5xxx pm520
smmaco4_config: unconfig
@$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200
@$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 tqc
cm5200_config: unconfig
@$(MKCONFIG) -a cm5200 ppc mpc5xxx cm5200
spieval_config: unconfig
@$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200
@$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 tqc
TB5200_B_config \
TB5200_config: unconfig
@ -655,7 +655,7 @@ TB5200_config: unconfig
{ echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
$(XECHO) "... with MPC5200B processor" ; \
}
@$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200
@$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200 tqc
MINI5200_config \
EVAL5200_config \
@ -704,7 +704,7 @@ TQM5200_B_HIGHBOOT_config \
TQM5200_config \
TQM5200_STK100_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/tqm5200
@mkdir -p $(obj)board/tqc/tqm5200
@[ -z "$(findstring cam5200,$@)" ] || \
{ echo "#define CONFIG_CAM5200" >>$(obj)include/config.h ; \
echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \
@ -737,7 +737,7 @@ TQM5200_STK100_config: unconfig
@[ -z "$(findstring HIGHBOOT,$@)" ] || \
{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 tqc
uc101_config: unconfig
@$(MKCONFIG) uc101 ppc mpc5xxx uc101
motionpro_config: unconfig
@ -830,7 +830,7 @@ hermes_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx hermes
HMI10_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc
IAD210_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx IAD210 siemens
@ -1059,7 +1059,7 @@ RRvision_LCD_config: unconfig
@$(MKCONFIG) -a RRvision ppc mpc8xx RRvision
SM850_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx
@$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc
spc1920_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920
@ -1109,13 +1109,13 @@ virtlab2_config: unconfig
echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
$(XECHO) "... with LCD display" ; \
}
@$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx
@$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx tqc
TTTech_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc
uc100_config : unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx uc100
@ -1130,7 +1130,7 @@ wtk_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>$(obj)include/config.h
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx
@$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc
#########################################################################
## PPC4xx Systems
@ -1784,10 +1784,10 @@ TQM8265_AA_config: unconfig
echo "#undef CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
$(XECHO) "... without 60x Bus Mode" ; \
fi
@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260
@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260 tqc
TQM8272_config: unconfig
@$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272
@$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272 tqc
VoVPN-GW_66MHz_config \
VoVPN-GW_100MHz_config: unconfig
@ -2114,7 +2114,7 @@ sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
#########################################################################
@ -2233,6 +2233,7 @@ stxssa_4M_config: unconfig
TQM8540_config \
TQM8541_config \
TQM8548_config \
TQM8555_config \
TQM8560_config: unconfig
@mkdir -p $(obj)include
@ -2241,9 +2242,8 @@ TQM8560_config: unconfig
echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; \
echo "#define CFG_BOOTFILE_PATH \"/tftpboot/tqm$${CTYPE}/uImage\"">>$(obj)include/config.h
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
#########################################################################
## MPC86xx Systems

14
board/atum8548/law.c
View File

@ -48,14 +48,14 @@
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW_ENTRY(8, CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

10
board/freescale/mpc8540ads/law.c
View File

@ -46,13 +46,13 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

42
board/freescale/mpc8540ads/mpc8540ads.c
View File

@ -41,12 +41,6 @@ void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
puts("Board: ADS\n");
@ -230,42 +224,6 @@ sdram_init(void)
udelay(100);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.

10
board/freescale/mpc8541cds/law.c
View File

@ -47,12 +47,12 @@
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

44
board/freescale/mpc8541cds/mpc8541cds.c
View File

@ -196,11 +196,6 @@ const iop_conf_t iop_conf_tab[4][32] = {
}
};
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
@ -425,45 +420,6 @@ sdram_init(void)
#endif /* enable SDRAM init */
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
CFG_MEMTEST_START,
CFG_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test passed.\n");
return 0;
}
#endif
#if defined(CONFIG_PCI)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.

16
board/freescale/mpc8544ds/law.c
View File

@ -28,15 +28,15 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(4, CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(5, CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(6, CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(7, CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW_ENTRY(8, CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
SET_LAW(CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
/* contains both PCIE3 MEM & IO space */
SET_LAW_ENTRY(9, CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
};
int num_law_entries = ARRAY_SIZE(law_table);

44
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -40,11 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void sdram_init(void);
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
@ -83,45 +78,6 @@ initdram(int board_type)
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
CFG_MEMTEST_START,
CFG_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test passed.\n");
return 0;
}
#endif
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

16
board/freescale/mpc8548cds/law.c
View File

@ -52,21 +52,21 @@
struct law_entry law_table[] = {
#ifdef CFG_PCI1_MEM_PHYS
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
#endif
#ifdef CFG_PCI2_MEM_PHYS
SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
#endif
#ifdef CFG_PCIE1_MEM_PHYS
SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
#endif
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW_ENTRY(8, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
#ifdef CFG_RIO_MEM_PHYS
SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
#endif
};

44
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -45,11 +45,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
void sdram_init(void);
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
@ -250,45 +245,6 @@ sdram_init(void)
#endif /* enable SDRAM init */
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
CFG_MEMTEST_START,
CFG_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test passed.\n");
return 0;
}
#endif
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.

10
board/freescale/mpc8555cds/law.c
View File

@ -47,12 +47,12 @@
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

44
board/freescale/mpc8555cds/mpc8555cds.c
View File

@ -194,11 +194,6 @@ const iop_conf_t iop_conf_tab[4][32] = {
}
};
int board_early_init_f (void)
{
return 0;
}
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
@ -422,45 +417,6 @@ sdram_init(void)
#endif /* enable SDRAM init */
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
CFG_MEMTEST_START,
CFG_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test passed.\n");
return 0;
}
#endif
#ifdef CONFIG_PCI
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it

10
board/freescale/mpc8560ads/law.c
View File

@ -46,13 +46,13 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

42
board/freescale/mpc8560ads/mpc8560ads.c
View File

@ -212,12 +212,6 @@ typedef struct bcsr_ {
volatile unsigned char bcsr5;
} bcsr_t;
int board_early_init_f (void)
{
return 0;
}
void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
@ -433,42 +427,6 @@ sdram_init(void)
udelay(100);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.

12
board/freescale/mpc8568mds/law.c
View File

@ -50,13 +50,13 @@
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
SET_LAW_ENTRY(7, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

39
board/freescale/mpc8568mds/mpc8568mds.c
View File

@ -292,45 +292,6 @@ sdram_init(void)
#endif /* enable SDRAM init */
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf("Testing DRAM from 0x%08x to 0x%08x\n",
CFG_MEMTEST_START,
CFG_MEMTEST_END);
printf("DRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("DRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("DRAM test passed.\n");
return 0;
}
#endif
#if defined(CONFIG_PCI)
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8568mds_config_table[] = {

18
board/freescale/mpc8610hpcd/law.c
View File

@ -29,16 +29,16 @@
struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
#endif
SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(8, CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(9, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
SET_LAW(CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
};
int num_law_entries = ARRAY_SIZE(law_table);

18
board/freescale/mpc8641hpcn/law.c
View File

@ -47,18 +47,18 @@
struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW((CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
#endif
SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);

6
board/mpc8540eval/law.c
View File

@ -43,11 +43,11 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
#ifndef CONFIG_RAM_AS_FLASH
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
#endif
};

10
board/pm854/law.c
View File

@ -46,13 +46,13 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

10
board/pm856/law.c
View File

@ -46,13 +46,13 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

8
board/sbc8548/law.c
View File

@ -46,12 +46,12 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

6
board/sbc8560/law.c
View File

@ -51,10 +51,10 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

18
board/sbc8641d/law.c
View File

@ -44,15 +44,15 @@
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(4, 0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(5, CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(6, CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(7, 0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
SET_LAW_ENTRY(9, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
SET_LAW(CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);

2
board/socrates/Makefile
View File

@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
#
COBJS := $(BOARD).o law.o tlb.o sdram.o
COBJS := $(BOARD).o law.o tlb.o sdram.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

3
board/socrates/config.mk
View File

@ -25,6 +25,5 @@
#
# socrates board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
#
TEXT_BASE = 0xfffc0000
TEXT_BASE = 0xfffa0000

21
board/socrates/law.c
View File

@ -33,13 +33,12 @@
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x0000_0000 0x2fff_ffff DDR 512M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xc000_0000 0xc00f_ffff FPGA 1M
* 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR)
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
* 0xfc00_0000 0xffff_ffff FLASH 64M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
@ -47,11 +46,13 @@
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#if defined(CFG_FPGA_BASE)
SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

218
board/socrates/nand.c Normal file
View File

@ -0,0 +1,218 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CFG_NAND_BASE)
#include <nand.h>
#include <asm/errno.h>
#include <asm/io.h>
static int state;
static void nand_write_byte(struct mtd_info *mtd, u_char byte);
static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
static void nand_write_word(struct mtd_info *mtd, u16 word);
static u_char nand_read_byte(struct mtd_info *mtd);
static u16 nand_read_word(struct mtd_info *mtd);
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
static int nand_device_ready(struct mtd_info *mtdinfo);
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd);
#define FPGA_NAND_CMD_MASK (0x7 << 28)
#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
#define FPGA_NAND_CMD_ADDR (0x1 << 28)
#define FPGA_NAND_CMD_READ (0x2 << 28)
#define FPGA_NAND_CMD_WRITE (0x3 << 28)
#define FPGA_NAND_BUSY (0x1 << 15)
#define FPGA_NAND_ENABLE (0x1 << 31)
#define FPGA_NAND_DATA_SHIFT 16
/**
* nand_write_byte - write one byte to the chip
* @mtd: MTD device structure
* @byte: pointer to data byte to write
*/
static void nand_write_byte(struct mtd_info *mtd, u_char byte)
{
nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
}
/**
* nand_write_word - write one word to the chip
* @mtd: MTD device structure
* @word: data word to write
*/
static void nand_write_word(struct mtd_info *mtd, u16 word)
{
nand_write_buf(mtd, (const uchar *)&word, sizeof(word));
}
/**
* nand_write_buf - write buffer to chip
* @mtd: MTD device structure
* @buf: data buffer
* @len: number of bytes to write
*/
static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
struct nand_chip *this = mtd->priv;
long val;
if ((state & FPGA_NAND_CMD_MASK) == FPGA_NAND_CMD_MASK) {
/* Write data */
val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_WRITE;
} else {
/* Write address or command */
val = state;
}
for (i = 0; i < len; i++) {
out_be32(this->IO_ADDR_W, val | (buf[i] << FPGA_NAND_DATA_SHIFT));
}
}
/**
* nand_read_byte - read one byte from the chip
* @mtd: MTD device structure
*/
static u_char nand_read_byte(struct mtd_info *mtd)
{
u8 byte;
nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
return byte;
}
/**
* nand_read_word - read one word from the chip
* @mtd: MTD device structure
*/
static u16 nand_read_word(struct mtd_info *mtd)
{
u16 word;
nand_read_buf(mtd, (uchar *)&word, sizeof(word));
return word;
}
/**
* nand_read_buf - read chip data into buffer
* @mtd: MTD device structure
* @buf: buffer to store date
* @len: number of bytes to read
*/
static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
int i;
struct nand_chip *this = mtd->priv;
int val;
val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
out_be32(this->IO_ADDR_W, val);
for (i = 0; i < len; i++) {
buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
}
}
/**
* nand_verify_buf - Verify chip data against buffer
* @mtd: MTD device structure
* @buf: buffer containing the data to compare
* @len: number of bytes to compare
*/
static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
if (buf[i] != nand_read_byte(mtd));
return -EFAULT;
}
return 0;
}
/**
* nand_device_ready - Check the NAND device is ready for next command.
* @mtd: MTD device structure
*/
static int nand_device_ready(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
return 0; /* busy */
return 1;
}
/**
* nand_hwcontrol - NAND control functions wrapper.
* @mtd: MTD device structure
* @cmd: Command
*/
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
{
switch(cmd) {
case NAND_CTL_CLRALE:
state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
break;
case NAND_CTL_CLRCLE:
state |= FPGA_NAND_CMD_MASK; /* use all 1s to mark */
break;
case NAND_CTL_SETCLE:
state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_COMMAND;
break;
case NAND_CTL_SETALE:
state = (state & ~FPGA_NAND_CMD_MASK) | FPGA_NAND_CMD_ADDR;
break;
case NAND_CTL_SETNCE:
state |= FPGA_NAND_ENABLE;
break;
case NAND_CTL_CLRNCE:
state &= ~FPGA_NAND_ENABLE;
break;
default:
printf("%s: unknown cmd %#x\n", __FUNCTION__, cmd);
break;
}
}
int board_nand_init(struct nand_chip *nand)
{
nand->hwcontrol = nand_hwcontrol;
nand->eccmode = NAND_ECC_SOFT;
nand->dev_ready = nand_device_ready;
nand->write_byte = nand_write_byte;
nand->read_byte = nand_read_byte;
nand->write_word = nand_write_word;
nand->read_word = nand_read_word;
nand->write_buf = nand_write_buf;
nand->read_buf = nand_read_buf;
nand->verify_buf = nand_verify_buf;
return 0;
}
#endif

22
board/socrates/socrates.c
View File

@ -35,7 +35,11 @@
#include <flash.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
#if defined(CFG_FPGA_BASE)
#include "upm_table.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
@ -58,7 +62,8 @@ int checkboard (void)
putc('\n');
#ifdef CONFIG_PCI
if (gur->porpllsr & (1<<15)) {
/* Check the PCI_clk sel bit */
if (in_be32(&gur->porpllsr) & (1<<15)) {
src = "SYSCLK";
f = CONFIG_SYS_CLK_FREQ;
} else {
@ -74,7 +79,10 @@ int checkboard (void)
* Initialize local bus.
*/
local_bus_init ();
#if defined(CFG_FPGA_BASE)
/* Init UPMA for FPGA access */
upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
#endif
return 0;
}
@ -216,5 +224,15 @@ ft_board_setup(void *blob, bd_t *bd)
if (rc)
printf("Unable to update property NOR mapping, err=%s\n",
fdt_strerror(rc));
#if defined (CFG_FPGA_BASE)
memset(val, 0, sizeof(val));
val[0] = CFG_FPGA_BASE;
rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg",
val, sizeof(val), 1);
if (rc)
printf("Unable to update property \"fpga\", err=%s\n",
fdt_strerror(rc));
#endif
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

25
board/socrates/tlb.c
View File

@ -46,16 +46,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
* TLB 0: 64M Non-cacheable, guarded
* 0xfc000000 64M FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
@ -73,21 +70,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
#if defined(CFG_FPGA_BASE)
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
* TLB 4: 1M Non-cacheable, guarded
* 0xc0000000 1M FPGA and NAND
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
0, 4, BOOKE_PAGESZ_1M, 1),
#endif
/*
* TLB 6: 64M Non-cacheable, guarded

55
board/socrates/upm_table.h Normal file
View File

@ -0,0 +1,55 @@
/*
* (C) Copyright 2008
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* Copyright 2004, 2007 Freescale Semiconductor, Inc.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __UPM_TABLE_H
#define __UPM_TABLE_H
/* UPM Table Configuration Code for FPGA access */
static const unsigned int UPMTableA[] =
{
0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, //Words 0 to 3
0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, //Words 4 to 7
0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, //Words 8 to 11
0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, //Words 12 to 15
0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, //Words 16 to 19
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, //Words 24 to 27
0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, //Words 28 to 31
0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 32 to 35
0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 36 to 39
0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 48 to 51
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 //Words 60 to 63
};
#endif

10
board/stxgp3/law.c
View File

@ -46,13 +46,13 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

12
board/stxssa/law.c
View File

@ -47,14 +47,14 @@
struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
#endif
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
/* Map the whole localbus, including flash and reset latch. */
SET_LAW_ENTRY(6, CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

0
board/tqm5200/Makefile → board/tqc/tqm5200/Makefile
View File

0
board/tqm5200/cam5200_flash.c → board/tqc/tqm5200/cam5200_flash.c
View File

0
board/tqm5200/cmd_stk52xx.c → board/tqc/tqm5200/cmd_stk52xx.c
View File

0
board/tqm5200/cmd_tb5200.c → board/tqc/tqm5200/cmd_tb5200.c
View File

0
board/tqm5200/config.mk → board/tqc/tqm5200/config.mk
View File

0
board/tqm5200/mt48lc16m16a2-75.h → board/tqc/tqm5200/mt48lc16m16a2-75.h
View File

0
board/tqm5200/tqm5200.c → board/tqc/tqm5200/tqm5200.c
View File

0
board/tqm8260/Makefile → board/tqc/tqm8260/Makefile
View File

0
board/tqm8260/config.mk → board/tqc/tqm8260/config.mk
View File

0
board/tqm8260/flash.c → board/tqc/tqm8260/flash.c
View File

0
board/tqm8260/tqm8260.c → board/tqc/tqm8260/tqm8260.c
View File

0
board/tqm8272/Makefile → board/tqc/tqm8272/Makefile
View File

0
board/tqm8272/config.mk → board/tqc/tqm8272/config.mk
View File

0
board/tqm8272/tqm8272.c → board/tqc/tqm8272/tqm8272.c
View File

0
board/tqm834x/Makefile → board/tqc/tqm834x/Makefile
View File

0
board/tqm834x/config.mk → board/tqc/tqm834x/config.mk
View File

0
board/tqm834x/pci.c → board/tqc/tqm834x/pci.c
View File

0
board/tqm834x/tqm834x.c → board/tqc/tqm834x/tqm834x.c
View File

8
board/tqm85xx/Makefile → board/tqc/tqm85xx/Makefile
View File

@ -25,8 +25,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o sdram.o law.o tlb.o
COBJS-y += $(BOARD).o
COBJS-y += sdram.o
COBJS-y += law.o
COBJS-y += tlb.o
COBJS-$(CONFIG_NAND) += nand.o
COBJS := $(COBJS-y)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

0
board/tqm85xx/config.mk → board/tqc/tqm85xx/config.mk
View File

86
board/tqc/tqm85xx/law.c Normal file
View File

@ -0,0 +1,86 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
* Standard mapping:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M
* 0xef00_0000 0xefff_ffff PCI express IO 16M
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M
*
* Big FLASH mapping:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xa000_ffff CCSR 1M
* 0xa200_0000 0xa2ff_ffff PCI1 IO 16M
* 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M
* 0xaf00_0000 0xafff_ffff PCI express IO 16M
* 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M
* 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
#ifdef CONFIG_TQM_BIGFLASH
#define LAW_3_SIZE LAW_SIZE_1G
#define LAW_5_SIZE LAW_SIZE_256M
#else
#define LAW_3_SIZE LAW_SIZE_128M
#define LAW_5_SIZE LAW_SIZE_512M
#endif
struct law_entry law_table[] = {
SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#ifdef CONFIG_PCIE1
SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
#else /* !CONFIG_PCIE1 */
SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
#endif /* CONFIG_PCIE1 */
#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
#ifdef CONFIG_PCIE1
SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
#endif /* CONFIG_PCIE */
};
int num_law_entries = ARRAY_SIZE (law_table);

469
board/tqc/tqm85xx/nand.c Normal file
View File

@ -0,0 +1,469 @@
/*
* (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
*
* (C) Copyright 2006
* Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/fsl_upm.h>
#include <ioports.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
extern uint get_lbc_clock (void);
/* index of UPM RAM array run pattern for NAND command cycle */
#define CFG_NAN_UPM_WRITE_CMD_OFS 0x08
/* index of UPM RAM array run pattern for NAND address cycle */
#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x10
/* Structure for table with supported UPM timings */
struct upm_freq {
ulong freq;
const u32 *upm_patt;
uchar gpl4_disable;
uchar ehtr;
uchar ead;
};
/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */
/* UPM pattern for bus clock = 25 MHz */
static const u32 upm_patt_25[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 33.3 MHz */
static const u32 upm_patt_33[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 41.7 MHz */
static const u32 upm_patt_42[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 50 MHz */
static const u32 upm_patt_50[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 66.7 MHz */
static const u32 upm_patt_67[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 83.3 MHz */
static const u32 upm_patt_83[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 100 MHz */
static const u32 upm_patt_100[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 133.3 MHz */
static const u32 upm_patt_133[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* UPM pattern for bus clock = 166.7 MHz */
static const u32 upm_patt_167[] = {
/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write CMD */
/* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35,
/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Read Burst RAM array entry -> NAND Write ADDR */
/* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35,
/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Single RAM array entry -> NAND Write Data */
/* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05,
/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* UPM Write Burst RAM array entry -> unused */
/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Refresh Timer RAM array entry -> unused */
/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
/* UPM Exception RAM array entry -> unsused */
/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
};
/* Supported UPM timings */
struct upm_freq upm_freq_table[] = {
/* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */
{25000000, upm_patt_25, 1, 0, 0},
{33333333, upm_patt_33, 1, 0, 0},
{41666666, upm_patt_42, 1, 0, 0},
{50000000, upm_patt_50, 0, 0, 0},
{66666666, upm_patt_67, 0, 0, 0},
{83333333, upm_patt_83, 0, 0, 0},
{100000000, upm_patt_100, 0, 1, 1},
{133333333, upm_patt_133, 0, 1, 1},
{166666666, upm_patt_167, 0, 1, 1},
};
#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq))
volatile const u32 *nand_upm_patt;
/*
* write into UPMB ram
*/
static void upmb_write (u_char addr, ulong val)
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
out_be32 (&lbc->mdr, val);
clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK,
MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
/* dummy access to perform write */
out_8 ((void __iomem *)CFG_NAND0_BASE, 0);
clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
}
/*
* Initialize UPM for NAND flash access.
*/
static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
{
uint i;
uint or3 = CFG_OR3_PRELIM;
uint clock = get_lbc_clock ();
out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */
out_be32 (&lbc->br3, CFG_BR3_PRELIM);
/*
* Search appropriate UPM table for bus clock.
* If the bus clock exceeds a tolerated value, take the UPM timing for
* the next higher supported frequency to ensure that access works
* (even the access may be slower then).
*/
for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++)
;
if (i >= UPM_FREQS)
/* no valid entry found */
/* take last entry with configuration for max. bus clock */
i--;
if (upm_freq_table[i].ehtr) {
/* EHTR must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EHTR;
}
if (upm_freq_table[i].ead)
/* EAD must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EAD;
out_be32 (&lbc->or3, or3);
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
for (i = 0; i < 64; i++) {
upmb_write (i, *nand_upm_patt);
nand_upm_patt++;
}
/* Put UPM back to normal operation mode */
if (upm_freq_table[i].gpl4_disable)
/* GPL4 must be disabled according to timing specification */
out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
return;
}
static struct fsl_upm_nand fun = {
.width = 8,
.upm_cmd_offset = 0x08,
.upm_addr_offset = 0x10,
.chip_delay = NAND_BIG_DELAY_US,
};
void board_nand_select_device (struct nand_chip *nand, int chip)
{
}
int board_nand_init (struct nand_chip *nand)
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
if (!nand_upm_patt)
nand_upm_setup (lbc);
fun.upm.io_addr = nand->IO_ADDR_R;
fun.upm.mxmr = (void __iomem *)&lbc->mbmr;
fun.upm.mdr = (void __iomem *)&lbc->mdr;
fun.upm.mar = (void __iomem *)&lbc->mar;
return fsl_upm_nand_init (nand, &fun);
}

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board/tqc/tqm85xx/sdram.c Normal file
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@ -0,0 +1,371 @@
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>
struct sdram_conf_s {
unsigned long size;
unsigned long reg;
#ifdef CONFIG_TQM8548
unsigned long refresh;
#endif /* CONFIG_TQM8548 */
};
typedef struct sdram_conf_s sdram_conf_t;
#ifdef CONFIG_TQM8548
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
{(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
};
#else /* !CONFIG_TQM8548 */
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
{( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
};
#endif /* CONFIG_TQM8548 */
#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
int cas_latency (void);
/*
* Autodetect onboard DDR SDRAM on 85xx platforms
*
* NOTE: Some of the hardcoded values are hardware dependant,
* so this should be extended for other future boards
* using this routine!
*/
long int sdram_setup (int casl)
{
int i;
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
#ifdef CONFIG_TQM8548
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#else /* !CONFIG_TQM8548 */
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
#endif /* CONFIG_TQM8548 */
/*
* Disable memory controller.
*/
ddr->cs0_config = 0;
ddr->sdram_cfg = 0;
#ifdef CONFIG_TQM8548
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
ddr->timing_cfg_3 = 0x00010000;
/* TIMING CFG 1, 533MHz
* PRETOACT: 4 Clocks
* ACTTOPRE: 12 Clocks
* ACTTORW: 4 Clocks
* CASLAT: 4 Clocks
* REFREC: 34 Clocks
* WRREC: 4 Clocks
* ACTTOACT: 3 Clocks
* WRTORD: 2 Clocks
*/
ddr->timing_cfg_1 = 0x4C47A432;
/* TIMING CFG 2, 533MHz
* ADD_LAT: 3 Clocks
* CPO: READLAT + 1
* WR_LAT: 3 Clocks
* RD_TO_PRE: 2 Clocks
* WR_DATA_DELAY: 1/2 Clock
* CKE_PLS: 1 Clock
* FOUR_ACT: 13 Clocks
*/
ddr->timing_cfg_2 = 0x3318484D;
/* DDR SDRAM Mode, 533MHz
* MRS: Extended Mode Register
* OUT: Outputs enabled
* RDQS: no
* DQS: enabled
* OCD: default state
* RTT: 75 Ohms
* Posted CAS: 3 Clocks
* ODS: reduced strength
* DLL: enabled
* MR: Mode Register
* PD: fast exit
* WR: 4 Clocks
* DLL: no DLL reset
* TM: normal
* CAS latency: 4 Clocks
* BT: sequential
* Burst length: 4
*/
ddr->sdram_mode = 0x439E0642;
/* DDR SDRAM Interval, 533MHz
* REFINT: 1040 Clocks
* BSTOPRE: 256
*/
ddr->sdram_interval = (1040 << 16) | 0x100;
/*
* workaround for erratum DD10 of MPC8458 family below rev. 2.0:
* DDR IO receiver must be set to an acceptable bias point by modifying
* a hidden register.
*/
if (SVR_REV (get_svr ()) < 0x20) {
gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
}
/* DDR SDRAM CFG 2
* FRC_SR: normal mode
* SR_IE: no self-refresh interrupt
* DLL_RST_DIS: don't care, leave at reset value
* DQS_CFG: differential DQS signals
* ODT_CFG: assert ODT to internal IOs only during reads to DRAM
* LVWx_CFG: don't care, leave at reset value
* NUM_PR: 1 refresh will be issued at a time
* DM_CFG: don't care, leave at reset value
* D_INIT: no data initialization
*/
ddr->sdram_cfg_2 = 0x04401000;
/* DDR SDRAM MODE 2
* MRS: Extended Mode Register 2
*/
ddr->sdram_mode_2 = 0x8000C000;
/* DDR SDRAM CLK CNTL
* CLK_ADJUST: 1/2 Clock 0x02000000
* CLK_ADJUST: 5/8 Clock 0x02800000
*/
ddr->sdram_clk_cntl = 0x02800000;
/* wait for clock stabilization */
asm ("sync;isync;msync");
udelay(1000);
/* DDR SDRAM CLK CNTL
* MEM_EN: enabled
* SREN: don't care, leave at reset value
* ECC_EN: no error report
* RD_EN: no register DIMMs
* SDRAM_TYPE: DDR2
* DYN_PWR: no power management
* 32_BE: don't care, leave at reset value
* 8_BE: 4 beat burst
* NCAP: don't care, leave at reset value
* 2T_EN: 1T Timing
* BA_INTLV_CTL: no interleaving
* x32_EN: x16 organization
* PCHB8: MA[10] for auto-precharge
* HSE: half strength for single and 2-layer stacks
* (full strength for 3- and 4-layer stacks no yet considered)
* MEM_HALT: no halt
* BI: automatic initialization
*/
ddr->sdram_cfg = 0x83000008;
asm ("sync; isync; msync");
udelay(1000);
#else /* !CONFIG_TQM8548 */
switch (casl) {
case 20:
cfg_ddr_timing1 = 0x47405331 | (3 << 16);
cfg_ddr_mode = 0x40020002 | (2 << 4);
break;
case 25:
cfg_ddr_timing1 = 0x47405331 | (4 << 16);
cfg_ddr_mode = 0x40020002 | (6 << 4);
break;
case 30:
default:
cfg_ddr_timing1 = 0x47405331 | (5 << 16);
cfg_ddr_mode = 0x40020002 | (3 << 4);
break;
}
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
ddr->timing_cfg_1 = cfg_ddr_timing1;
ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
ddr->sdram_mode = cfg_ddr_mode;
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
ddr->err_disable = 0x0000000D;
asm ("sync; isync; msync");
udelay (1000);
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
asm ("sync; isync; msync");
udelay (1000);
#endif /* CONFIG_TQM8548 */
for (i = 0; i < N_DDR_CS_CONF; i++) {
ddr->cs0_config = ddr_cs_conf[i].reg;
if (get_ram_size (0, ddr_cs_conf[i].size) ==
ddr_cs_conf[i].size) {
/*
* size detected -> set Chip Select Bounds Register
*/
ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
break;
}
}
#ifdef CONFIG_TQM8548
if (i < N_DDR_CS_CONF) {
/* Adjust refresh rate for DDR2 */
ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
(ddr_cs_conf[i].refresh & 0x0000F000);
return ddr_cs_conf[i].size;
}
#endif /* CONFIG_TQM8548 */
/* return size if detected, else return 0 */
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}
void board_add_ram_info (int use_default)
{
int casl;
if (use_default)
casl = CONFIG_DDR_DEFAULT_CL;
else
casl = cas_latency ();
puts (" (CL=");
switch (casl) {
case 20:
puts ("2)");
break;
case 25:
puts ("2.5)");
break;
case 30:
puts ("3)");
break;
}
}
long int initdram (int board_type)
{
long dram_size = 0;
int casl;
#if defined(CONFIG_DDR_DLL)
/*
* This DLL-Override only used on TQM8540 and TQM8560
*/
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i, x;
x = 10;
/*
* Work around to stabilize DDR DLL
*/
gur->ddrdllcr = 0x81000000;
asm ("sync; isync; msync");
udelay (200);
while (gur->ddrdllcr != 0x81000100) {
gur->devdisr = gur->devdisr | 0x00010000;
asm ("sync; isync; msync");
for (i = 0; i < x; i++)
;
gur->devdisr = gur->devdisr & 0xfff7ffff;
asm ("sync; isync; msync");
x++;
}
}
#endif
casl = cas_latency ();
dram_size = sdram_setup (casl);
if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
/*
* Try again with default CAS latency
*/
puts ("Problem with CAS lantency");
board_add_ram_info (1);
puts (", using default CL!\n");
casl = CONFIG_DDR_DEFAULT_CL;
dram_size = sdram_setup (casl);
puts (" ");
}
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf ("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test passed.\n");
return 0;
}
#endif

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/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
CFG_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
CFG_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
CFG_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
#ifndef CONFIG_TQM_BIGFLASH
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
CFG_FLASH_BASE + 0x4000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
CFG_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
#ifdef CONFIG_PCIE1
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M PCI express MEM Second half
*/
SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
CFG_PCIE1_MEM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
CFG_RIO_MEM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#endif /* CONFIG_PCIE */
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 16M PCI1 IO
* 0xe3000000 16M CAN and NAND Flash
*/
SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
CFG_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
#ifdef CONFIG_PCIE1
/*
* TLB 9: 16M Non-cacheable, guarded
* 0xef000000 16M PCI express IO
*/
SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
#else /* CONFIG_TQM_BIGFLASH */
/*
* TLB 0,1,2,3: 1G Non-cacheable, guarded
* 0xc0000000 1G FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
CFG_FLASH_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
CFG_FLASH_BASE + 0x20000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
CFG_FLASH_BASE + 0x30000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1),
/*
* TLB 4: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
CFG_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#ifdef CONFIG_PCIE1
/*
* TLB 6: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
/*
* TLB 6: 256M Non-cacheable, guarded
* 0xb0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#endif /* CONFIG_PCIE */
/*
* TLB 7: 64M Non-cacheable, guarded
* 0xa0000000 1M CCSRBAR
* 0xa2000000 16M PCI1 IO
* 0xa3000000 16M CAN and NAND Flash
*/
SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
/*
* TLB 8+9: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
CFG_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_256M, 1),
#ifdef CONFIG_PCIE1
/*
* TLB 10: 16M Non-cacheable, guarded
* 0xaf000000 16M PCI express IO
*/
SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 10, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
#endif /* CONFIG_TQM_BIGFLASH */
};
int num_tlb_entries = ARRAY_SIZE (tlb_table);

744
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/*
* (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
*
* (C) Copyright 2006
* Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/io.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
#ifdef CONFIG_PS2MULT
void ps2mult_early_init (void);
#endif
#ifdef CONFIG_CPM2
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A: conf, ppar, psor, pdir, podr, pdat */
{
{1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
{1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
{1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
{1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
{1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
{1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
{0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
{0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
{0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
{0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
{1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
{1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
{1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
{1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
{1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
{1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
{1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
{1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
{0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
{0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
{0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
{0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
{0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
{0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
{0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
{0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
{0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
{0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
{0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
{0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
{0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
{0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
},
/* Port B: conf, ppar, psor, pdir, podr, pdat */
{
{1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
{1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
{1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
{1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
{1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
{1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
{1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
{1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
{1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
{1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
{1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
{1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
{1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
{1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
{1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
{1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
{1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
{1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
{1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
{1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
{1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
{1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
{1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
{1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
{1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
{1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
{1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
{1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
{0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
{0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
{0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
{0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
},
/* Port C: conf, ppar, psor, pdir, podr, pdat */
{
{0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
{0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
{0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
{0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
{0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
{0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
{0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
{0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
{0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
{0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
{1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
{1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
{1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
{1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
{1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
{1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
{0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
{0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
{0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
{0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
{0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
{0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
{0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
{0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
{0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
{0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
{0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
{0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
{0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
{0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
{0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
{0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
},
/* Port D: conf, ppar, psor, pdir, podr, pdat */
{
#ifdef CONFIG_TQM8560
{1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
{1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
{1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
#else /* !CONFIG_TQM8560 */
{0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
{0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
{0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
#endif /* CONFIG_TQM8560 */
{1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
{1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
{1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
{0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
{0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
{0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
{0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
{0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
{0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
{0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
{0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
{0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
{0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
{0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
{0, 0, 0, 1, 0, 0}, /* PD14: LED */
{0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
{0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
{0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
{0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
{0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
{0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
{0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
{0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
{0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
{0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
{0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
{0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
{0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
{0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
}
};
#endif /* CONFIG_CPM2 */
#define CASL_STRING1 "casl=xx"
#define CASL_STRING2 "casl="
static const int casl_table[] = { 20, 25, 30 };
#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
int cas_latency (void)
{
char *s = getenv ("serial#");
int casl;
int val;
int i;
casl = CONFIG_DDR_DEFAULT_CL;
if (s != NULL) {
if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
CASL_STRING2, strlen (CASL_STRING2)) == 0) {
val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
for (i = 0; i < N_CASL; ++i) {
if (val == casl_table[i]) {
return val;
}
}
}
}
return casl;
}
int checkboard (void)
{
char *s = getenv ("serial#");
printf ("Board: %s", CONFIG_BOARDNAME);
if (s != NULL) {
puts (", serial# ");
puts (s);
}
putc ('\n');
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/*
* Recalculate CS configuration if second FLASH bank is available
*/
if (flash_info[0].size > 0) {
memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
(CFG_OR1_PRELIM & 0x00007fff);
memctl->br1 = gd->bd->bi_flashstart |
(CFG_BR1_PRELIM & 0x00007fff);
/*
* Re-check to get correct base address for bank 1
*/
flash_get_size (gd->bd->bi_flashstart, 0);
} else {
memctl->or1 = 0;
memctl->br1 = 0;
}
/*
* If bank 1 is equipped, bank 0 is mapped after bank 1
*/
memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
(CFG_OR0_PRELIM & 0x00007fff);
memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
(CFG_BR0_PRELIM & 0x00007fff);
/*
* Re-check to get correct base address for bank 0
*/
flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
#ifdef CFG_ENV_ADDR_REDUND
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
#endif
return 0;
}
#ifdef CONFIG_CAN_DRIVER
/*
* Initialize UPMC RAM
*/
static void upmc_write (u_char addr, uint val)
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
out_be32 (&lbc->mdr, val);
clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
/* dummy access to perform write */
out_8 ((void __iomem *)CFG_CAN_BASE, 0);
/* normal operation */
clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
}
#endif /* CONFIG_CAN_DRIVER */
uint get_lbc_clock (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
sys_info_t sys_info;
ulong clkdiv = lbc->lcrr & 0x0f;
get_sys_info (&sys_info);
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#ifdef CONFIG_MPC8548
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider value.
*/
clkdiv *= 2;
#endif
return sys_info.freqSystemBus / clkdiv;
}
puts("Invalid clock divider value in CFG_LBC_LCRR\n");
return 0;
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
uint svr = get_svr ();
uint lcrr;
/*
* MPC revision < 2.0
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
* Modify engineering use only register at address 0xE_0F20.
* "1. Read register at offset 0xE_0F20
* 2. And value with 0x0000_FFFF
* 3. OR result with 0x0000_0004
* 4. Write result back to offset 0xE_0F20."
*
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
* Modify engineering use only register at address 0xE_0F20.
* "1. Read register at offset 0xE_0F20
* 2. And value with 0xFFFF_FFDF
* 3. Write result back to offset 0xE_0F20."
*
* Since it is the same register, we do the modification in one step.
*/
if (SVR_MAJ (svr) < 2) {
uint dummy = gur->lbiuiplldcr1;
dummy &= 0x0000FFDF;
dummy |= 0x00000004;
gur->lbiuiplldcr1 = dummy;
}
lcrr = CFG_LBC_LCRR;
/*
* Local Bus Clock > 83.3 MHz. According to timing
* specifications set LCRR[EADC] to 2 delay cycles.
*/
if (lbc_mhz > 83) {
lcrr &= ~LCRR_EADC;
lcrr |= LCRR_EADC_2;
}
/*
* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
* disable PLL bypass for Local Bus Clock > 83 MHz.
*/
if (lbc_mhz >= 66)
lcrr &= (~LCRR_DBYP); /* DLL Enabled */
else
lcrr |= LCRR_DBYP; /* DLL Bypass */
lbc->lcrr = lcrr;
asm ("sync;isync;msync");
/*
* According to MPC8548ERMAD Rev.1.3 read back LCRR
* and terminate with isync
*/
lcrr = lbc->lcrr;
asm ("isync;");
/* let DLL stabilize */
udelay (500);
#else /* !CONFIG_MPC8548 */
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
* If localbus freq is > 133Mhz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
if (lbc_mhz < 66) {
lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
lbc->ltedr = 0xa4c80000; /* DK: !!! */
} else if (lbc_mhz >= 133) {
lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
uint pvr = get_pvr ();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
udelay (200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm ("sync;isync;msync");
}
#endif /* !CONFIG_MPC8548 */
#ifdef CONFIG_CAN_DRIVER
/*
* According to timing specifications EAD must be
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
else
out_be32 (&lbc->or2, CFG_OR2_CAN);
out_be32 (&lbc->br2, CFG_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
/* Initialize UPMC for CAN: single read */
upmc_write (0x00, 0xFFFFED00);
upmc_write (0x01, 0xCCFFCC00);
upmc_write (0x02, 0x00FFCF00);
upmc_write (0x03, 0x00FFCF00);
upmc_write (0x04, 0x00FFDC00);
upmc_write (0x05, 0x00FFCF00);
upmc_write (0x06, 0x00FFED00);
upmc_write (0x07, 0x3FFFCC07);
/* Initialize UPMC for CAN: single write */
upmc_write (0x18, 0xFFFFED00);
upmc_write (0x19, 0xCCFFEC00);
upmc_write (0x1A, 0x00FFED80);
upmc_write (0x1B, 0x00FFED80);
upmc_write (0x1C, 0x00FFFC00);
upmc_write (0x1D, 0x0FFFEC00);
upmc_write (0x1E, 0x0FFFEF00);
upmc_write (0x1F, 0x3FFFEC05);
#endif /* CONFIG_CAN_DRIVER */
}
/*
* Initialize PCI Devices, report devices found.
*/
static int first_free_busno;
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI || CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
static inline void init_pci1(void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
/* PORDEVSR[15] */
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
/* PORDEVSR[14] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
/* PORPLLSR[16] */
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
uint pci_agent = (host_agent == 3) || (host_agent == 4 ) ||
(host_agent == 6);
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333333) ? "33" :
(pci_speed == 66666666) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
/* inbound */
pci_set_region (hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region (hose->regions + 1,
CFG_PCI1_MEM_BASE,
CFG_PCI1_MEM_PHYS,
CFG_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region (hose->regions + 2,
CFG_PCI1_IO_BASE,
CFG_PCI1_IO_PHYS,
CFG_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->first_busno = first_free_busno;
pci_setup_indirect (hose, (int)&pci->cfg_addr,
(int)&pci->cfg_data);
fsl_pci_init (hose);
printf (" PCI on bus %02x..%02x\n",
hose->first_busno, hose->last_busno);
first_free_busno = hose->last_busno + 1;
#ifdef CONFIG_PCIX_CHECK
if (!(gur->pordevsr & PORDEVSR_PCI)) {
ushort reg16 =
PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
uint dev = PCI_BDF(hose->first_busno, 0, 0);
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
puts ("PCI-X will only work at 66 MHz\n");
pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
reg16);
}
#endif
} else {
puts ("PCI1: disabled\n");
}
#else /* !(CONFIG_PCI || CONFIG_PCI1) */
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif /* CONFIG_PCI || CONFIG_PCI1) */
}
static inline void init_pcie1(void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCIE1
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
(host_agent == 3);
int pcie_configured = io_sel >= 1;
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("PCIe: %s, base address %x",
pcie_ep ? "End point" : "Root complex", (uint)pci);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug (", with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
puts ("\n");
/* inbound */
pci_set_region (hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
pci_set_region (hose->regions + 1,
CFG_PCIE1_MEM_BASE,
CFG_PCIE1_MEM_PHYS,
CFG_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region (hose->regions + 2,
CFG_PCIE1_IO_BASE,
CFG_PCIE1_IO_PHYS,
CFG_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
(int)&pci->cfg_data);
fsl_pci_init (hose);
printf (" PCIe on bus %02x..%02x\n",
hose->first_busno, hose->last_busno);
first_free_busno = hose->last_busno + 1;
} else {
printf ("PCIe: disabled\n");
}
#else /* !CONFIG_PCIE1 */
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif /* CONFIG_PCIE1 */
}
void pci_init_board (void)
{
init_pci1();
init_pcie1();
}
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup (void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
ft_cpu_setup (blob, bd);
node = fdt_path_offset (blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
path = fdt_getprop (blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
}
#endif /* CONFIG_PCI || CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
path = fdt_getprop (blob, node, "pci1", NULL);
if (path) {
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
}
#endif /* CONFIG_PCIE1 */
}
}
#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
ps2mult_early_init ();
#endif /* CONFIG_PS2MULT */
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */

0
board/tqm85xx/u-boot.lds → board/tqc/tqm85xx/u-boot.lds
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board/tqm8xx/Makefile → board/tqc/tqm8xx/Makefile
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board/tqm8xx/config.mk → board/tqc/tqm8xx/config.mk
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board/tqm8xx/flash.c → board/tqc/tqm8xx/flash.c
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board/tqm8xx/load_sernum_ethaddr.c → board/tqc/tqm8xx/load_sernum_ethaddr.c
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board/tqm8xx/tqm8xx.c → board/tqc/tqm8xx/tqm8xx.c
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board/tqm8xx/u-boot.lds → board/tqc/tqm8xx/u-boot.lds
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board/tqm8xx/u-boot.lds.debug → board/tqc/tqm8xx/u-boot.lds.debug
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54
board/tqm85xx/law.c
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@ -1,54 +0,0 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

223
board/tqm85xx/sdram.c
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@ -1,223 +0,0 @@
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <asm/mmu.h>
struct sdram_conf_s {
unsigned long size;
unsigned long reg;
};
typedef struct sdram_conf_s sdram_conf_t;
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
{(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
};
#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
int cas_latency(void);
/*
* Autodetect onboard DDR SDRAM on 85xx platforms
*
* NOTE: Some of the hardcoded values are hardware dependant,
* so this should be extended for other future boards
* using this routine!
*/
long int sdram_setup(int casl)
{
int i;
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
/*
* Disable memory controller.
*/
ddr->cs0_config = 0;
ddr->sdram_cfg = 0;
switch (casl) {
case 20:
cfg_ddr_timing1 = 0x47405331 | (3 << 16);
cfg_ddr_mode = 0x40020002 | (2 << 4);
break;
case 25:
cfg_ddr_timing1 = 0x47405331 | (4 << 16);
cfg_ddr_mode = 0x40020002 | (6 << 4);
break;
case 30:
default:
cfg_ddr_timing1 = 0x47405331 | (5 << 16);
cfg_ddr_mode = 0x40020002 | (3 << 4);
break;
}
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
ddr->timing_cfg_1 = cfg_ddr_timing1;
ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
ddr->sdram_mode = cfg_ddr_mode;
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
ddr->err_disable = 0x0000000D;
asm ("sync;isync;msync");
udelay(1000);
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
asm ("sync; isync; msync");
udelay(1000);
for (i=0; i<N_DDR_CS_CONF; i++) {
ddr->cs0_config = ddr_cs_conf[i].reg;
if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
/*
* OK, size detected -> all done
*/
return ddr_cs_conf[i].size;
}
}
return 0; /* nothing found ! */
}
void board_add_ram_info(int use_default)
{
int casl;
if (use_default)
casl = CONFIG_DDR_DEFAULT_CL;
else
casl = cas_latency();
puts(" (CL=");
switch (casl) {
case 20:
puts("2)");
break;
case 25:
puts("2.5)");
break;
case 30:
puts("3)");
break;
}
}
long int initdram (int board_type)
{
long dram_size = 0;
int casl;
#if defined(CONFIG_DDR_DLL)
/*
* This DLL-Override only used on TQM8540 and TQM8560
*/
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
int i,x;
x = 10;
/*
* Work around to stabilize DDR DLL
*/
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay (200);
while (gur->ddrdllcr != 0x81000100) {
gur->devdisr = gur->devdisr | 0x00010000;
asm("sync;isync;msync");
for (i=0; i<x; i++)
;
gur->devdisr = gur->devdisr & 0xfff7ffff;
asm("sync;isync;msync");
x++;
}
}
#endif
casl = cas_latency();
dram_size = sdram_setup(casl);
if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
/*
* Try again with default CAS latency
*/
puts("Problem with CAS lantency");
board_add_ram_info(1);
puts(", using default CL!\n");
casl = CONFIG_DDR_DEFAULT_CL;
dram_size = sdram_setup(casl);
puts(" ");
}
return dram_size;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *p;
printf ("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf ("SDRAM test passed.\n");
return 0;
}
#endif

114
board/tqm85xx/tlb.c
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@ -1,114 +0,0 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
* Out of reset this entry is only 4K.
*/
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

419
board/tqm85xx/tqm85xx.c
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@ -1,419 +0,0 @@
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2002,2003, Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <flash.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
#ifdef CONFIG_CPM2
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
/* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
#endif /* CONFIG_CPM2 */
#define CASL_STRING1 "casl=xx"
#define CASL_STRING2 "casl="
static const int casl_table[] = { 20, 25, 30 };
#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
int cas_latency(void)
{
char *s = getenv("serial#");
int casl;
int val;
int i;
casl = CONFIG_DDR_DEFAULT_CL;
if (s != NULL) {
if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
strlen(CASL_STRING2)) == 0) {
val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
for (i=0; i<N_CASL; ++i) {
if (val == casl_table[i]) {
return val;
}
}
}
}
return casl;
}
int checkboard (void)
{
char *s = getenv("serial#");
printf("Board: %s", CONFIG_BOARDNAME);
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
printf ("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/*
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
}
/*
* Check if only one FLASH bank is available
*/
if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
memctl->or1 = 0;
memctl->br1 = 0;
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
}
return 0;
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
uint clkdiv;
uint lbc_hz;
sys_info_t sysinfo;
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
* If localbus freq is > 133Mhz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
get_sys_info (&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
lbc->ltedr = 0xa4c80000; /* DK: !!! */
} else if (lbc_hz >= 133) {
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
uint pvr = get_pvr ();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
udelay (200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm ("sync;isync;msync");
}
}
#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
PCI_ENET0_MEMADDR,
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER}},
{}
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table:pci_mpc85xxads_config_table,
#endif
};
#endif /* CONFIG_PCI */
void pci_init_board (void)
{
#ifdef CONFIG_PCI
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */

154
cpu/mpc85xx/cpu.c
View File

@ -29,42 +29,46 @@
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
struct cpu_type {
char name[15];
u32 soc_ver;
};
#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8533),
CPU_TYPE_ENTRY(8533_E),
CPU_TYPE_ENTRY(8540),
CPU_TYPE_ENTRY(8541),
CPU_TYPE_ENTRY(8541_E),
CPU_TYPE_ENTRY(8543),
CPU_TYPE_ENTRY(8543_E),
CPU_TYPE_ENTRY(8544),
CPU_TYPE_ENTRY(8544_E),
CPU_TYPE_ENTRY(8545),
CPU_TYPE_ENTRY(8545_E),
CPU_TYPE_ENTRY(8547_E),
CPU_TYPE_ENTRY(8548),
CPU_TYPE_ENTRY(8548_E),
CPU_TYPE_ENTRY(8555),
CPU_TYPE_ENTRY(8555_E),
CPU_TYPE_ENTRY(8560),
CPU_TYPE_ENTRY(8567),
CPU_TYPE_ENTRY(8567_E),
CPU_TYPE_ENTRY(8568),
CPU_TYPE_ENTRY(8568_E),
CPU_TYPE_ENTRY(8572),
CPU_TYPE_ENTRY(8572_E),
CPU_TYPE_ENTRY(8533, 8533),
CPU_TYPE_ENTRY(8533, 8533_E),
CPU_TYPE_ENTRY(8540, 8540),
CPU_TYPE_ENTRY(8541, 8541),
CPU_TYPE_ENTRY(8541, 8541_E),
CPU_TYPE_ENTRY(8543, 8543),
CPU_TYPE_ENTRY(8543, 8543_E),
CPU_TYPE_ENTRY(8544, 8544),
CPU_TYPE_ENTRY(8544, 8544_E),
CPU_TYPE_ENTRY(8545, 8545),
CPU_TYPE_ENTRY(8545, 8545_E),
CPU_TYPE_ENTRY(8547, 8547_E),
CPU_TYPE_ENTRY(8548, 8548),
CPU_TYPE_ENTRY(8548, 8548_E),
CPU_TYPE_ENTRY(8555, 8555),
CPU_TYPE_ENTRY(8555, 8555_E),
CPU_TYPE_ENTRY(8560, 8560),
CPU_TYPE_ENTRY(8567, 8567),
CPU_TYPE_ENTRY(8567, 8567_E),
CPU_TYPE_ENTRY(8568, 8568),
CPU_TYPE_ENTRY(8568, 8568_E),
CPU_TYPE_ENTRY(8572, 8572),
CPU_TYPE_ENTRY(8572, 8572_E),
};
struct cpu_type *identify_cpu(uint ver)
{
int i;
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if (cpu_type_list[i].soc_ver == ver)
return &cpu_type_list[i];
return NULL;
}
int checkcpu (void)
{
sys_info_t sysinfo;
@ -74,9 +78,13 @@ int checkcpu (void)
uint fam;
uint ver;
uint major, minor;
int i;
u32 ddr_ratio;
struct cpu_type *cpu;
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
#else
u32 ddr_ratio = 0;
#endif
svr = get_svr();
ver = SVR_SOC_VER(svr);
@ -85,14 +93,15 @@ int checkcpu (void)
puts("CPU: ");
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if (cpu_type_list[i].soc_ver == ver) {
puts(cpu_type_list[i].name);
break;
}
cpu = identify_cpu(ver);
if (cpu) {
puts(cpu->name);
if (i == ARRAY_SIZE(cpu_type_list))
if (svr & 0x80000)
puts("E");
} else {
puts("Unknown");
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
@ -118,7 +127,7 @@ int checkcpu (void)
puts("Clock Configuration:\n");
printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
@ -159,7 +168,7 @@ int checkcpu (void)
}
#ifdef CONFIG_CPM2
printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
#endif
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
@ -279,3 +288,68 @@ int dma_xfer(void *dest, uint count, void *src) {
return dma_check();
}
#endif
/*
* Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF)
* are hardcoded as "1"."size" is the number or entries, not a sizeof.
*/
void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
int loopval = 0x00004440;
volatile u32 *brp,*orp;
volatile u8* dummy = NULL;
int upmmask;
switch (upm) {
case UPMA:
mxmr = &lbc->mamr;
upmmask = BR_MS_UPMA;
break;
case UPMB:
mxmr = &lbc->mbmr;
upmmask = BR_MS_UPMB;
break;
case UPMC:
mxmr = &lbc->mcmr;
upmmask = BR_MS_UPMC;
break;
default:
printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
hang();
}
/* Find the address for the dummy write transaction */
for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
break;
}
}
if (i == 8) {
printf("Error: %s() could not find matching BR\n", __FUNCTION__);
hang();
}
for (i = 0; i < size; i++) {
/* 1 */
out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */
/* 2 */
out_be32(&lbc->mdr, table[i]);
/* 3 */
mdr = in_be32(&lbc->mdr);
/* 4 */
*(volatile u8 *)dummy = 0;
/* 5 */
do {
mad = in_be32(mxmr) & 0x3f;
} while (mad <= old_mad && !(!mad && i == (size-1)));
old_mad = mad;
}
out_be32(mxmr, loopval); /* OP_NORMAL */
}

39
cpu/mpc85xx/cpu_init.c
View File

@ -148,6 +148,12 @@ void cpu_init_early_f(void)
}
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
init_laws();
invalidate_tlb(0);
init_tlbs();
@ -168,12 +174,6 @@ void cpu_init_f (void)
disable_tlb(14);
disable_tlb(15);
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#ifdef CONFIG_CPM2
config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR);
#endif
@ -254,16 +254,7 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
#ifdef CONFIG_CLEAR_LAW0
#ifdef CONFIG_FSL_LAW
disable_law(0);
#else
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#endif
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
@ -281,17 +272,17 @@ int cpu_init_r(void)
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
ver == SVR_8544 || ver == SVR_8568_E) {
printf ("L2 cache 512KB:");
puts ("512 KB ");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
} else {
printf ("L2 cache 256KB:");
puts("256 KB ");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
cache_ctl = 0xc8000000;
}
break;
case 0x10000000:
printf ("L2 cache 256KB:");
puts("256 KB ");
if (ver == SVR_8544 || ver == SVR_8544_E) {
cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
}
@ -299,18 +290,18 @@ int cpu_init_r(void)
case 0x30000000:
case 0x00000000:
default:
printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
printf(" unknown size (0x%08x)\n", cache_ctl);
return -1;
}
if (l2cache->l2ctl & 0x80000000) {
printf(" already enabled.");
puts("already enabled");
l2srbar = l2cache->l2srbar0;
#ifdef CFG_INIT_L2_ADDR
if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
l2srbar = CFG_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
printf("moving to 0x%08x", CFG_INIT_L2_ADDR);
}
#endif /* CFG_INIT_L2_ADDR */
puts("\n");
@ -318,10 +309,10 @@ int cpu_init_r(void)
asm("msync;isync");
l2cache->l2ctl = cache_ctl; /* invalidate & enable */
asm("msync;isync");
printf(" enabled\n");
puts("enabled\n");
}
#else
printf("L2 cache: disabled\n");
puts("disabled\n");
#endif
#ifdef CONFIG_QE
uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */

128
cpu/mpc85xx/fdt.c
View File

@ -26,6 +26,7 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
extern void ft_qe_setup(void *blob);
#ifdef CONFIG_MP
@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
}
#endif
#ifdef CONFIG_L2_CACHE
/* return size in kilobytes */
static inline u32 l2cache_size(void)
{
volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
u32 ver = SVR_SOC_VER(get_svr());
switch (l2siz_field) {
case 0x0:
break;
case 0x1:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E)
return 128;
else
return 256;
break;
case 0x2:
if (ver == SVR_8540 || ver == SVR_8560 ||
ver == SVR_8541 || ver == SVR_8541_E ||
ver == SVR_8555 || ver == SVR_8555_E)
return 256;
else
return 512;
break;
case 0x3:
return 1024;
break;
}
return 0;
}
static inline void ft_fixup_l2cache(void *blob)
{
int len, off;
u32 *ph;
struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
char compat_buf[38];
const u32 line_size = 32;
const u32 num_ways = 8;
const u32 size = l2cache_size() * 1024;
const u32 num_sets = size / (line_size * num_ways);
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
if (off < 0) {
debug("no cpu node fount\n");
return;
}
ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
if (ph == NULL) {
debug("no next-level-cache property\n");
return ;
}
off = fdt_node_offset_by_phandle(blob, *ph);
if (off < 0) {
printf("%s: %s\n", __func__, fdt_strerror(off));
return ;
}
if (cpu) {
len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
cpu->name);
sprintf(&compat_buf[len + 1], "cache");
}
fdt_setprop(blob, off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, off, "cache-block-size", line_size);
fdt_setprop_cell(blob, off, "cache-line-size", line_size);
fdt_setprop_cell(blob, off, "cache-size", size);
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
}
#else
#define ft_fixup_l2cache(x)
#endif
static inline void ft_fixup_cache(void *blob)
{
int off;
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
u32 l1cfg0 = mfspr(SPRN_L1CFG0);
u32 l1cfg1 = mfspr(SPRN_L1CFG1);
u32 isize, iline_size, inum_sets, inum_ways;
u32 dsize, dline_size, dnum_sets, dnum_ways;
/* d-side config */
dsize = (l1cfg0 & 0x7ff) * 1024;
dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
dnum_sets = dsize / (dline_size * dnum_ways);
fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
fdt_setprop_cell(blob, off, "d-cache-size", dsize);
fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
/* i-side config */
isize = (l1cfg1 & 0x7ff) * 1024;
inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
inum_sets = isize / (iline_size * inum_ways);
fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
fdt_setprop_cell(blob, off, "i-cache-size", isize);
fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
off = fdt_node_offset_by_prop_value(blob, off,
"device_type", "cpu", 4);
}
ft_fixup_l2cache(blob);
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_MP
ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
#endif
ft_fixup_cache(blob);
}

2
cpu/mpc85xx/spd_sdram.c
View File

@ -1090,7 +1090,7 @@ setup_laws_and_tlbs(unsigned int memsize)
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
#endif
/*

8
cpu/mpc85xx/traps.c
View File

@ -50,10 +50,12 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0;
extern unsigned long search_exception_table(unsigned long);
/*
* End of memory as shown by board info and determined by DDR setup.
* End of addressable memory. This may be less than the actual
* amount of memory on the system if we're unable to keep all
* the memory mapped in.
*/
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
extern ulong get_effective_memsize(void);
#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
static __inline__ void set_tsr(unsigned long val)
{

3
cpu/mpc86xx/cpu_init.c
View File

@ -119,8 +119,5 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
#ifdef CONFIG_FSL_LAW
disable_law(0);
#endif
return 0;
}

6
cpu/mpc86xx/spd_sdram.c
View File

@ -1183,7 +1183,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 1 space.
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
#endif
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
@ -1238,7 +1238,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 1 space.
*/
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
#endif
}
@ -1265,7 +1265,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 2 space.
*/
#ifdef CONFIG_FSL_LAW
set_law(8,
set_next_law(
(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
law_size_ddr2, LAW_TRGT_IF_DDR_2);
#endif

31
drivers/input/ps2ser.c
View File

@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CFG_CCSRBAR+0x4500)
@ -65,7 +66,9 @@ static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
extern struct serial_state rs_table[]; /* in serial.c */
#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \
!defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \
!defined(CONFIG_MPC8555)
static struct serial_state *state;
#endif
@ -120,7 +123,8 @@ int ps2ser_init(void)
return (0);
}
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
int ps2ser_init(void)
{
NS16550_t com_port = (NS16550_t)COM_BASE;
@ -186,7 +190,8 @@ void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
#ifdef DEBUG
@ -197,7 +202,8 @@ void ps2ser_putc(int chr)
while (!(psc->psc_status & PSC_SR_TXRDY));
psc->psc_buffer_8 = chr;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
while ((com_port->lsr & LSR_THRE) == 0);
com_port->thr = chr;
#else
@ -211,7 +217,8 @@ static int ps2ser_getc_hw(void)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int res = -1;
@ -220,7 +227,8 @@ static int ps2ser_getc_hw(void)
if (psc->psc_status & PSC_SR_RXRDY) {
res = (psc->psc_buffer_8);
}
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
if (com_port->lsr & LSR_DR) {
res = com_port->rbr;
}
@ -279,7 +287,8 @@ static void ps2ser_interrupt(void *dev_id)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int chr;
@ -289,7 +298,8 @@ static void ps2ser_interrupt(void *dev_id)
chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
status = psc->psc_status;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
status = com_port->lsr;
#else
status = ps2ser_in(UART_IIR);
@ -305,7 +315,8 @@ static void ps2ser_interrupt(void *dev_id)
}
#ifdef CONFIG_MPC5xxx
} while (status & PSC_SR_RXRDY);
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555)
} while (status & LSR_DR);
#else
} while (status & UART_IIR_RDI);

65
drivers/misc/fsl_law.c
View File

@ -27,8 +27,22 @@
#include <asm/fsl_law.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define LAWAR_EN 0x80000000
#define FSL_HW_NUM_LAWS 10 /* number of LAWs in the hw implementation */
/* number of LAWs in the hw implementation */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
#define FSL_HW_NUM_LAWS 8
#elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
defined(CONFIG_MPC8568) || \
defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
#define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8572)
#define FSL_HW_NUM_LAWS 12
#else
#error FSL_HW_NUM_LAWS not defined for this platform
#endif
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
@ -36,18 +50,53 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
gd->used_laws |= (1 << idx);
out_be32(lawbar, addr >> 12);
out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
return ;
}
int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx = ffz(gd->used_laws);
if (idx >= FSL_HW_NUM_LAWS)
return -1;
set_law(idx, addr, sz, id);
return idx;
}
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
/* we have no LAWs free */
if (gd->used_laws == -1)
return -1;
/* grab the last free law */
idx = __ilog2(~(gd->used_laws));
if (idx >= FSL_HW_NUM_LAWS)
return -1;
set_law(idx, addr, sz, id);
return idx;
}
void disable_law(u8 idx)
{
volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
gd->used_laws &= ~(1 << idx);
out_be32(lawar, 0);
out_be32(lawbar, 0);
@ -75,14 +124,16 @@ void print_laws(void)
void init_laws(void)
{
int i;
u8 law_idx = 0;
gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index != -1)
law_idx = law_table[i].index;
set_law(law_idx++, law_table[i].addr,
law_table[i].size, law_table[i].trgt_id);
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
law_table[i].trgt_id);
else
set_law(law_table[i].index, law_table[i].addr,
law_table[i].size, law_table[i].trgt_id);
}
return ;

138
drivers/mtd/nand/fsl_upm.c
View File

@ -20,102 +20,56 @@
#include <linux/mtd/fsl_upm.h>
#include <nand.h>
#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */
#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */
#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */
#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */
static int fsl_upm_in_pattern;
static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
{
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset);
clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
}
static void fsl_upm_end_pattern(struct fsl_upm *upm)
{
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
eieio();
}
static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
{
out_be32(upm->mar, cmd << (32 - width * 8));
out_8(upm->io_addr, 0x0);
}
static void fsl_upm_setup(struct fsl_upm *upm)
{
int i;
/* write upm array */
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);
for (i = 0; i < 64; i++) {
out_be32(upm->mdr, upm->array[i]);
out_be32(upm->mar, cmd << (32 - width));
switch (width) {
case 8:
out_8(upm->io_addr, 0x0);
break;
case 16:
out_be16(upm->io_addr, 0x0);
break;
case 32:
out_be32(upm->io_addr, 0x0);
break;
}
/* normal operation */
out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO);
while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO)
eieio();
}
static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column,
int page_addr)
static void nand_hwcontrol (struct mtd_info *mtd, int cmd)
{
struct nand_chip *chip = mtd->priv;
struct fsl_upm_nand *fun = chip->priv;
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
if (command == NAND_CMD_SEQIN) {
int readcmd;
if (column >= mtd->oobblock) {
/* OOB area */
column -= mtd->oobblock;
readcmd = NAND_CMD_READOOB;
} else if (column < 256) {
/* First 256 bytes --> READ0 */
readcmd = NAND_CMD_READ0;
} else {
column -= 256;
readcmd = NAND_CMD_READ1;
}
fsl_upm_run_pattern(&fun->upm, fun->width, readcmd);
}
fsl_upm_run_pattern(&fun->upm, fun->width, command);
fsl_upm_end_pattern(&fun->upm);
fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
if (column != -1)
fsl_upm_run_pattern(&fun->upm, fun->width, column);
if (page_addr != -1) {
fsl_upm_run_pattern(&fun->upm, fun->width, page_addr);
fsl_upm_run_pattern(&fun->upm, fun->width,
(page_addr >> 8) & 0xFF);
if (chip->chipsize > (32 << 20)) {
fsl_upm_run_pattern(&fun->upm, fun->width,
(page_addr >> 16) & 0x0f);
}
}
fsl_upm_end_pattern(&fun->upm);
if (fun->wait_pattern) {
/*
* Some boards/chips needs this. At least on MPC8360E-RDK we
* need it. Probably weird chip, because I don't see any need
* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
* 0-2 unexpected busy states per block read.
*/
while (!fun->dev_ready())
debug("unexpected busy state\n");
switch (cmd) {
case NAND_CTL_SETCLE:
fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
fsl_upm_in_pattern++;
break;
case NAND_CTL_SETALE:
fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
fsl_upm_in_pattern++;
break;
case NAND_CTL_CLRCLE:
case NAND_CTL_CLRALE:
fsl_upm_end_pattern(&fun->upm);
fsl_upm_in_pattern--;
break;
}
}
@ -123,7 +77,24 @@ static void nand_write_byte(struct mtd_info *mtd, u_char byte)
{
struct nand_chip *chip = mtd->priv;
out_8(chip->IO_ADDR_W, byte);
if (fsl_upm_in_pattern) {
struct fsl_upm_nand *fun = chip->priv;
fsl_upm_run_pattern(&fun->upm, fun->width, byte);
/*
* Some boards/chips needs this. At least on MPC8360E-RDK we
* need it. Probably weird chip, because I don't see any need
* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
* 0-2 unexpected busy states per block read.
*/
if (fun->wait_pattern) {
while (!fun->dev_ready())
debug("unexpected busy state\n");
}
} else {
out_8(chip->IO_ADDR_W, byte);
}
}
static u8 nand_read_byte(struct mtd_info *mtd)
@ -164,10 +135,6 @@ static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
return 0;
}
static void nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
}
static int nand_dev_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
@ -178,23 +145,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
{
/* yet only 8 bit accessors implemented */
if (fun->width != 1)
if (fun->width != 8 && fun->width != 16 && fun->width != 32)
return -ENOSYS;
fsl_upm_setup(&fun->upm);
chip->priv = fun;
chip->chip_delay = fun->chip_delay;
chip->eccmode = NAND_ECC_SOFT;
chip->cmdfunc = fun_cmdfunc;
chip->hwcontrol = nand_hwcontrol;
chip->read_byte = nand_read_byte;
chip->read_buf = nand_read_buf;
chip->write_byte = nand_write_byte;
chip->write_buf = nand_write_buf;
chip->verify_buf = nand_verify_buf;
chip->dev_ready = nand_dev_ready;
if (fun->dev_ready)
chip->dev_ready = nand_dev_ready;
return 0;
}

46
drivers/mtd/nand/nand_base.c
View File

@ -113,18 +113,22 @@ static struct nand_oobinfo nand_oob_64 = {
.oobfree = { {2, 38} }
};
/* This is used for padding purposes in nand_write_oob */
static u_char ffchars[] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
static struct nand_oobinfo nand_oob_128 = {
.useecc = MTD_NANDECC_AUTOPLACE,
.eccbytes = 48,
.eccpos = {
80, 81, 82, 83, 84, 85, 86, 87,
88, 89, 90, 91, 92, 93, 94, 95,
96, 97, 98, 99, 100, 101, 102, 103,
104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123, 124, 125, 126, 127},
.oobfree = { {2, 78} }
};
/* This is used for padding purposes in nand_write_oob */
static u_char *ffchars;
/*
* NAND low-level MTD interface functions
*/
@ -193,6 +197,10 @@ static void nand_release_device (struct mtd_info *mtd)
{
struct nand_chip *this = mtd->priv;
this->select_chip(mtd, -1); /* De-select the NAND device */
if (ffchars) {
kfree(ffchars);
ffchars = NULL;
}
}
#endif
@ -891,7 +899,7 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa
u_char *oob_buf, struct nand_oobinfo *oobsel, int cached)
{
int i, status;
u_char ecc_code[32];
u_char ecc_code[NAND_MAX_OOBSIZE];
int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
uint *oob_config = oobsel->eccpos;
int datidx = 0, eccidx = 0, eccsteps = this->eccsteps;
@ -1112,8 +1120,8 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0;
struct nand_chip *this = mtd->priv;
u_char *data_poi, *oob_data = oob_buf;
u_char ecc_calc[32];
u_char ecc_code[32];
u_char ecc_calc[NAND_MAX_OOBSIZE];
u_char ecc_code[NAND_MAX_OOBSIZE];
int eccmode, eccsteps;
unsigned *oob_config;
int datidx;
@ -1811,6 +1819,15 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t *
if (NAND_MUST_PAD(this)) {
/* Write out desired data */
this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask);
if (!ffchars) {
if (!(ffchars = kmalloc (mtd->oobsize, GFP_KERNEL))) {
DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
"No memory for padding array, need %d bytes", mtd->oobsize);
ret = -ENOMEM;
goto out;
}
memset(ffchars, 0xff, mtd->oobsize);
}
/* prepad 0xff for partial programming */
this->write_buf(mtd, ffchars, column);
/* write data */
@ -2479,6 +2496,9 @@ int nand_scan (struct mtd_info *mtd, int maxchips)
case 64:
this->autooob = &nand_oob_64;
break;
case 128:
this->autooob = &nand_oob_128;
break;
default:
printk (KERN_WARNING "No oob scheme defined for oobsize %d\n",
mtd->oobsize);

5
include/asm-ppc/fsl_law.h
View File

@ -6,6 +6,9 @@
#define SET_LAW_ENTRY(idx, a, sz, trgt) \
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
#define SET_LAW(a, sz, trgt) \
{ .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
enum law_size {
LAW_SIZE_4K = 0xb,
LAW_SIZE_8K,
@ -70,6 +73,8 @@ struct law_entry {
};
extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
extern void disable_law(u8 idx);
extern void init_laws(void);
extern void print_laws(void);

47
include/asm-ppc/fsl_lbc.h
View File

@ -59,6 +59,10 @@
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define UPMA 0
#define UPMB 1
#define UPMC 2
#if defined(CONFIG_MPC834X)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#else
@ -161,11 +165,6 @@
#define OR_UPM_EAD 0x00000001
#define OR_UPM_EAD_SHIFT 0
#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
#define MxMR_OP_WARR 0x10000000 /* Write to Array */
#define MxMR_BSEL 0x80000000 /* Bus Select */
#define OR_SDRAM_AM 0xFFFF8000
#define OR_SDRAM_AM_SHIFT 15
#define OR_SDRAM_XAM 0x00006000
@ -198,6 +197,44 @@
#define OR_AM_2GB 0x80000000
#define OR_AM_4GB 0x00000000
/* MxMR - UPM Machine A/B/C Mode Registers
*/
#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
#define MxMR_OP_WARR 0x10000000 /* Write to Array */
#define MxMR_OP_RARR 0x20000000 /* Read from Array */
#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
#define MxMR_RFEN 0x40000000 /* Refresh Enable */
#define MxMR_BSEL 0x80000000 /* Bus Select */
#define LBLAWAR_EN 0x80000000
#define LBLAWAR_4KB 0x0000000B
#define LBLAWAR_8KB 0x0000000C

3
include/asm-ppc/global_data.h
View File

@ -96,6 +96,9 @@ typedef struct global_data {
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
#if defined(CONFIG_FSL_LAW)
u32 used_laws;
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;

36
include/asm-ppc/io.h
View File

@ -238,6 +238,42 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val)
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
/* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
* specifying the mask in the 'clear' parameter and the new bit pattern
* in the 'set' parameter.
*/
#define clrbits(type, addr, clear) \
out_##type((addr), in_##type(addr) & ~(clear))
#define setbits(type, addr, set) \
out_##type((addr), in_##type(addr) | (set))
#define clrsetbits(type, addr, clear, set) \
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
#define setbits_be32(addr, set) setbits(be32, addr, set)
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching

11
include/asm-ppc/processor.h
View File

@ -960,6 +960,17 @@ n:
#define SR15 15
#ifndef __ASSEMBLY__
struct cpu_type {
char name[15];
u32 soc_ver;
};
struct cpu_type *identify_cpu(uint ver);
#define CPU_TYPE_ENTRY(n, v) \
{ .name = #n, .soc_ver = SVR_##v, }
#ifndef CONFIG_MACH_SPECIFIC
extern int _machine;
extern int have_of;

3
include/configs/MPC8540ADS.h
View File

@ -87,9 +87,6 @@
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000

3
include/configs/MPC8541CDS.h
View File

@ -73,9 +73,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000

6
include/configs/MPC8544DS.h
View File

@ -77,19 +77,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#define CFG_ALT_MEMTEST
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
@ -171,6 +166,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */

3
include/configs/MPC8548CDS.h
View File

@ -87,9 +87,6 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000

3
include/configs/MPC8555CDS.h
View File

@ -73,9 +73,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000

4
include/configs/MPC8560ADS.h
View File

@ -40,6 +40,7 @@
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
#define CONFIG_MPC8560 1
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
@ -80,11 +81,8 @@
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000

1
include/configs/MPC8568MDS.h
View File

@ -80,7 +80,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000

1
include/configs/SBC8540.h
View File

@ -49,6 +49,7 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
#define CONFIG_MPC8540 1
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */

382
include/configs/TQM85xx.h
View File

@ -1,4 +1,7 @@
/*
* (C) Copyright 2007
* Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
@ -27,7 +30,7 @@
*/
/*
* TQM85xx (8560/40/55/41) board configuration file
* TQM85xx (8560/40/55/41/48) board configuration file
*/
#ifndef __CONFIG_H
@ -39,25 +42,53 @@
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
#define CONFIG_PCI
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
#ifdef CONFIG_TQM8548
#define CONFIG_PCI1
#define CONFIG_PCIE1
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
/*
* Only MPC8540 doesn't have CPM module
/*
* Configuration for big NOR Flashes
*
* Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
* Please be aware, that this changes the whole memory map (new CCSRBAR
* address, etc). You have to use an adapted Linux kernel or FDT blob
* if this option is set.
*/
#ifndef CONFIG_MPC8540
#undef CONFIG_TQM_BIGFLASH
/*
* NAND flash support (disabled by default)
*
* Warning: NAND support will likely increase the U-Boot image size
* to more than 256 KB. Please adjust TEXT_BASE if necessary.
*/
#undef CONFIG_NAND
/*
* MPC8540 and MPC8548 don't have CPM module
*/
#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
#define CONFIG_CPM2 1 /* has CPM2 */
#endif
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#undef CONFIG_CAN_DRIVER /* CAN Driver support */
/*
* sysclk for MPC85xx
*
* Two valid values are:
* 33000000
* 66000000
* 33333333
* 66666666
*
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
* is likely the desired value here, so that is now the default.
@ -88,10 +119,18 @@
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_CCSRBAR 0xA0000000 /* relocated CCSRBAR */
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_PCI1_ADDR (CFG_CCSRBAR + 0x8000)
#define CFG_PCI2_ADDR (CFG_CCSRBAR + 0x9000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR + 0xa000)
/*
* DDR Setup
*/
@ -102,65 +141,116 @@
/* TQM8540 & 8560 need DLL-override */
#define CONFIG_DDR_DLL /* DLL fix needed */
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
defined(CONFIG_TQM8548)
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
/*
* Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
* series while new boards have 'N' type Flashes from the S29GLxxxN
* series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
*/
#ifdef CONFIG_TQM8548
#define CONFIG_TQM_FLASH_N_TYPE
#endif /* CONFIG_TQM8548 */
/*
* Flash on the Local Bus
*/
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_FLASH0 0xE0000000
#define CFG_FLASH1 0xC0000000
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_FLASH0 0xFC000000
#define CFG_FLASH1 0xF8000000
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
*
* Note: According to timing specifications external addr latch delay
* (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
*
* For other Local Bus Clocks see following table:
*
* Clock/MHz CFG_ORx_PRELIM
* 166 0x.....CA5
* 133 0x.....C85
* 100 0x.....C65
* 83 0x.....FA2
* 66 0x.....C82
* 50 0x.....C60
* 42 0x.....040
* 33 0x.....030
* 25 0x.....020
*
*/
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_BR0_PRELIM 0xE0001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xE0000040 /* 512MB Flash */
#define CFG_BR1_PRELIM 0xC0001801 /* port size 32bit */
#define CFG_OR1_PRELIM 0xE0000040 /* 512MB Flash */
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_FLASH_CFI /* flash is CFI compat. */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_CFI /* flash is CFI compat. */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
/*
* Note: when changing the Local Bus clock divider you have to
* change the timing values in CFG_ORx_PRELIM.
*
* LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
* LCRR[16:17] EADC : External address delay cycles. It should be set to 2
* for Local Bus Clock > 83.3 MHz.
*/
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_ADDR (CFG_CCSRBAR \
+ 0x04010000) /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
#define CFG_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */
#define CFG_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
/* Serial Port */
#if defined(CONFIG_TQM8560)
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
#else /* ! TQM8560 */
#else /* !CONFIG_TQM8560 */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
@ -173,20 +263,18 @@
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* PS/2 Keyboard */
#if !defined(CONFIG_TQM8560)
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
#define CONFIG_BOARD_EARLY_INIT_R 1
#endif /* !CONFIG_TQM8560 */
#endif /* CONFIG_TQM8560 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
@ -194,11 +282,25 @@
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* CAN */
#define CFG_CAN_BASE (CFG_CCSRBAR \
+ 0x03000000) /* CAN base address */
#ifdef CONFIG_CAN_DRIVER
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
#define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI)
#define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \
BR_PS_8 | BR_MS_UPMC | BR_V)
#endif /* CONFIG_CAN_DRIVER */
/*
* I2C
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
@ -219,7 +321,7 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
@ -228,10 +330,64 @@
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
#ifndef CONFIG_PCIE1
/* RapidIO MMU */
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_RIO_MEM_BASE 0xb0000000 /* base address */
#define CFG_RIO_MEM_SIZE 0x10000000 /* 256M */
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
#endif /* CONFIG_PCIE1 */
/* NAND FLASH */
#ifdef CONFIG_NAND
#undef CFG_NAND_LEGACY
#define CONFIG_NAND_FSL_UPM 1
#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
/* address distance between chip selects */
#define CFG_NAND_SELECT_DEVICE 1
#define CFG_NAND_CS_DIST 0x200
#define CFG_NAND_SIZE 0x8000
#define CFG_NAND0_BASE (CFG_CCSRBAR + 0x03010000)
#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
#define NAND_MAX_CHIPS 1
#if (CFG_MAX_NAND_DEVICE == 1)
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
#elif (CFG_MAX_NAND_DEVICE == 2)
#define CFG_NAND_QUIET_TEST 1
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
CFG_NAND1_BASE, \
}
#elif (CFG_MAX_NAND_DEVICE == 4)
#define CFG_NAND_QUIET_TEST 1
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
CFG_NAND1_BASE, \
CFG_NAND2_BASE, \
CFG_NAND3_BASE, \
}
#endif
/* CS3 for NAND Flash */
#define CFG_BR3_PRELIM ((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \
BR_MS_UPMB | BR_V)
#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI)
#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
#endif /* CONFIG_NAND */
/*
* General PCI
@ -240,9 +396,33 @@
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_BASE (CFG_CCSRBAR + 0x02000000)
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x80000000
#ifdef CONFIG_PCIE1
/*
* General PCI express
* Addresses are mapped 1-1.
*/
#ifdef CONFIG_TQM_BIGFLASH
#define CFG_PCIE1_MEM_BASE 0xb0000000
#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 512M */
#define CFG_PCIE1_IO_BASE 0xaf000000
#else /* !CONFIG_TQM_BIGFLASH */
#define CFG_PCIE1_MEM_BASE 0xc0000000
#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE1_IO_BASE 0xef000000
#endif /* CONFIG_TQM_BIGFLASH */
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE
#define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */
#endif /* CONFIG_PCIE1 */
#if defined(CONFIG_PCI)
@ -254,8 +434,7 @@
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#endif /* CONFIG_PCI */
#define CONFIG_NET_MULTI 1
@ -277,6 +456,27 @@
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#ifdef CONFIG_TQM8548
/*
* TQM8548 has 4 ethernet ports. 4 ETSEC's.
*
* On the STK85xx Starterkit the ETSEC3/4 ports are on an
* additional adapter (AIO) between module and Starterkit.
*/
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "TSEC2"
#define CONFIG_TSEC4 1
#define CONFIG_TSEC4_NAME "TSEC3"
#define TSEC3_PHY_ADDR 4
#define TSEC4_PHY_ADDR 5
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define CONFIG_HAS_ETH3
#define CONFIG_HAS_ETH4
#endif /* CONFIG_TQM8548 */
/* Options are TSEC[0-1], FEC */
#define CONFIG_ETHPRIME "TSEC0"
@ -305,7 +505,7 @@
* FCC2: a - c (X50.2 - 1)
*/
#define CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_TQM8560)
@ -321,12 +521,13 @@
* FCC3: a - d (X50.2 - 3)
*/
#define CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
#endif
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
#define CONFIG_ETHER_ON_FCC1
#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
CMXFCR_TF1CS_MSK)
#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@ -334,7 +535,8 @@
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
#define CONFIG_ETHER_ON_FCC2
#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@ -342,7 +544,8 @@
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
#define CONFIG_ETHER_ON_FCC3
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
CMXFCR_TF3CS_MSK)
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
@ -352,17 +555,21 @@
* Environment
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#ifdef CONFIG_TQM_FLASH_N_TYPE
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
#else /* !CONFIG_TQM_FLASH_N_TYPE */
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
#endif /* CONFIG_TQM_FLASH_N_TYPE */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_TIMESTAMP /* Print image info with ts */
#define CONFIG_TIMESTAMP /* Print image info with ts */
/*
* BOOTP options
@ -372,6 +579,25 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#ifdef CONFIG_NAND
/*
* Use NAND-FLash as JFFS2 device
*/
#define CONFIG_CMD_NAND
#define CONFIG_CMD_JFFS2
#define CONFIG_JFFS2_NAND 1
#ifdef CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
#else
#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
#endif /* CONFIG_JFFS2_CMDLINE */
#endif /* CONFIG_NAND */
/*
* Command line configuration.
@ -389,10 +615,9 @@
#define CONFIG_CMD_MII
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI
#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
@ -403,12 +628,13 @@
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
#define CFG_PBSIZE (CFG_CBSIZE + \
sizeof(CFG_PROMPT) + 16) /* Print Buf Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
@ -433,7 +659,6 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
@ -444,10 +669,26 @@
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
/*
* Setup some board specific values for the default environment variables
*/
#ifdef CONFIG_CPM2
#define CFG_ENV_CONSDEV "consdev=ttyCPM0\0"
#else
#define CFG_ENV_CONSDEV "consdev=ttyS0\0"
#endif
#define CFG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
MK_STR(CONFIG_HOSTNAME)".dtb\0"
#define CFG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
#define CFG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
"uboot_addr="MK_STR(TEXT_BASE)"\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootfile="CFG_BOOTFILE_PATH"\0" \
CFG_ENV_BOOTFILE \
CFG_ENV_FDT_FILE \
CFG_ENV_CONSDEV \
"netdev=eth0\0" \
"consdev=ttyS0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@ -457,20 +698,27 @@
"addcons=setenv bootargs $bootargs " \
"console=$consdev,$baudrate\0" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm $kernel_addr\0" \
"bootm $kernel_addr - $fdt_addr\0" \
"flash_self=run ramargs addip addcons;" \
"bootm $kernel_addr $ramdisk_addr\0" \
"net_nfs=tftp $loadaddr $bootfile;" \
"run nfsargs addip addcons;bootm\0" \
"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
"net_nfs=tftp $kernel_addr_r $bootfile;" \
"tftp $fdt_addr_r $fdt_file;" \
"run nfsargs addip addcons;" \
"bootm $kernel_addr_r - $fdt_addr_r\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"kernel_addr=FE000000\0" \
"ramdisk_addr=FE180000\0" \
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"fdt_addr_r=900000\0" \
"kernel_addr_r=1000000\0" \
"fdt_addr=ffec0000\0" \
"kernel_addr=ffd00000\0" \
"ramdisk_addr=ff800000\0" \
CFG_ENV_UBOOT \
"load=tftp 100000 $uboot\0" \
"update=protect off $uboot_addr +$filesize;" \
"erase $uboot_addr +$filesize;" \
"cp.b 100000 $uboot_addr $filesize;" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#endif /* __CONFIG_H */
#endif /* __CONFIG_H */

1
include/configs/sbc8560.h
View File

@ -42,6 +42,7 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
#define CONFIG_MPC8560 1
/* XXX flagging this as something I might want to delete */
#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */

29
include/configs/socrates.h
View File

@ -165,7 +165,7 @@
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/* Serial Port */
@ -216,11 +216,6 @@
#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
#define CFG_EEPROM_PAGE_WRITE_BITS 4
/* RapidIO MMU */
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
/*
* General PCI
* Memory space is mapped 1-1.
@ -238,13 +233,7 @@
#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
@ -390,10 +379,10 @@
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addcons;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"fdt_file=$hostname/socrates.dtb\0" \
"fdt_file=$hostname/socrates.dtb\0" \
"fdt_addr_r=B00000\0" \
"fdt_addr=FC1E0000\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"rootpath=/opt/eldk/ppc_85xxDP\0" \
"kernel_addr=FC000000\0" \
"kernel_addr_r=200000\0" \
"ramdisk_addr=FC200000\0" \
@ -420,4 +409,14 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_USB_STORAGE 1
/* FPGA and NAND */
#define CFG_FPGA_BASE 0xc0000000
#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */
#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70)
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_CMD_NAND
#endif /* __CONFIG_H */

1
include/configs/stxgp3.h
View File

@ -41,6 +41,7 @@
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
#define CONFIG_MPC8560 1
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/

1
include/configs/stxssa.h
View File

@ -41,6 +41,7 @@
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#define CONFIG_MPC8560 1
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/

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