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ARM: sunxi: Add clock and uart to sunxi headers

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This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Icenowy Zheng 2022-01-29 10:23:03 -05:00 committed by Andre Przywara
parent 88998f7775
commit 5d35f0f254
4 changed files with 21 additions and 1 deletions
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2
arch/arm/include/asm/arch-sunxi/clock.h
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@ -19,7 +19,7 @@
#elif defined(CONFIG_SUN50I_GEN_H6)
#include <asm/arch/clock_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
defined(CONFIG_MACH_SUN50I)
defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)
#include <asm/arch/clock_sun6i.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/clock_sun9i.h>

13
arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@ -226,7 +226,12 @@ struct sunxi_ccm_reg {
#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24)
#define CCM_PLL5_CTRL_EN (0x1 << 31)
#ifdef CONFIG_MACH_SUNIV
/* suniv pll6 doesn't have postdiv 2, so k is set to 0 */
#define PLL6_CFG_DEFAULT 0x90041801
#else
#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
#endif
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
@ -488,6 +493,14 @@ struct sunxi_ccm_reg {
#define AHB_RESET_OFFSET_EPHY 2
#define AHB_RESET_OFFSET_LVDS 0
/* apb1 reset */
#ifdef CONFIG_MACH_SUNIV
#define APB1_GATE_UART_SHIFT (20)
#define APB1_GATE_TWI_SHIFT (16)
#define APB1_RESET_UART_SHIFT (20)
#define APB1_RESET_TWI_SHIFT (16)
#endif
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)

6
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
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@ -129,9 +129,15 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
#ifdef CONFIG_MACH_SUNIV
#define SUNXI_UART0_BASE 0x01c25000
#define SUNXI_UART1_BASE 0x01c25400
#define SUNXI_UART2_BASE 0x01c25800
#else
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
#endif
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400

1
arch/arm/include/asm/arch-sunxi/gpio.h
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@ -165,6 +165,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
#define SUNIV_GPE_UART0 5
#define SUN8I_GPE_TWI2 3
#define SUN50I_GPE_TWI2 3