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arm: arm926ej-s: Add sunxi code

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Some Allwinner SoCs use ARM926EJ-S core.

Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Icenowy Zheng 2022-01-29 10:23:02 -05:00 committed by Andre Przywara
parent 0d4377fc92
commit 88998f7775
6 changed files with 106 additions and 0 deletions
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1
arch/arm/cpu/arm926ejs/Makefile
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@ -15,6 +15,7 @@ endif
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
# some files can only build in ARM or THUMB2, not THUMB1

13
arch/arm/cpu/arm926ejs/cpu.c
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@ -21,6 +21,19 @@
static void cache_flush(void);
/************************************************************
* sdelay() - simple spin loop. Will be constant time as
* its generally used in bypass conditions only. This
* is necessary until timers are accessible.
*
* not inline to increase chances its in cache when called
*************************************************************/
void sdelay(unsigned long loops)
{
__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0"(loops));
}
int cleanup_before_linux (void)
{
/*

5
arch/arm/cpu/arm926ejs/sunxi/Makefile Normal file
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@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
obj-y += fel_utils.o
CFLAGS_fel_utils.o := -marm

6
arch/arm/cpu/arm926ejs/sunxi/config.mk Normal file
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@ -0,0 +1,6 @@
# Build a combined spl + u-boot image
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
ALL-y += u-boot-sunxi-with-spl.bin
endif
endif

33
arch/arm/cpu/arm926ejs/sunxi/fel_utils.S Normal file
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@ -0,0 +1,33 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Utility functions for FEL mode.
*
* Copyright (c) 2015 Google, Inc
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
ldr r0, =fel_stash
str sp, [r0, #0]
str lr, [r0, #4]
mrs lr, cpsr @ Read CPSR
str lr, [r0, #8]
mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
str lr, [r0, #12]
b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(return_to_fel)
mov sp, r0
mov lr, r1
ldr r0, =fel_stash
ldr r1, [r0, #16]
mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
ldr r1, [r0, #12]
msr cpsr, r1 @ Write CPSR
bx lr
ENDPROC(return_to_fel)

48
arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds Normal file
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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2018
* Icenowy Zheng <icenowy@aosc.io>
*
* Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
.text :
{
__start = .;
*(.vectors)
*(.text*)
} > .sram
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
} > .sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} > .sdram
}