ARM: rmobile: Add R8A77970 SoC
Add bits to support yet another SoC, the R8A77970 V3M . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
894ee0575f
commit
5cb19e7ad5
392
arch/arm/dts/r8a77970.dtsi
Normal file
392
arch/arm/dts/r8a77970.dtsi
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@ -0,0 +1,392 @@
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/*
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* Device Tree Source for the r8a77970 SoC
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*
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* Copyright (C) 2016-2017 Renesas Electronics Corp.
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* Copyright (C) 2017 Cogent Embedded, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/ {
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compatible = "renesas,r8a77970";
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0>;
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clocks = <&cpg CPG_CORE 0>;
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power-domains = <&sysc 5>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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};
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L2_CA53: cache-controller {
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compatible = "cache";
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power-domains = <&sysc 21>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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u-boot,dm-pre-reloc;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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u-boot,dm-pre-reloc;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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u-boot,dm-pre-reloc;
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1010000 0 0x1000>,
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<0 0xf1020000 0 0x20000>,
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<0 0xf1040000 0 0x20000>,
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<0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc 32>;
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resets = <&cpg 408>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77970-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77970-rst";
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reg = <0 0xe6160000 0 0x200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77970-sysc";
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reg = <0 0xe6180000 0 0x440>;
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#power-domain-cells = <1>;
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};
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pfc: pfc@e6060000 {
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compatible = "renesas,pfc-r8a77970";
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reg = <0 0xe6060000 0 0x50c>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc 32>;
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resets = <&cpg 407>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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u-boot,dm-pre-reloc;
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};
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dmac1: dma-controller@e7300000 {
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compatible = "renesas,dmac-r8a77970",
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"renesas,rcar-dmac";
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reg = <0 0xe7300000 0 0x10000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 218>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 218>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
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dmac2: dma-controller@e7310000 {
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compatible = "renesas,dmac-r8a77970",
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"renesas,rcar-dmac";
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reg = <0 0xe7310000 0 0x10000>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 217>;
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clock-names = "fck";
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power-domains = <&sysc 32>;
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resets = <&cpg 217>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
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hscif0: serial@e6540000 {
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compatible = "renesas,hscif-r8a77970",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6540000 0 96>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 520>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x31>, <&dmac1 0x30>,
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<&dmac2 0x31>, <&dmac2 0x30>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 520>;
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status = "disabled";
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};
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hscif1: serial@e6550000 {
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compatible = "renesas,hscif-r8a77970",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6550000 0 96>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 519>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x33>, <&dmac1 0x32>,
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<&dmac2 0x33>, <&dmac2 0x32>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 519>;
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status = "disabled";
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};
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hscif2: serial@e6560000 {
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compatible = "renesas,hscif-r8a77970",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6560000 0 96>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 518>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x35>, <&dmac1 0x34>,
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<&dmac2 0x35>, <&dmac2 0x34>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 518>;
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status = "disabled";
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};
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hscif3: serial@e66a0000 {
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compatible = "renesas,hscif-r8a77970",
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"renesas,rcar-gen3-hscif", "renesas,hscif";
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reg = <0 0xe66a0000 0 96>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 517>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x37>, <&dmac1 0x36>,
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<&dmac2 0x37>, <&dmac2 0x36>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 517>;
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status = "disabled";
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a77970",
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"renesas,rcar-gen3-scif",
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"renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 207>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x51>, <&dmac1 0x50>,
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<&dmac2 0x51>, <&dmac2 0x50>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 207>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a77970",
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"renesas,rcar-gen3-scif",
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"renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 206>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x53>, <&dmac1 0x52>,
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<&dmac2 0x53>, <&dmac2 0x52>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 206>;
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status = "disabled";
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};
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scif3: serial@e6c50000 {
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compatible = "renesas,scif-r8a77970",
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"renesas,rcar-gen3-scif",
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"renesas,scif";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 204>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x57>, <&dmac1 0x56>,
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<&dmac2 0x57>, <&dmac2 0x56>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 204>;
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status = "disabled";
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};
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scif4: serial@e6c40000 {
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compatible = "renesas,scif-r8a77970",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6c40000 0 64>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 203>,
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<&cpg CPG_CORE 9>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x59>, <&dmac1 0x58>,
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<&dmac2 0x59>, <&dmac2 0x58>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc 32>;
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resets = <&cpg 203>;
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status = "disabled";
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a77970",
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"renesas,etheravb-rcar-gen3";
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reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24";
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc 32>;
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resets = <&cpg 812>;
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phy-mode = "rgmii-id";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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@ -9,6 +9,9 @@ config R8A7795
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config R8A7796
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bool "Renesas SoC R8A7796"
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config R8A77970
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bool "Renesas SoC R8A77970"
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endchoice
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choice
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@ -61,6 +61,7 @@ static const struct {
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{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
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{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
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{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
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{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
|
||||
{ 0x0, "CPU" },
|
||||
};
|
||||
|
||||
|
||||
@ -33,6 +33,7 @@
|
||||
#define RMOBILE_CPU_TYPE_R8A7794 0x4C
|
||||
#define RMOBILE_CPU_TYPE_R8A7795 0x4F
|
||||
#define RMOBILE_CPU_TYPE_R8A7796 0x52
|
||||
#define RMOBILE_CPU_TYPE_R8A77970 0x54
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
u32 rmobile_get_cpu_type(void);
|
||||
|
||||
@ -49,6 +49,26 @@ static struct mm_region r8a7796_mem_map[] = {
|
||||
}
|
||||
};
|
||||
|
||||
static struct mm_region r8a77970_mem_map[] = {
|
||||
{
|
||||
.virt = 0x0UL,
|
||||
.phys = 0x0UL,
|
||||
.size = 0xe0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
.virt = 0xe0000000UL,
|
||||
.phys = 0xe0000000UL,
|
||||
.size = 0xe0000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE |
|
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
|
||||
struct mm_region *mem_map = r8a7795_mem_map;
|
||||
|
||||
void rcar_gen3_memmap_fixup(void)
|
||||
@ -62,5 +82,8 @@ void rcar_gen3_memmap_fixup(void)
|
||||
case RMOBILE_CPU_TYPE_R8A7796:
|
||||
mem_map = r8a7796_mem_map;
|
||||
break;
|
||||
case RMOBILE_CPU_TYPE_R8A77970:
|
||||
mem_map = r8a77970_mem_map;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -44,7 +44,11 @@
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
|
||||
|
||||
/* MEMORY */
|
||||
#if defined(CONFIG_R8A77970)
|
||||
#define CONFIG_SYS_TEXT_BASE 0x58280000
|
||||
#else
|
||||
#define CONFIG_SYS_TEXT_BASE 0x50000000
|
||||
#endif
|
||||
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define DRAM_RSV_SIZE 0x08000000
|
||||
|
||||
48
include/dt-bindings/clock/r8a77970-cpg-mssr.h
Normal file
48
include/dt-bindings/clock/r8a77970-cpg-mssr.h
Normal file
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77970 CPG Core Clocks */
|
||||
#define R8A77970_CLK_Z2 0
|
||||
#define R8A77970_CLK_ZR 1
|
||||
#define R8A77970_CLK_ZTR 2
|
||||
#define R8A77970_CLK_ZTRD2 3
|
||||
#define R8A77970_CLK_ZT 4
|
||||
#define R8A77970_CLK_ZX 5
|
||||
#define R8A77970_CLK_S1D1 6
|
||||
#define R8A77970_CLK_S1D2 7
|
||||
#define R8A77970_CLK_S1D4 8
|
||||
#define R8A77970_CLK_S2D1 9
|
||||
#define R8A77970_CLK_S2D2 10
|
||||
#define R8A77970_CLK_S2D4 11
|
||||
#define R8A77970_CLK_LB 12
|
||||
#define R8A77970_CLK_CL 13
|
||||
#define R8A77970_CLK_ZB3 14
|
||||
#define R8A77970_CLK_ZB3D2 15
|
||||
#define R8A77970_CLK_DDR 16
|
||||
#define R8A77970_CLK_CR 17
|
||||
#define R8A77970_CLK_CRD2 18
|
||||
#define R8A77970_CLK_SD0H 19
|
||||
#define R8A77970_CLK_SD0 20
|
||||
#define R8A77970_CLK_RPC 21
|
||||
#define R8A77970_CLK_RPCD2 22
|
||||
#define R8A77970_CLK_MSO 23
|
||||
#define R8A77970_CLK_CANFD 24
|
||||
#define R8A77970_CLK_CSI0 25
|
||||
#define R8A77970_CLK_FRAY 26
|
||||
#define R8A77970_CLK_CP 27
|
||||
#define R8A77970_CLK_CPEX 28
|
||||
#define R8A77970_CLK_R 29
|
||||
#define R8A77970_CLK_OSC 30
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
|
||||
32
include/dt-bindings/power/r8a77970-sysc.h
Normal file
32
include/dt-bindings/power/r8a77970-sysc.h
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Cogent Embedded Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77970_PD_CA53_CPU0 5
|
||||
#define R8A77970_PD_CA53_CPU1 6
|
||||
#define R8A77970_PD_CR7 13
|
||||
#define R8A77970_PD_CA53_SCU 21
|
||||
#define R8A77970_PD_A2IR0 23
|
||||
#define R8A77970_PD_A3IR 24
|
||||
#define R8A77970_PD_A2IR1 27
|
||||
#define R8A77970_PD_A2IR2 28
|
||||
#define R8A77970_PD_A2IR3 29
|
||||
#define R8A77970_PD_A2SC0 30
|
||||
#define R8A77970_PD_A2SC1 31
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77970_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
|
||||
Loading…
Reference in New Issue
Block a user