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powerpc/83xx/km: add MV88E6122 switch support for kmvect1

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kmvect1 has a UEC2 connection to the piggy board and a UEC0 connection
to the switch MV88E6122. This switch has a connection to a frontport
ethernet interface. The ethernet port used for network booting is
automatically selected by u-boot. If a Piggy is plugged, the Piggy
port is selected (UEC2, eth1). If the Piggy isn't present, the
Frontport is selected (UEC0, eth0).

The switch reset is connected to a GPIO on the PRIO3 board FPGA (GPIO28)
and released at startup.

Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
This commit is contained in:
Karlheinz Jerg 2013-01-21 03:55:18 +00:00 committed by Kim Phillips
parent 322bb2056b
commit 5bcd64cf5c
4 changed files with 113 additions and 7 deletions
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8
board/keymile/common/ivm.c
View File

@ -233,7 +233,13 @@ static int ivm_analyze_block2(unsigned char *buf, int len)
if (getenv("ethaddr") == NULL)
setenv((char *)"ethaddr", (char *)valbuf);
#endif
#ifdef CONFIG_KMVECT1
/* KMVECT1 has two ethernet interfaces */
if (getenv("eth1addr") == NULL) {
calculate_mac_offset(buf, valbuf, 1);
setenv((char *)"eth1addr", (char *)valbuf);
}
#endif
/* IVM_MacCount */
count = (buf[10] << 24) +
(buf[11] << 16) +

67
board/keymile/km83xx/km83xx.c
View File

@ -215,8 +215,75 @@ int misc_init_r(void)
return 0;
}
#if defined(CONFIG_KMVECT1)
#include <mv88e6352.h>
/* Marvell MV88E6122 switch configuration */
static struct mv88e_sw_reg extsw_conf[] = {
/* port 1, FRONT_MDI, autoneg */
{ PORT(1), PORT_PHY, NO_SPEED_FOR },
{ PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
{ PHY(1), PHY_1000_CTRL, NO_ADV },
{ PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
{ PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
FULL_DUPLEX },
/* port 2, unused */
{ PORT(2), PORT_CTRL, PORT_DIS },
{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
/* port 3, BP_MII (CPU), PHY mode, 100BASE */
{ PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
/* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
{ PORT(4), PORT_PHY, SPEED_1000_FOR },
{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
/* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
{ PORT(5), PORT_STATUS, NO_PHY_DETECT },
{ PORT(5), PORT_PHY, SPEED_1000_FOR },
{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
/*
* Errata Fix: 1.9V Output from Internal 1.8V Regulator,
* acc . MV-S300889-00D.pdf , clause 4.5
*/
{ PORT(5), 0x1A, 0xADB1 },
/* port 6, unused, this port has no phy */
{ PORT(6), PORT_CTRL, PORT_DIS },
};
#endif
int last_stage_init(void)
{
#if defined(CONFIG_KMVECT1)
struct km_bec_fpga __iomem *base =
(struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
u8 tmp_reg;
/* Release mv88e6122 from reset */
tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
out_8(&base->res1[0], tmp_reg); /* GP28 as output */
tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */
out_8(&base->gprt3, tmp_reg);
/* configure MV88E6122 switch */
char *name = "UEC2";
if (miiphy_set_current_dev(name))
return 0;
mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
ARRAY_SIZE(extsw_conf));
mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
if (piggy_present()) {
setenv("ethact", "UEC2");
setenv("netdev", "eth1");
puts("using PIGGY for network boot\n");
} else {
setenv("netdev", "eth0");
puts("using frontport for network boot\n");
}
#endif
#if defined(CONFIG_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;

8
include/configs/km/km83xx-common.h
View File

@ -165,19 +165,15 @@
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
#if !defined(CONFIG_MPC8309)
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#endif
#ifdef CONFIG_UEC_ETH1
#if defined(CONFIG_MPC8309)
#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
#else
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#endif
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII

37
include/configs/suvd3.h
View File

@ -110,4 +110,41 @@
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/*
* QE UEC ethernet configuration
*/
#if defined(CONFIG_KMVECT1)
#define CONFIG_MV88E6352_SWITCH
#define CONFIG_KM_MVEXTSW_ADDR 0x10
/* ethernet port connected to simple switch 88e6122 (UEC0) */
#define CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
#define CONFIG_FIXED_PHY 0xFFFFFFFF
#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
{devnum, speed, duplex}
#define CONFIG_SYS_FIXED_PHY_PORTS \
CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
/* ethernet port connected to piggy (UEC2) */
#define CONFIG_HAS_ETH1
#define CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 0
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
#endif /* CONFIG_KMVECT1 */
#endif /* __CONFIG_H */