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Blackfin: define CONFIG_SYS_CACHELINE_SIZE

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Common U-Boot API wants this define, so import asm/cache.h from Linux
to provide suitable defines.

Acked-by: Anton Staaf <robotboy@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-10-12 20:16:31 -04:00 committed by Wolfgang Denk
parent 82a04900a5
commit 5aa5b88404
3 changed files with 74 additions and 0 deletions
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1
arch/blackfin/include/asm/blackfin_local.h
View File

@ -49,6 +49,7 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#include <asm/linkage.h>
#include <asm/cache.h>
#ifndef __ASSEMBLY__
# ifdef SHARED_RESOURCES

70
arch/blackfin/include/asm/cache.h Normal file
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@ -0,0 +1,70 @@
/*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __ARCH_BLACKFIN_CACHE_H
#define __ARCH_BLACKFIN_CACHE_H
#include <asm/linkage.h> /* for asmlinkage */
/*
* Bytes per L1 cache line
* Blackfin loads 32 bytes for cache
*/
#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#ifdef CONFIG_SMP
#define __cacheline_aligned
#else
#define ____cacheline_aligned
/*
* Put cacheline_aliged data to L1 data memory
*/
#ifdef CONFIG_CACHELINE_ALIGNED_L1
#define __cacheline_aligned \
__attribute__((__aligned__(L1_CACHE_BYTES), \
__section__(".data_l1.cacheline_aligned")))
#endif
#endif
/*
* largest L1 which this arch supports
*/
#define L1_CACHE_SHIFT_MAX 5
#if defined(CONFIG_SMP) && \
!defined(CONFIG_BFIN_CACHE_COHERENT)
# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
# define __ARCH_SYNC_CORE_ICACHE
# endif
# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
# define __ARCH_SYNC_CORE_DCACHE
# endif
#ifndef __ASSEMBLY__
asmlinkage void __raw_smp_mark_barrier_asm(void);
asmlinkage void __raw_smp_check_barrier_asm(void);
static inline void smp_mark_barrier(void)
{
__raw_smp_mark_barrier_asm();
}
static inline void smp_check_barrier(void)
{
__raw_smp_check_barrier_asm();
}
void resync_core_dcache(void);
void resync_core_icache(void);
#endif
#endif
#endif

3
arch/blackfin/include/asm/config.h
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@ -21,6 +21,9 @@
# define CONFIG_BFIN_SCRATCH_REG retn
#endif
/* U-Boot wants this config name */
#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
/* Make sure the structure is properly aligned */
#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned