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mx5 clocks: Fix get_periph_clk()

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In the case periph_clk comes from periph_apm_clk, the latter is selected by the
CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its
input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in
this case.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau
2012-09-27 10:22:51 +00:00
committed by Tom Rini
parent b94792982f
commit 55c8df0cb1
1 changed files with 22 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
arch/arm/cpu/armv7/mx5/clock.c
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@@ -239,6 +239,26 @@ static u32 get_fpm(void)
} }
#endif #endif
/*
* This function returns the low power audio clock.
*/
static u32 get_lp_apm(void)
{
u32 ret_val = 0;
u32 ccsr = readl(&mxc_ccm->ccsr);
if (ccsr & MXC_CCM_CCSR_LP_APM)
#if defined(CONFIG_MX51)
ret_val = get_fpm();
#elif defined(CONFIG_MX53)
ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
#endif
else
ret_val = MXC_HCLK;
return ret_val;
}
/* /*
* Get mcu main rate * Get mcu main rate
*/ */
@@ -267,6 +287,8 @@ u32 get_periph_clk(void)
return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
case 1: case 1:
return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
case 2:
return get_lp_apm();
default: default:
return 0; return 0;
} }
@@ -335,26 +357,6 @@ static u32 get_uart_clk(void)
return freq; return freq;
} }
/*
* This function returns the low power audio clock.
*/
static u32 get_lp_apm(void)
{
u32 ret_val = 0;
u32 ccsr = readl(&mxc_ccm->ccsr);
if (ccsr & MXC_CCM_CCSR_LP_APM)
#if defined(CONFIG_MX51)
ret_val = get_fpm();
#elif defined(CONFIG_MX53)
ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
#endif
else
ret_val = MXC_HCLK;
return ret_val;
}
/* /*
* get cspi clock rate. * get cspi clock rate.
*/ */