arm64: versal: Enable memory mapping via DT

Code reads DT and setup MMU table based on memory node.
This will ensure that only DT needs to be changed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arch/arm/mach-versal/Kconfig

@@ -54,4 +54,11 @@ config SYS_MEM_RSVD_FOR_MMU
 	  MMU table than the one which will be allocated during
 	  relocation.
 
+config DEFINE_TCM_OCM_MMAP
+	bool "Define TCM and OCM memory in MMU Table"
+	default y if MP
+	help
+	  This option if enabled defines the TCM and OCM memory and its
+	  memory attributes in MMU table entry.
+
 endif

arch/arm/mach-versal/cpu.c

@@ -12,14 +12,21 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct mm_region versal_mem_map[] = {
+#define VERSAL_MEM_MAP_USED	5
+
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#define TCM_MAP 1
+#else
+#define TCM_MAP 0
+#endif
+
+/* +1 is end of list which needs to be empty */
+#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
+
+static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
 	{
-		.virt = 0x0UL,
-		.phys = 0x0UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
 		.virt = 0x80000000UL,
 		.phys = 0x80000000UL,
 		.size = 0x70000000UL,
@@ -33,12 +40,6 @@ static struct mm_region versal_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0xffe00000UL,
-		.phys = 0xffe00000UL,
-		.size = 0x00200000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
 	}, {
 		.virt = 0x400000000UL,
 		.phys = 0x400000000UL,
@@ -59,12 +60,36 @@ static struct mm_region versal_mem_map[] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
-		0,
 	}
 };
 
+void mem_map_fill(void)
+{
+	int banks = VERSAL_MEM_MAP_USED;
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+	versal_mem_map[banks].virt = 0xffe00000UL;
+	versal_mem_map[banks].phys = 0xffe00000UL;
+	versal_mem_map[banks].size = 0x00200000UL;
+	versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				      PTE_BLOCK_INNER_SHARE;
+	banks = banks + 1;
+#endif
+
+	for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* Zero size means no more DDR that's this is end */
+		if (!gd->bd->bi_dram[i].size)
+			break;
+
+		versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+		versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+		versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+		versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+					      PTE_BLOCK_INNER_SHARE;
+		banks = banks + 1;
+	}
+}
+
 struct mm_region *mem_map = versal_mem_map;
 
 u64 get_page_table_size(void)

arch/arm/mach-versal/include/mach/sys_proto.h

@@ -9,3 +9,4 @@ enum {
 };
 
 void tcm_init(u8 mode);
+void mem_map_fill(void);

board/xilinx/versal/board.c

@@ -9,6 +9,7 @@
 #include <malloc.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
 
@@ -178,7 +179,13 @@ int board_late_init(void)
 
 int dram_init_banksize(void)
 {
-	fdtdec_setup_memory_banksize();
+	int ret;
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		return ret;
+
+	mem_map_fill();
 
 	return 0;
 }