board_f: Drop board_type parameter from initdram()

It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -874,7 +874,7 @@ void update_early_mmu_table(void)
 
 __weak int dram_init(void)
 {
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();

arch/mips/mach-ath79/dram.c

@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <mach/ddr.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	ddr_tap_tuning();
 	return get_ram_size((void *)KSEG1, SZ_256M);

arch/mips/mach-pic32/cpu.c

@@ -110,7 +110,7 @@ static void ddr2_pmd_ungate(void)
 }
 
 /* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	ddr2_pmd_ungate();
 	ddr2_phy_init();

arch/powerpc/cpu/mpc5xxx/spl_boot.c

@@ -62,7 +62,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram(0);
+	initdram();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);

arch/powerpc/cpu/mpc85xx/cpu.c

@@ -401,7 +401,7 @@ void mpc85xx_reginfo(void)
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
 	!defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
 	defined(CONFIG_ARCH_QEMU_E500)
@@ -411,7 +411,7 @@ phys_size_t initdram(int board_type)
 #endif
 }
 #else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size = 0;
 

arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

@@ -414,7 +414,7 @@ static unsigned char spd_read(uchar chip, uint addr)
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -2855,7 +2855,7 @@ static void test(void)
  *		time parameters.
  * 		Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	unsigned long val;
 

arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c

@@ -998,7 +998,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
  *		 banks appropriately. If Auto Memory Configuration is
  *		 not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 	unsigned long dimm_ranks[MAXDIMMS];

arch/powerpc/cpu/ppc4xx/sdram.c

@@ -148,7 +148,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 /*
  * Autodetect onboard SDRAM on 405 platforms
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	ulong speed;
 	ulong sdtr1;
@@ -349,7 +349,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
  *	 so this should be extended for other future boards
  *	 using this routine!
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	int i;
 	int tr1_bank1;

arch/powerpc/cpu/ppc4xx/spl_boot.c

@@ -26,7 +26,7 @@ void board_init_f(ulong bootflag)
 	 * First we need to initialize the SDRAM, so that the real
 	 * U-Boot or the OS (Linux) can be loaded
 	 */
-	initdram(0);
+	initdram();
 
 	/* Clear bss */
 	memset(__bss_start, '\0', __bss_end - __bss_start);

board/Arcturus/ucp1020/spl.c

@@ -110,7 +110,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/BuS/eb_cpu5282/eb_cpu5282.c

@@ -35,7 +35,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	int size, i;
 

board/a3m071/a3m071.c

@@ -76,7 +76,7 @@ static void sdram_start(int hi_addr)
  * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;

board/a4m072/a4m072.c

@@ -71,7 +71,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	ulong dramsize = 0;
 	uint svr, pvr;

board/amcc/acadia/memory.c

@@ -41,7 +41,7 @@ static void cram_bcr_write(u32 wr_val)
 	return;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	int i;
 	u32 val;

board/amcc/bamboo/bamboo.c

@@ -436,7 +436,7 @@ int checkboard(void)
 }
 
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	return spd_sdram();
 }

board/amcc/bubinga/bubinga.c

@@ -52,10 +52,10 @@ int checkboard(void)
 }
 
 /* -------------------------------------------------------------------------
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  initdram() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
    ------------------------------------------------------------------------- */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return spd_sdram();
 }

board/amcc/sequoia/sdram.c

@@ -31,7 +31,7 @@ extern void denali_core_search_data_eye(void);
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
 	ulong speed = get_bus_freq(0);

board/amcc/walnut/walnut.c

@@ -71,10 +71,10 @@ int checkboard(void)
 }
 
 /*
- * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * initdram() reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return spd_sdram();
 }

board/amcc/yosemite/yosemite.c

@@ -286,7 +286,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-phys_size_t initdram(int board)
+phys_size_t initdram(void)
 {
 	register uint reg;
 	int tr1_bank1, tr1_bank2;

board/astro/mcf5373l/mcf5373l.c

@@ -27,7 +27,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);

board/canmb/canmb.c

@@ -65,7 +65,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;

board/cm5200/cm5200.c

@@ -97,14 +97,14 @@ static mem_conf_t* get_mem_config(int board_type)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 	mem_conf_t *mem_conf;
 
-	mem_conf = get_mem_config(board_type);
+	mem_conf = get_mem_config(gd->board_type);
 
 	/* configure SDRAM start/end for detection */
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */

board/cobra5272/cobra5272.c

@@ -16,7 +16,7 @@ int checkboard (void)
 	return 0;
 };
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
 

board/davedenx/aria/aria.c

@@ -18,7 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	return fixed_sdram(NULL, NULL, 0);
 }

board/dbau1x00/dbau1x00.c

@@ -11,7 +11,7 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */

board/esd/mecp5123/mecp5123.c

@@ -62,7 +62,7 @@ int board_early_init_f(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
 }

board/esd/pmc440/sdram.c

@@ -105,7 +105,7 @@ int initdram_by_rb(int rows, int banks)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t size;
 	int n;

board/esd/vme8349/vme8349.c

@@ -28,7 +28,7 @@
 
 void ddr_enable_ecc(unsigned int dram_size);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/b4860qds/ddr.c

@@ -176,7 +176,7 @@ found:
 	popts->cpo_sample = 0x3e;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/b4860qds/spl.c

@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_boot();

board/freescale/c29xpcie/spl.c

@@ -67,7 +67,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("TPL\n");

board/freescale/corenet_ds/ddr.c

@@ -260,7 +260,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls1021aqds/ddr.c

@@ -164,7 +164,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls1021aqds/ls1021aqds.c

@@ -162,7 +162,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 	return 0;
 }

board/freescale/ls1043aqds/ddr.c

@@ -108,7 +108,7 @@ found:
 #endif
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls1043aqds/ls1043aqds.c

@@ -153,7 +153,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();

board/freescale/ls1043ardb/ddr.c

@@ -170,7 +170,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls1046aqds/ddr.c

@@ -92,7 +92,7 @@ found:
 	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls1046aqds/ls1046aqds.c

@@ -149,7 +149,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();

board/freescale/ls1046ardb/ddr.c

@@ -96,7 +96,7 @@ found:
 	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls2080a/ddr.c

@@ -158,7 +158,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 	return 0;
 }
 #endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls2080aqds/ddr.c

@@ -155,7 +155,7 @@ found:
 	}
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/ls2080ardb/ddr.c

@@ -158,7 +158,7 @@ found:
 	}
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/m5208evbe/m5208evbe.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m52277evb/m52277evb.c

@@ -21,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	u32 dramsize;
 

board/freescale/m5235evb/m5235evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);

board/freescale/m5249evb/m5249evb.c

@@ -29,7 +29,8 @@ int checkboard (void) {
 };
 
 
-phys_size_t initdram (int board_type) {
+phys_size_t initdram(void)
+{
 	unsigned long	junk = 0xa5a59696;
 
 	/*

board/freescale/m5253demo/m5253demo.c

@@ -20,7 +20,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	u32 dramsize = 0;
 

board/freescale/m5253evbe/m5253evbe.c

@@ -19,7 +19,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	/*
 	 * Check to see if the SDRAM has already been initialized

board/freescale/m5272c3/m5272c3.c

@@ -18,7 +18,8 @@ int checkboard (void) {
 	return 0;
 	};
 
-phys_size_t initdram (int board_type) {
+phys_size_t initdram(void)
+{
 	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
 
 	out_be16(&sdp->sdram_sdtr, 0xf539);

board/freescale/m5275evb/m5275evb.c

@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
 	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);

board/freescale/m5282evb/m5282evb.c

@@ -16,7 +16,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	u32 dramsize, i, dramclk;
 

board/freescale/m53017evb/m53017evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m5329evb/m5329evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m5373evb/m5373evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;

board/freescale/m54418twr/m54418twr.c

@@ -25,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	u32 dramsize;
 

board/freescale/m54451evb/m54451evb.c

@@ -26,7 +26,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF

board/freescale/m54455evb/m54455evb.c

@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF

board/freescale/m547xevb/m547xevb.c

@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);

board/freescale/m548xevb/m548xevb.c

@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);

board/freescale/mpc5121ads/mpc5121ads.c

@@ -95,7 +95,7 @@ int is_micron(void){
 	return(ismicron);
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	u32 msize = 0;
 	/*

board/freescale/mpc8308rdb/sdram.c

@@ -65,7 +65,7 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;

board/freescale/mpc8313erdb/mpc8313erdb.c

@@ -134,7 +134,7 @@ void board_init_f(ulong bootflag)
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
 	timer_init();
-	initdram(0);
+	initdram();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }

board/freescale/mpc8313erdb/sdram.c

@@ -97,7 +97,7 @@ static long fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &im->im_lbc;

board/freescale/mpc8315erdb/mpc8315erdb.c

@@ -222,7 +222,7 @@ void board_init_f(ulong bootflag)
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
 	timer_init();
-	initdram(0);
+	initdram();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }

board/freescale/mpc8315erdb/sdram.c

@@ -92,7 +92,7 @@ static long fixed_sdram(void)
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;

board/freescale/mpc8323erdb/mpc8323erdb.c

@@ -68,7 +68,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc832xemds/mpc832xemds.c

@@ -88,7 +88,7 @@ int board_early_init_r(void)
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc8349emds/mpc8349emds.c

@@ -46,7 +46,7 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	phys_size_t msize = 0;

board/freescale/mpc8349itx/mpc8349itx.c

@@ -116,7 +116,7 @@ volatile static struct pci_controller hose[] = {
 };
 #endif				/* CONFIG_PCI */
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc837xemds/mpc837xemds.c

@@ -216,7 +216,7 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc837xerdb/mpc837xerdb.c

@@ -60,7 +60,7 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -116,8 +116,7 @@ int checkboard(void)
 }
 
 
-phys_size_t
-initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size = 0;
 

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -37,8 +37,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t
-initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size = 0;
 

board/freescale/p1010rdb/spl.c

@@ -94,7 +94,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("\nTertiary program loader running in sram...");
 #else

board/freescale/p1022ds/spl.c

@@ -111,7 +111,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/freescale/p1_p2_rdb_pc/spl.c

@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else

board/freescale/p2041rdb/ddr.c

@@ -116,7 +116,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size = 0;
 

board/freescale/t102xqds/ddr.c

@@ -169,7 +169,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t102xqds/spl.c

@@ -142,7 +142,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t102xrdb/ddr.c

@@ -229,7 +229,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t102xrdb/spl.c

@@ -129,7 +129,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t1040qds/ddr.c

@@ -117,7 +117,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t104xrdb/ddr.c

@@ -120,7 +120,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t104xrdb/spl.c

@@ -125,7 +125,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t208xqds/ddr.c

@@ -104,7 +104,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t208xqds/spl.c

@@ -128,7 +128,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t208xrdb/ddr.c

@@ -97,7 +97,7 @@ found:
 	popts->cpo_sample = 0x54;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t208xrdb/spl.c

@@ -98,7 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t4qds/ddr.c

@@ -112,7 +112,7 @@ found:
 	popts->cpo_sample = 0x63;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t4qds/spl.c

@@ -133,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();

board/freescale/t4rdb/ddr.c

@@ -105,7 +105,7 @@ found:
 	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	phys_size_t dram_size;
 

board/freescale/t4rdb/spl.c

@@ -91,7 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	gd->ram_size = initdram();
 
 	mmc_boot();
 }

board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c

@@ -10,7 +10,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return 1;
 }

board/gaisler/gr_ep2s60/gr_ep2s60.c

@@ -10,7 +10,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return 1;
 }

board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c

@@ -9,7 +9,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return 1;
 }

board/gaisler/grsim/grsim.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return 1;
 }

board/gaisler/grsim_leon2/grsim_leon2.c

@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	return 1;
 }

board/gdsys/mpc8308/sdram.c

@@ -66,7 +66,7 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;

board/ids/ids8313/ids8313.c

@@ -119,7 +119,7 @@ static int setup_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	fsl_lbc_t *lbc = &im->im_lbc;