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rockchip: spl: rk3399: disable DDR security regions for SPL

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The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).

System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.

With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Philipp Tomsich 2017-03-29 21:20:28 +02:00 committed by Simon Glass
parent fbeb337529
commit 504b9f1a5f
1 changed files with 13 additions and 0 deletions
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13
arch/arm/mach-rockchip/rk3399-board-spl.c
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@ -157,6 +157,7 @@ void secure_timer_init(void)
}
#define GRF_EMMCCORE_CON11 0xff77f02c
#define SGRF_DDR_RGN_CON16 0xff330040
void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
@ -201,6 +202,17 @@ void board_init_f(ulong dummy)
hang();
}
/*
* Disable DDR security regions.
*
* As we are entered from the BootROM, the region from
* 0x0 through 0xfffff (i.e. the first MB of memory) will
* be protected. This will cause issues with the DW_MMC
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0);
secure_timer_init();
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
@ -238,6 +250,7 @@ void spl_board_init(void)
#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
back_to_bootrom();
#endif
return;
err:
printf("spl_board_init: Error %d\n", ret);