Last-minute fixes for Rockchip for 2019.04:
- reverts the deprecation of the 'download-key' detection (with a full solution pending for the next release) - applies a temporary fix for the 32bit pinctrl registers on the RK3288 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJcnoA9AAoJECaAFcEOcohNRYYH/0SAGKro+gO1q07xpBLGbOSL MJPNDQ853IpH+kI+Mc+VFeFZz8fuQHae2aKfgmHmEGGSygFqAKXvMUgG73XO8Z27 Ov9r0RgR5s35eXFC0URqcDSCuTtFSP/MdmSy2hO546pJOapHhmx/eZUId3ZFjSe5 puIQfTxK0zbNqfFlfjsRnkXhR9jhYVvPtSpFYYjCeU/dRB4/OUzNHQjwjkdB8ru1 mTLmrhqqZ4fq3t9JMrxCH3COvI6QYBXj73ynKYtJ4lByh3NdIz0a37F99FiWgH2X 0WptUN8tjjZP+2BboVNo6io/12YxE6V+wG2LGEXreS9ubMr4nm+LXqDCoZIB7MM= =ESBv -----END PGP SIGNATURE----- Merge tag 'rockchip-fixes-for-2019.04' of git://git.denx.de/u-boot-rockchip Last-minute fixes for Rockchip for 2019.04: - reverts the deprecation of the 'download-key' detection (with a full solution pending for the next release) - applies a temporary fix for the 32bit pinctrl registers on the RK3288
This commit is contained in:
Tom Rini
commit
4c644692f2
@ -61,13 +61,7 @@ int setup_boot_mode(void)
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void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG;
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int boot_mode = readl(reg);
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/*
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* This should be handled using a driver-tree property and a suitable
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* driver which can read the appropriate settings. As it is, this
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* breaks chromebook_minnie.\
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*
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* rockchip_dnl_mode_check();
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*/
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rockchip_dnl_mode_check();
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boot_mode = readl(reg);
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debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
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@ -92,10 +92,19 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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}
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static struct rockchip_pin_bank rk3288_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_UNROUTED
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PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
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IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
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IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
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IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
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IOMUX_UNROUTED,
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DRV_TYPE_WRITABLE_32BIT,
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DRV_TYPE_WRITABLE_32BIT,
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DRV_TYPE_WRITABLE_32BIT,
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0,
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PULL_TYPE_WRITABLE_32BIT,
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PULL_TYPE_WRITABLE_32BIT,
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PULL_TYPE_WRITABLE_32BIT,
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0
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),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
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IOMUX_UNROUTED,
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@ -228,7 +228,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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}
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}
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data = (mask << (bit + 16));
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if (mux_type & IOMUX_WRITABLE_32BIT) {
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regmap_read(regmap, reg, &data);
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data &= ~(mask << bit);
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} else {
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data = (mask << (bit + 16));
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}
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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@ -252,7 +258,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
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int reg, ret, i;
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u32 data, rmask_bits, temp;
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u8 bit;
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int drv_type = bank->drv[pin_num / 8].drv_type;
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/* Where need to clean the special mask for rockchip_perpin_drv_list */
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int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
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debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
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pin_num, strength);
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@ -324,10 +331,15 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
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return -EINVAL;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << rmask_bits) - 1) << (bit + 16);
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data |= (ret << bit);
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if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
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regmap_read(regmap, reg, &data);
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data &= ~(((1 << rmask_bits) - 1) << bit);
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} else {
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/* enable the write to the equivalent lower bits */
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data = ((1 << rmask_bits) - 1) << (bit + 16);
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}
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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@ -375,7 +387,11 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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case RK3288:
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case RK3368:
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case RK3399:
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pull_type = bank->pull_type[pin_num / 8];
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/*
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* Where need to clean the special mask for
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* rockchip_pull_list.
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*/
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pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
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ret = -EINVAL;
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for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
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i++) {
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@ -390,10 +406,15 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
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regmap_read(regmap, reg, &data);
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data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
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} else {
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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}
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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break;
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default:
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@ -26,6 +26,7 @@ enum rockchip_pinctrl_type {
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#define IOMUX_SOURCE_PMU BIT(2)
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#define IOMUX_UNROUTED BIT(3)
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#define IOMUX_WIDTH_3BIT BIT(4)
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#define IOMUX_WRITABLE_32BIT BIT(5)
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/**
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* Defined some common pins constants
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@ -49,6 +50,9 @@ struct rockchip_iomux {
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int offset;
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};
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#define DRV_TYPE_IO_MASK GENMASK(31, 16)
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#define DRV_TYPE_WRITABLE_32BIT BIT(31)
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/**
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* enum type index corresponding to rockchip_perpin_drv_list arrays index.
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*/
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@ -61,6 +65,9 @@ enum rockchip_pin_drv_type {
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DRV_TYPE_MAX
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};
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#define PULL_TYPE_IO_MASK GENMASK(31, 16)
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#define PULL_TYPE_WRITABLE_32BIT BIT(31)
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/**
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* enum type index corresponding to rockchip_pull_list arrays index.
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*/
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@ -200,6 +207,32 @@ struct rockchip_pin_bank {
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}, \
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}
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#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
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iom2, iom3, drv0, drv1, drv2, \
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drv3, pull0, pull1, pull2, \
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pull3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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.drv = { \
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{ .drv_type = drv0, .offset = -1 }, \
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{ .drv_type = drv1, .offset = -1 }, \
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{ .drv_type = drv2, .offset = -1 }, \
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{ .drv_type = drv3, .offset = -1 }, \
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}, \
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.pull_type[0] = pull0, \
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.pull_type[1] = pull1, \
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.pull_type[2] = pull2, \
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.pull_type[3] = pull3, \
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}
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#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
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label, iom0, iom1, iom2, \
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iom3, drv0, drv1, drv2, \
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