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Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse Source 
Conflicts:
	board/samsung/trats2/trats2.c
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2013-12-10 17:15:18 -05:00
commit 4b210ad342
217 changed files with 12159 additions and 2833 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -372,7 +372,7 @@ $(obj)u-boot.hex: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
$(obj)u-boot.srec: $(obj)u-boot
$(OBJCOPY) -O srec $< $@
$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@

19
README
View File

@ -818,6 +818,22 @@ The following options need to be configured:
as a convenience, when switching between booting from
RAM and NFS.
- Bootcount:
CONFIG_BOOTCOUNT_LIMIT
Implements a mechanism for detecting a repeating reboot
cycle, see:
http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
CONFIG_BOOTCOUNT_ENV
If no softreset save registers are found on the hardware
"bootcount" is stored in the environment. To prevent a
saveenv on all reboots, the environment variable
"upgrade_available" is used. If "upgrade_available" is
0, "bootcount" is always 0, if "upgrade_available" is
1 "bootcount" is incremented in the environment.
So the Userspace Applikation must set the "upgrade_available"
and "bootcount" variable to 0, if a boot was successfully.
- Pre-Boot Commands:
CONFIG_PREBOOT
@ -4394,6 +4410,9 @@ Low Level (hardware related) configuration options:
NOTE : currently only supported on AM335x platforms.
- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
Enables the RTC32K OSC on AM33xx based plattforms
Freescale QE/FMAN Firmware Support:
-----------------------------------

3
arch/arm/config.mk
View File

@ -103,3 +103,6 @@ ALL-y += checkarmreloc
# such usage by requiring word relocations.
PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
endif
# limit ourselves to the sections we want in the .bin.
OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn

1
arch/arm/cpu/Makefile
View File

@ -1,2 +1,3 @@
obj-$(CONFIG_AT91FAMILY) += at91-common/
obj-$(CONFIG_TEGRA) += $(SOC)-common/
obj-$(CONFIG_TEGRA) += tegra-common/

16
arch/arm/cpu/arm926ejs/at91/led.c
View File

@ -7,43 +7,41 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#ifdef CONFIG_RED_LED
void red_led_on(void)
{
at91_set_gpio_value(CONFIG_RED_LED, 1);
gpio_set_value(CONFIG_RED_LED, 1);
}
void red_led_off(void)
{
at91_set_gpio_value(CONFIG_RED_LED, 0);
gpio_set_value(CONFIG_RED_LED, 0);
}
#endif
#ifdef CONFIG_GREEN_LED
void green_led_on(void)
{
at91_set_gpio_value(CONFIG_GREEN_LED, 0);
gpio_set_value(CONFIG_GREEN_LED, 0);
}
void green_led_off(void)
{
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
gpio_set_value(CONFIG_GREEN_LED, 1);
}
#endif
#ifdef CONFIG_YELLOW_LED
void yellow_led_on(void)
{
at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
gpio_set_value(CONFIG_YELLOW_LED, 0);
}
void yellow_led_off(void)
{
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
gpio_set_value(CONFIG_YELLOW_LED, 1);
}
#endif

16
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
View File

@ -51,11 +51,13 @@ SECTIONS
_end = .;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynsym*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.hash*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
.dynsym _end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

16
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
View File

@ -51,11 +51,13 @@ SECTIONS
_end = .;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynsym*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.hash*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
.dynsym _end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

2
arch/arm/cpu/armv7/Makefile
View File

@ -12,7 +12,7 @@ obj-y += cache_v7.o
obj-y += cpu.o
obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif

4
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -149,6 +149,7 @@ __weak void am33xx_spl_board_init(void)
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
static void rtc32k_enable(void)
{
struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
@ -164,6 +165,7 @@ static void rtc32k_enable(void)
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
writel((1 << 3) | (1 << 6), &rtc->osc);
}
#endif
static void uart_soft_reset(void)
{
@ -232,8 +234,10 @@ void s_init(void)
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
sdram_init();
#endif
}

7
arch/arm/cpu/armv7/am33xx/ddr.c
View File

@ -89,15 +89,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
}
@ -121,10 +118,6 @@ void config_ddr_data(const struct ddr_data *data, int nr)
&(ddr_data_reg[nr]+i)->dt0fwsratio0);
writel(data->datawrsratio0,
&(ddr_data_reg[nr]+i)->dt0wrsratio0);
writel(data->datauserank0delay,
&(ddr_data_reg[nr]+i)->dt0rdelays0);
writel(data->datadldiff0,
&(ddr_data_reg[nr]+i)->dt0dldiff0);
}
}

6
arch/arm/cpu/armv7/at91/sama5d3_devices.c
View File

@ -15,7 +15,7 @@
unsigned int has_emac()
{
return cpu_is_sama5d31() || cpu_is_sama5d35();
return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
}
unsigned int has_gmac()
@ -42,6 +42,8 @@ char *get_cpu_name()
return "SAMA5D34";
case ARCH_EXID_SAMA5D35:
return "SAMA5D35";
case ARCH_EXID_SAMA5D36:
return "SAMA5D36";
default:
return "Unknown CPU type";
}
@ -82,7 +84,7 @@ void at91_seriald_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
/* Enable clock */
at91_periph_clk_enable(ATMEL_ID_SYS);
at91_periph_clk_enable(ATMEL_ID_DBGU);
}
#if defined(CONFIG_ATMEL_SPI)

2
arch/arm/cpu/armv7/at91/timer.c
View File

@ -60,7 +60,7 @@ int timer_init(void)
at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
/* Enable PITC Clock */
at91_periph_clk_enable(ATMEL_ID_SYS);
at91_periph_clk_enable(ATMEL_ID_PIT);
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

3
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -1410,7 +1410,8 @@ void set_mmc_clk(int dev_index, unsigned int div)
else {
if (proid_is_exynos4412())
exynos4x12_set_mmc_clk(dev_index, div);
exynos4_set_mmc_clk(dev_index, div);
else
exynos4_set_mmc_clk(dev_index, div);
}
}

2
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:
printf("SDMMC device %d not implemented\n", peripheral);
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);

126
arch/arm/cpu/armv7/exynos/spl_boot.c
View File

@ -10,8 +10,11 @@
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/dmc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/arch/spl.h>
#include <asm/arch/spi.h>
#include "common_setup.h"
#include "clock_init.h"
@ -59,6 +62,121 @@ static int config_branch_prediction(int set_cr_z)
}
#endif
#ifdef CONFIG_SPI_BOOTING
static void spi_rx_tx(struct exynos_spi *regs, int todo,
void *dinp, void const *doutp, int i)
{
uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
int rx_lvl, tx_lvl;
uint out_bytes, in_bytes;
out_bytes = todo;
in_bytes = todo;
setbits_le32(&regs->ch_cfg, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
while (in_bytes) {
uint32_t spi_sts;
int temp;
spi_sts = readl(&regs->spi_sts);
rx_lvl = ((spi_sts >> 15) & 0x7f);
tx_lvl = ((spi_sts >> 6) & 0x7f);
while (tx_lvl < 32 && out_bytes) {
temp = 0xffffffff;
writel(temp, &regs->tx_data);
out_bytes -= 4;
tx_lvl += 4;
}
while (rx_lvl >= 4 && in_bytes) {
temp = readl(&regs->rx_data);
if (rxp)
*rxp++ = temp;
in_bytes -= 4;
rx_lvl -= 4;
}
}
}
/*
* Copy uboot from spi flash to RAM
*
* @parma uboot_size size of u-boot to copy
* @param uboot_addr address in u-boot to copy
*/
static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
{
int upto, todo;
int i, timeout = 100;
struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* set the spi1 GPIO */
exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
/* set pktcnt and enable it */
writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
/* set FB_CLK_SEL */
writel(SPI_FB_DELAY_180, &regs->fb_clk);
/* set CH_WIDTH and BUS_WIDTH as word */
setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
SPI_MODE_BUS_WIDTH_WORD);
clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
/* clear rx and tx channel if set priveously */
clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
SPI_RX_BYTE_SWAP |
SPI_RX_HWORD_SWAP);
/* do a soft reset */
setbits_le32(&regs->ch_cfg, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
/* now set rx and tx channel ON */
setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
/* Send read instruction (0x3h) followed by a 24 bit addr */
writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
/* waiting for TX done */
while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
if (!timeout) {
debug("SPI TIMEOUT\n");
break;
}
timeout--;
}
for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
todo = min(uboot_size - upto, (1 << 15));
spi_rx_tx(regs, todo, (void *)(uboot_addr),
(void *)(SPI_FLASH_UBOOT_POS), i);
}
setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
/*
* Let put controller mode to BYTE as
* SPI driver does not support WORD mode yet
*/
clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
SPI_MODE_BUS_WIDTH_WORD);
writel(0, &regs->swap_cfg);
/*
* Flush spi tx, rx fifos and reset the SPI controller
* and clear rx/tx channel
*/
clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
}
#endif
/*
* Copy U-boot from mmc to RAM:
* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@ -70,6 +188,9 @@ void copy_uboot_to_ram(void)
u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
u32 offset = 0, size = 0;
#ifdef CONFIG_SPI_BOOTING
struct spl_machine_param *param = spl_get_machine_params();
#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT
u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
void (*end_bootop_from_emmc)(void);
@ -91,9 +212,8 @@ void copy_uboot_to_ram(void)
switch (bootmode) {
#ifdef CONFIG_SPI_BOOTING
case BOOT_MODE_SERIAL:
offset = SPI_FLASH_UBOOT_POS;
size = CONFIG_BL2_SIZE;
copy_bl2 = get_irom_func(SPI_INDEX);
/* Customised function to copy u-boot from SF */
exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
break;
#endif
case BOOT_MODE_MMC:

2
arch/arm/cpu/armv7/nonsec_virt.S
View File

@ -14,6 +14,7 @@
.arch_extension sec
.arch_extension virt
.align 5
/* the vector table for secure state and HYP mode */
_monitor_vectors:
.word 0 /* reset */
@ -32,7 +33,6 @@ _monitor_vectors:
* to non-secure state.
* We use only r0 and r1 here, due to constraints in the caller.
*/
.align 5
_secure_monitor:
mrc p15, 0, r1, c1, c1, 0 @ read SCR
bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits

5
arch/arm/cpu/armv7/omap-common/Makefile
View File

@ -17,6 +17,11 @@ obj-y += vc.o
obj-y += abb.o
endif
ifneq ($(CONFIG_OMAP54XX),)
obj-y += pipe3-phy.o
obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
obj-y += lowlevel_init.o

142
arch/arm/cpu/armv7/omap-common/emif-common.c
View File

@ -206,7 +206,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
}
}
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@ -217,47 +217,86 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
/*
* Set invert_clkout (if activated)--DDR_PHYCTRL_1
* Invert clock adds an additional half cycle delay on the command
* interface. The additional half cycle, is usually meant to enable
* leveling in the situation that DQS is later than CK on the board.It
* also helps provide some additional margin for leveling.
* Invert clock adds an additional half cycle delay on the
* command interface. The additional half cycle, is usually
* meant to enable leveling in the situation that DQS is later
* than CK on the board.It also helps provide some additional
* margin for leveling.
*/
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
writel(regs->emif_ddr_phy_ctlr_1,
&emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1,
&emif->emif_ddr_phy_ctrl_1_shdw);
__udelay(130);
writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
__udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
/* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
/*
* Launch 8 incremental WR_LVL- to compensate for
* PHY limitation.
*/
writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Launch Incremental leveling */
writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
__udelay(130);
__udelay(130);
}
static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
u32 fifo_reg;
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_1);
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_2);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
writel(regs->sdram_config, &emif->emif_sdram_config);
/*
* Disable leveling. This is because if leveling is kept
* enabled, then PHY triggers a false leveling during
* EMIF-idle scenario which results in wrong delay
* values getting updated. After this the EMIF becomes
* unaccessible. So disable it after the first time
*/
writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
}
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
{
if (is_omap54xx())
omap5_ddr3_leveling(base, regs);
else
dra7_ddr3_leveling(base, regs);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
@ -270,9 +309,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
/* Update timing registers */
@ -283,15 +319,24 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
do_ext_phy_settings(base, regs);
/*
* The same sequence should work on OMAP5432 as well. But strange that
* it is not working
*/
if (omap_revision() == DRA752_ES1_0) {
do_ext_phy_settings(base, regs);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
} else {
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
do_ext_phy_settings(base, regs);
}
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
if (omap_revision() == DRA752_ES1_0)
ddr3_sw_leveling(base, regs);
else
ddr3_leveling(base, regs);
ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@ -1079,10 +1124,7 @@ static void do_sdram_init(u32 base)
if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
if (omap_revision() == DRA752_ES1_0)
ddr3_sw_leveling(base, regs);
else
ddr3_leveling(base, regs);
ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
@ -1244,6 +1286,42 @@ void dmm_init(u32 base)
}
static void do_bug0039_workaround(u32 base)
{
u32 val, i, clkctrl;
struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
const struct read_write_regs *bug_00339_regs;
u32 iterations;
u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
if (is_dra7xx())
phy_status_base++;
bug_00339_regs = get_bug_regs(&iterations);
/* Put EMIF in to idle */
clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
__raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
/* Copy the phy status registers in to phy ctrl shadow registers */
for (i = 0; i < iterations; i++) {
val = __raw_readl(phy_status_base +
bug_00339_regs[i].read_reg - 1);
__raw_writel(val, phy_ctrl_base +
((bug_00339_regs[i].write_reg - 1) << 1));
__raw_writel(val, phy_ctrl_base +
(bug_00339_regs[i].write_reg << 1) - 1);
}
/* Disable leveling */
writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
__raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
}
/*
* SDRAM initialization:
* SDRAM initialization has two parts:
@ -1319,5 +1397,11 @@ void sdram_init(void)
debug("get_ram_size() successful");
}
if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
(!in_sdram && !warm_reset())) {
do_bug0039_workaround(EMIF1_BASE);
do_bug0039_workaround(EMIF2_BASE);
}
debug("<<sdram_init()\n");
}

231
arch/arm/cpu/armv7/omap-common/pipe3-phy.c Normal file
View File

@ -0,0 +1,231 @@
/*
* TI PIPE3 PHY
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <sata.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/errno.h>
#include "pipe3-phy.h"
/* PLLCTRL Registers */
#define PLL_STATUS 0x00000004
#define PLL_GO 0x00000008
#define PLL_CONFIGURATION1 0x0000000C
#define PLL_CONFIGURATION2 0x00000010
#define PLL_CONFIGURATION3 0x00000014
#define PLL_CONFIGURATION4 0x00000020
#define PLL_REGM_MASK 0x001FFE00
#define PLL_REGM_SHIFT 9
#define PLL_REGM_F_MASK 0x0003FFFF
#define PLL_REGM_F_SHIFT 0
#define PLL_REGN_MASK 0x000001FE
#define PLL_REGN_SHIFT 1
#define PLL_SELFREQDCO_MASK 0x0000000E
#define PLL_SELFREQDCO_SHIFT 1
#define PLL_SD_MASK 0x0003FC00
#define PLL_SD_SHIFT 10
#define SET_PLL_GO 0x1
#define PLL_TICOPWDN BIT(16)
#define PLL_LDOPWDN BIT(15)
#define PLL_LOCK 0x2
#define PLL_IDLE 0x1
/* PHY POWER CONTROL Register */
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
#define PLL_IDLE_TIME 100 /* in milliseconds */
#define PLL_LOCK_TIME 100 /* in milliseconds */
static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
{
return __raw_readl(addr + offset);
}
static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
u32 data)
{
__raw_writel(data, addr + offset);
}
static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
*pipe3)
{
u32 rate;
struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
rate = get_sys_clk_freq();
for (; dpll_map->rate; dpll_map++) {
if (rate == dpll_map->rate)
return &dpll_map->params;
}
printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
__func__, rate);
return NULL;
}
static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
{
u32 val;
int timeout = PLL_LOCK_TIME;
do {
mdelay(1);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
if (val & PLL_LOCK)
break;
} while (--timeout);
if (!(val & PLL_LOCK)) {
printf("%s: DPLL failed to lock\n", __func__);
return -EBUSY;
}
return 0;
}
static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
{
u32 val;
struct pipe3_dpll_params *dpll_params;
dpll_params = omap_pipe3_get_dpll_params(phy);
if (!dpll_params) {
printf("%s: Invalid DPLL parameters\n", __func__);
return -EINVAL;
}
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
val &= ~PLL_REGN_MASK;
val |= dpll_params->n << PLL_REGN_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
val &= ~PLL_SELFREQDCO_MASK;
val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
val &= ~PLL_REGM_MASK;
val |= dpll_params->m << PLL_REGM_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
val &= ~PLL_REGM_F_MASK;
val |= dpll_params->mf << PLL_REGM_F_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
val &= ~PLL_SD_MASK;
val |= dpll_params->sd << PLL_SD_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
return omap_pipe3_wait_lock(phy);
}
static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
{
u32 val, rate;
val = readl(phy->power_reg);
rate = get_sys_clk_freq();
rate = rate/1000000;
if (on) {
val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
val |= rate <<
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
} else {
val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
}
writel(val, phy->power_reg);
}
int phy_pipe3_power_on(struct omap_pipe3 *phy)
{
int ret;
u32 val;
/* Program the DPLL only if not locked */
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
if (!(val & PLL_LOCK)) {
ret = omap_pipe3_dpll_program(phy);
if (ret)
return ret;
} else {
/* else just bring it out of IDLE mode */
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
if (val & PLL_IDLE) {
val &= ~PLL_IDLE;
omap_pipe3_writel(phy->pll_ctrl_base,
PLL_CONFIGURATION2, val);
ret = omap_pipe3_wait_lock(phy);
if (ret)
return ret;
}
}
/* Power up the PHY */
omap_control_phy_power(phy, 1);
return 0;
}
int phy_pipe3_power_off(struct omap_pipe3 *phy)
{
u32 val;
int timeout = PLL_IDLE_TIME;
/* Power down the PHY */
omap_control_phy_power(phy, 0);
/* Put DPLL in IDLE mode */
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
val |= PLL_IDLE;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
/* wait for LDO and Oscillator to power down */
do {
mdelay(1);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
break;
} while (--timeout);
if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
__func__, val);
return -EBUSY;
}
return 0;
}

36
arch/arm/cpu/armv7/omap-common/pipe3-phy.h Normal file
View File

@ -0,0 +1,36 @@
/*
* TI PIPE3 PHY
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __OMAP_PIPE3_PHY_H
#define __OMAP_PIPE3_PHY_H
struct pipe3_dpll_params {
u16 m;
u8 n;
u8 freq:3;
u8 sd;
u32 mf;
};
struct pipe3_dpll_map {
unsigned long rate;
struct pipe3_dpll_params params;
};
struct omap_pipe3 {
void __iomem *pll_ctrl_base;
void __iomem *power_reg;
struct pipe3_dpll_map *dpll_map;
};
int phy_pipe3_power_on(struct omap_pipe3 *phy);
int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
#endif /* __OMAP_PIPE3_PHY_H */

75
arch/arm/cpu/armv7/omap-common/sata.c Normal file
View File

@ -0,0 +1,75 @@
/*
* TI SATA platform driver
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/clock.h>
#include <asm/arch/sata.h>
#include <asm/io.h>
#include "pipe3-phy.h"
static struct pipe3_dpll_map dpll_map_sata[] = {
{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
{ }, /* Terminator */
};
struct omap_pipe3 sata_phy = {
.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
/* .power_reg is updated at runtime */
.dpll_map = dpll_map_sata,
};
int omap_sata_init(void)
{
int ret;
u32 val;
u32 const clk_domains_sata[] = {
0
};
u32 const clk_modules_hw_auto_sata[] = {
(*prcm)->cm_l3init_ocp2scp3_clkctrl,
0
};
u32 const clk_modules_explicit_en_sata[] = {
(*prcm)->cm_l3init_sata_clkctrl,
0
};
do_enable_clocks(clk_domains_sata,
clk_modules_hw_auto_sata,
clk_modules_explicit_en_sata,
0);
/* Enable optional functional clock for SATA */
setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
SATA_CLKCTRL_OPTFCLKEN_MASK);
sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
/* Power up the PHY */
phy_pipe3_power_on(&sata_phy);
/* Enable SATA module, No Idle, No Standby */
val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
ret = ahci_init(DWC_AHSATA_BASE);
scsi_scan(1);
return ret;
}

2
arch/arm/cpu/armv7/omap3/clock.c
View File

@ -730,8 +730,6 @@ void per_clocks_enable(void)
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
}
sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
sdelay(1000);
}

12
arch/arm/cpu/armv7/omap4/hw_data.c
View File

@ -288,17 +288,21 @@ struct vcores_data omap4460_volts = {
.mm.pmic = &twl6030,
};
/*
* Take closest integer part of the mV value corresponding to a TWL6032 SMPS
* voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
*/
struct vcores_data omap4470_volts = {
.mpu.value = 1200,
.mpu.value = 1202,
.mpu.addr = SMPS_REG_ADDR_SMPS1,
.mpu.pmic = &twl6030,
.core.value = 1126,
.core.addr = SMPS_REG_ADDR_SMPS1,
.core.addr = SMPS_REG_ADDR_SMPS2,
.core.pmic = &twl6030,
.mm.value = 1137,
.mm.addr = SMPS_REG_ADDR_SMPS1,
.mm.value = 1139,
.mm.addr = SMPS_REG_ADDR_SMPS5,
.mm.pmic = &twl6030,
};

9
arch/arm/cpu/armv7/omap4/sdram_elpida.c
View File

@ -32,7 +32,7 @@
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
.sdram_config_init = 0x80000eb9,
.sdram_config = 0x80001ab9,
.ref_ctrl = 0x0000030c,
@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
.emif_ddr_phy_ctlr_1 = 0x049ff808
};
static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
.sdram_config_init = 0x80000eb1,
.sdram_config = 0x80001ab1,
.ref_ctrl = 0x000005cd,
@ -321,3 +321,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
*regs = &mr_regs;
}
__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
{
return 0;
}

9
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -600,6 +600,7 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = {
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_omap5432_es2 = {
@ -610,16 +611,18 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrio_0 = 0xbae8c631,
.ctrl_ddrio_1 = 0xb46318d8,
.ctrl_ddrio_0 = 0xA2084210,
.ctrl_ddrio_1 = 0x84210840,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0xb2c00000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x000101A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};

18
arch/arm/cpu/armv7/omap5/hwinit.c
View File

@ -168,12 +168,6 @@ void do_io_settings(void)
io_settings_lpddr2();
else
io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, (*ctrl)->control_efuse_1);
writel(EFUSE_2, (*ctrl)->control_efuse_2);
writel(EFUSE_3, (*ctrl)->control_efuse_3);
writel(EFUSE_4, (*ctrl)->control_efuse_4);
}
static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
@ -297,13 +291,17 @@ void srcomp_enable(void)
void config_data_eye_leveling_samples(u32 emif_base)
{
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
(*ctrl)->control_emif1_sdram_config_ext);
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
(*ctrl)->control_emif2_sdram_config_ext);
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif2_sdram_config_ext);
}
void init_omap_revision(void)

7
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
.cm_l3init_p1500_clkctrl = 0x4a009378,
.cm_l3init_sata_clkctrl = 0x4a009388,
.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009400,
@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
.control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
@ -373,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_status = 0x4A002134,
.control_phy_power_sata = 0x4A002374,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
.control_core_mac_id_1_lo = 0x4A00251C,
@ -698,6 +702,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
.cm_l3init_p1500_clkctrl = 0x4a009678,
.cm_l3init_sata_clkctrl = 0x4a009688,
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
@ -891,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350,
.cm_l3init_sata_clkctrl = 0x4a009388,
.cm_gmac_clkstctrl = 0x4a0093c0,
.cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,

214
arch/arm/cpu/armv7/omap5/sdram.c
View File

@ -148,13 +148,13 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0E20400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_3 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_4 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@ -172,13 +172,13 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0020400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_3 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_4 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_5 = 0x009D009D,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@ -306,7 +306,7 @@ void emif_get_device_details(u32 emif_nr,
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
const u32 ext_phy_ctrl_const_base[] = {
0x01004010,
0x00001004,
0x04010040,
@ -329,7 +329,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
0x01004010,
0x00001004,
0x04010040,
@ -352,7 +352,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
0x50D4350D,
0x00000D43,
0x04010040,
@ -376,51 +376,61 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
};
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x009E009E,
0x002E002E,
0x002E002E,
0x002E002E,
0x002E002E,
0x002E002E,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x0,
0x600020,
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x00B000B0,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00800080,
0x00800080,
0x40010080,
0x8102040
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0
};
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x009D009D,
0x002D002D,
0x002D002D,
0x002D002D,
0x002D002D,
0x002D002D,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00BB00BB,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x0,
0x600020,
0x00600020,
0x40010080,
0x8102040
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0
};
const struct lpddr2_mr_regs mr_regs = {
@ -431,27 +441,38 @@ const struct lpddr2_mr_regs mr_regs = {
.mr16 = MR16_REF_FULL_ARRAY
};
static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
const u32 **regs,
u32 *size)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = ext_phy_ctrl_const_base;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
break;
case OMAP5432_ES1_0:
*regs = ddr3_ext_phy_ctrl_const_base_es1;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
break;
case OMAP5432_ES2_0:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
break;
case DRA752_ES1_0:
if (emif_nr == 1)
if (emif_nr == 1) {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
else
*size =
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
} else {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
*size =
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
}
break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
}
}
@ -468,6 +489,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
u32 size;
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
@ -487,8 +509,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
* external phy 6-24 registers do not change with
* ddr frequency
*/
emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
emif_get_ext_phy_ctrl_const_regs(emif_nr,
&ext_phy_ctrl_const_regs, &size);
for (i = 0; i < size; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
@ -545,6 +569,74 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = {
.min_tck = &min_tck,
};
/*
* List of status registers to be controlled back to control registers
* after initial leveling
* readreg, writereg
*/
const struct read_write_regs omap5_bug_00339_regs[] = {
{ 8, 5 },
{ 9, 6 },
{ 10, 7 },
{ 14, 8 },
{ 15, 9 },
{ 16, 10 },
{ 11, 2 },
{ 12, 3 },
{ 13, 4 },
{ 17, 11 },
{ 18, 12 },
{ 19, 13 },
};
const struct read_write_regs dra_bug_00339_regs[] = {
{ 7, 7 },
{ 8, 8 },
{ 9, 9 },
{ 10, 10 },
{ 11, 11 },
{ 12, 2 },
{ 13, 3 },
{ 14, 4 },
{ 15, 5 },
{ 16, 6 },
{ 17, 12 },
{ 18, 13 },
{ 19, 14 },
{ 20, 15 },
{ 21, 16 },
{ 22, 17 },
{ 23, 18 },
{ 24, 19 },
{ 25, 20 },
{ 26, 21}
};
const struct read_write_regs *get_bug_regs(u32 *iterations)
{
const struct read_write_regs *bug_00339_regs_ptr = NULL;
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
case OMAP5432_ES1_0:
case OMAP5432_ES2_0:
bug_00339_regs_ptr = omap5_bug_00339_regs;
*iterations = sizeof(omap5_bug_00339_regs)/
sizeof(omap5_bug_00339_regs[0]);
break;
case DRA752_ES1_0:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);
break;
default:
printf("\n Error: UnKnown SOC");
}
return bug_00339_regs_ptr;
}
void emif_get_device_timings_sdp(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)

11
arch/arm/cpu/armv7/rmobile/Makefile
View File

@ -5,14 +5,13 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = lowlevel_init.o
obj-y += cpu_info.o
obj-y = cpu_info.o
obj-y += emac.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
obj-$(CONFIG_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
obj-$(CONFIG_SH73A0) += pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o

9
arch/arm/cpu/armv7/rmobile/config.mk
View File

@ -1,9 +0,0 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
# Make ARMv5 to allow more compilers to work, even though its v7a.
PLATFORM_CPPFLAGS += -march=armv5

22
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c Normal file
View File

@ -0,0 +1,22 @@
/*
* arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
* This file is r8a7790 processor support.
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
u32 rmobile_get_cpu_type(void)
{
return (readl(PRR) & 0x00007F00) >> 8;
}
u32 rmobile_get_cpu_rev_integer(void)
{
return (readl(PRR) & 0x000000F0) >> 4;
}

29
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c Normal file
View File

@ -0,0 +1,29 @@
/*
* arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#define PRR 0xFF000044
u32 rmobile_get_cpu_type(void)
{
u32 product;
product = readl(PRR);
return (u32)((product & 0x00007F00) >> 8);
}
u32 rmobile_get_cpu_rev_integer(void)
{
u32 product;
product = readl(PRR);
return (u32)((product & 0x000000F0) >> 4);
}

10
arch/arm/cpu/armv7/rmobile/cpu_info.c
View File

@ -58,6 +58,16 @@ int print_cpuinfo(void)
rmobile_get_cpu_rev_fraction());
break;
case 0x45:
printf("CPU: Renesas Electronics R8A7790 rev %d\n",
rmobile_get_cpu_rev_integer());
break;
case 0x47:
printf("CPU: Renesas Electronics R8A7791 rev %d\n",
rmobile_get_cpu_rev_integer());
break;
default:
printf("CPU: Renesas Electronics CPU rev %d.%d\n",
rmobile_get_cpu_rev_integer(),

60
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S Normal file
View File

@ -0,0 +1,60 @@
/*
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
mrc p15, 0, r4, c0, c0, 5 /* mpidr */
orr r4, r4, r4, lsr #6
and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
b do_lowlevel_init
.pool
/*
* CPU ID #1-#3 come here
*/
.align 4
do_cpu_waiting:
ldr r1, =0xe6180000 /* sysc */
1: ldr r0, [r1, #0x20] /* sbar */
tst r0, r0
beq 1b
bx r0
/*
* Only CPU ID #0 comes here
*/
.align 4
do_lowlevel_init:
/* surpress wfe if ca15 */
tst r4, #4
mrceq p15, 0, r0, c1, c0, 1 /* actlr */
orreq r0, r0, #(1<<7)
mcreq p15, 0, r0, c1, c0, 1
/* and set l2 latency */
mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
orreq r0, r0, #0x00000800
orreq r0, r0, #0x00000003
mcreq p15, 1, r0, c9, c0, 2
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]
/* initialize system */
bl s_init
ldr lr, [sp]
mov pc, lr
nop
ENDPROC(lowlevel_init)
.ltorg

829
arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c Normal file
View File

@ -0,0 +1,829 @@
/*
* arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
* This file is r8a7790 processor support - PFC hardware block.
*
* Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
*
* Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2013 Magnus Damm
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <sh_pfc.h>
#include <asm/gpio.h>
#include "pfc-r8a7790.h"
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
GP_ALL(DATA),
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
GP_ALL(IN),
PINMUX_INPUT_END,
PINMUX_OUTPUT_BEGIN,
GP_ALL(OUT),
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN),
/* GPSR0 */
FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
FN_IP3_14_12, FN_IP3_17_15,
/* GPSR1 */
FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
/* GPSR2 */
FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
/* GPSR3 */
FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
/* GPSR4 */
FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
FN_IP14_15_12, FN_IP14_18_16,
/* GPSR5 */
FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
/* IPSR0 - IPSR5 */
/* IPSR6 */
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F,
/* IPSR7 */
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
/* IPSR8 - IPSR16 */
FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
FN_SEL_SCIF1_4,
FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
FN_SEL_SCIFB1_4,
FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
FN_SEL_SCFA_0, FN_SEL_SCFA_1,
FN_SEL_SOF1_0, FN_SEL_SOF1_1,
FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
FN_SEL_SSI6_0, FN_SEL_SSI6_1,
FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
FN_SEL_VI3_0, FN_SEL_VI3_1,
FN_SEL_VI2_0, FN_SEL_VI2_1,
FN_SEL_VI1_0, FN_SEL_VI1_1,
FN_SEL_VI0_0, FN_SEL_VI0_1,
FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
FN_SEL_LBS_0, FN_SEL_LBS_1,
FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
FN_SEL_SOF3_0, FN_SEL_SOF3_1,
FN_SEL_SOF0_0, FN_SEL_SOF0_1,
FN_SEL_TMU1_0, FN_SEL_TMU1_1,
FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
FN_SEL_CAN1_0, FN_SEL_CAN1_1,
FN_SEL_ADI_0, FN_SEL_ADI_1,
FN_SEL_SSP_0, FN_SEL_SSP_1,
FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
FN_SEL_IIC0_0, FN_SEL_IIC0_1,
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
FN_SEL_IIC2_4,
FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
FN_SEL_I2C2_4,
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
MII_RXD2_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_IPSR_DATA(IP6_2_0, DACK0),
PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
PINMUX_IPSR_DATA(IP6_8_6, DACK1),
PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
PINMUX_IPSR_DATA(IP6_13_11, DACK2),
PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_18_16, PWM0),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_21_19, PWM1),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
PINMUX_IPSR_DATA(IP7_24_22, PWM2),
PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
};
static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO_GP_ALL(),
/*IPSR0 - IPSR5*/
/*IPSR6*/
GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
/*IPSR7*/
GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
/*IPSR8 - IPSR16*/
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
GP_0_31_FN, FN_IP3_17_15,
GP_0_30_FN, FN_IP3_14_12,
GP_0_29_FN, FN_IP3_11_8,
GP_0_28_FN, FN_IP3_7_4,
GP_0_27_FN, FN_IP3_3_0,
GP_0_26_FN, FN_IP2_28_26,
GP_0_25_FN, FN_IP2_25_22,
GP_0_24_FN, FN_IP2_21_18,
GP_0_23_FN, FN_IP2_17_15,
GP_0_22_FN, FN_IP2_14_12,
GP_0_21_FN, FN_IP2_11_9,
GP_0_20_FN, FN_IP2_8_6,
GP_0_19_FN, FN_IP2_5_3,
GP_0_18_FN, FN_IP2_2_0,
GP_0_17_FN, FN_IP1_29_28,
GP_0_16_FN, FN_IP1_27_26,
GP_0_15_FN, FN_IP1_25_22,
GP_0_14_FN, FN_IP1_21_18,
GP_0_13_FN, FN_IP1_17_15,
GP_0_12_FN, FN_IP1_14_12,
GP_0_11_FN, FN_IP1_11_8,
GP_0_10_FN, FN_IP1_7_4,
GP_0_9_FN, FN_IP1_3_0,
GP_0_8_FN, FN_IP0_30_27,
GP_0_7_FN, FN_IP0_26_23,
GP_0_6_FN, FN_IP0_22_20,
GP_0_5_FN, FN_IP0_19_16,
GP_0_4_FN, FN_IP0_15_12,
GP_0_3_FN, FN_IP0_11_9,
GP_0_2_FN, FN_IP0_8_6,
GP_0_1_FN, FN_IP0_5_3,
GP_0_0_FN, FN_IP0_2_0 }
},
{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
0, 0,
0, 0,
GP_1_29_FN, FN_IP6_13_11,
GP_1_28_FN, FN_IP6_10_9,
GP_1_27_FN, FN_IP6_8_6,
GP_1_26_FN, FN_IP6_5_3,
GP_1_25_FN, FN_IP6_2_0,
GP_1_24_FN, FN_IP5_29_27,
GP_1_23_FN, FN_IP5_26_24,
GP_1_22_FN, FN_IP5_23_21,
GP_1_21_FN, FN_IP5_20_18,
GP_1_20_FN, FN_IP5_17_15,
GP_1_19_FN, FN_IP5_14_13,
GP_1_18_FN, FN_IP5_12_10,
GP_1_17_FN, FN_IP5_9_6,
GP_1_16_FN, FN_IP5_5_3,
GP_1_15_FN, FN_IP5_2_0,
GP_1_14_FN, FN_IP4_29_27,
GP_1_13_FN, FN_IP4_26_24,
GP_1_12_FN, FN_IP4_23_21,
GP_1_11_FN, FN_IP4_20_18,
GP_1_10_FN, FN_IP4_17_15,
GP_1_9_FN, FN_IP4_14_12,
GP_1_8_FN, FN_IP4_11_9,
GP_1_7_FN, FN_IP4_8_6,
GP_1_6_FN, FN_IP4_5_3,
GP_1_5_FN, FN_IP4_2_0,
GP_1_4_FN, FN_IP3_31_29,
GP_1_3_FN, FN_IP3_28_26,
GP_1_2_FN, FN_IP3_25_23,
GP_1_1_FN, FN_IP3_22_20,
GP_1_0_FN, FN_IP3_19_18, }
},
{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
0, 0,
0, 0,
GP_2_29_FN, FN_IP7_15_13,
GP_2_28_FN, FN_IP7_12_10,
GP_2_27_FN, FN_IP7_9_8,
GP_2_26_FN, FN_IP7_7_6,
GP_2_25_FN, FN_IP7_5_3,
GP_2_24_FN, FN_IP7_2_0,
GP_2_23_FN, FN_IP6_31_29,
GP_2_22_FN, FN_IP6_28_26,
GP_2_21_FN, FN_IP6_25_23,
GP_2_20_FN, FN_IP6_22_20,
GP_2_19_FN, FN_IP6_19_17,
GP_2_18_FN, FN_IP6_16_14,
GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
GP_2_16_FN, FN_IP8_27,
GP_2_15_FN, FN_IP8_26,
GP_2_14_FN, FN_IP8_25_24,
GP_2_13_FN, FN_IP8_23_22,
GP_2_12_FN, FN_IP8_21_20,
GP_2_11_FN, FN_IP8_19_18,
GP_2_10_FN, FN_IP8_17_16,
GP_2_9_FN, FN_IP8_15_14,
GP_2_8_FN, FN_IP8_13_12,
GP_2_7_FN, FN_IP8_11_10,
GP_2_6_FN, FN_IP8_9_8,
GP_2_5_FN, FN_IP8_7_6,
GP_2_4_FN, FN_IP8_5_4,
GP_2_3_FN, FN_IP8_3_2,
GP_2_2_FN, FN_IP8_1_0,
GP_2_1_FN, FN_IP7_30_29,
GP_2_0_FN, FN_IP7_28_27 }
},
{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
GP_3_31_FN, FN_IP11_21_18,
GP_3_30_FN, FN_IP11_17_15,
GP_3_29_FN, FN_IP11_14_13,
GP_3_28_FN, FN_IP11_12_11,
GP_3_27_FN, FN_IP11_10_9,
GP_3_26_FN, FN_IP11_8_7,
GP_3_25_FN, FN_IP11_6_5,
GP_3_24_FN, FN_IP11_4,
GP_3_23_FN, FN_IP11_3_0,
GP_3_22_FN, FN_IP10_29_26,
GP_3_21_FN, FN_IP10_25_23,
GP_3_20_FN, FN_IP10_22_19,
GP_3_19_FN, FN_IP10_18_15,
GP_3_18_FN, FN_IP10_14_11,
GP_3_17_FN, FN_IP10_10_7,
GP_3_16_FN, FN_IP10_6_4,
GP_3_15_FN, FN_IP10_3_0,
GP_3_14_FN, FN_IP9_31_28,
GP_3_13_FN, FN_IP9_27_26,
GP_3_12_FN, FN_IP9_25_24,
GP_3_11_FN, FN_IP9_23_22,
GP_3_10_FN, FN_IP9_21_20,
GP_3_9_FN, FN_IP9_19_18,
GP_3_8_FN, FN_IP9_17_16,
GP_3_7_FN, FN_IP9_15_12,
GP_3_6_FN, FN_IP9_11_8,
GP_3_5_FN, FN_IP9_7_6,
GP_3_4_FN, FN_IP9_5_4,
GP_3_3_FN, FN_IP9_3_2,
GP_3_2_FN, FN_IP9_1_0,
GP_3_1_FN, FN_IP8_30_29,
GP_3_0_FN, FN_IP8_28 }
},
{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
GP_4_31_FN, FN_IP14_18_16,
GP_4_30_FN, FN_IP14_15_12,
GP_4_29_FN, FN_IP14_11_9,
GP_4_28_FN, FN_IP14_8_6,
GP_4_27_FN, FN_IP14_5_3,
GP_4_26_FN, FN_IP14_2_0,
GP_4_25_FN, FN_IP13_30_29,
GP_4_24_FN, FN_IP13_28_26,
GP_4_23_FN, FN_IP13_25_23,
GP_4_22_FN, FN_IP13_22_19,
GP_4_21_FN, FN_IP13_18_16,
GP_4_20_FN, FN_IP13_15_13,
GP_4_19_FN, FN_IP13_12_10,
GP_4_18_FN, FN_IP13_9_7,
GP_4_17_FN, FN_IP13_6_3,
GP_4_16_FN, FN_IP13_2_0,
GP_4_15_FN, FN_IP12_30_28,
GP_4_14_FN, FN_IP12_27_25,
GP_4_13_FN, FN_IP12_24_23,
GP_4_12_FN, FN_IP12_22_20,
GP_4_11_FN, FN_IP12_19_17,
GP_4_10_FN, FN_IP12_16_14,
GP_4_9_FN, FN_IP12_13_11,
GP_4_8_FN, FN_IP12_10_8,
GP_4_7_FN, FN_IP12_7_6,
GP_4_6_FN, FN_IP12_5_4,
GP_4_5_FN, FN_IP12_3_2,
GP_4_4_FN, FN_IP12_1_0,
GP_4_3_FN, FN_IP11_31_30,
GP_4_2_FN, FN_IP11_29_27,
GP_4_1_FN, FN_IP11_26_24,
GP_4_0_FN, FN_IP11_23_22 }
},
{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
GP_5_31_FN, FN_IP7_24_22,
GP_5_30_FN, FN_IP7_21_19,
GP_5_29_FN, FN_IP7_18_16,
GP_5_28_FN, FN_DU_DOTCLKIN2,
GP_5_27_FN, FN_IP7_26_25,
GP_5_26_FN, FN_DU_DOTCLKIN0,
GP_5_25_FN, FN_AVS2,
GP_5_24_FN, FN_AVS1,
GP_5_23_FN, FN_USB2_OVC,
GP_5_22_FN, FN_USB2_PWEN,
GP_5_21_FN, FN_IP16_7,
GP_5_20_FN, FN_IP16_6,
GP_5_19_FN, FN_USB0_OVC_VBUS,
GP_5_18_FN, FN_USB0_PWEN,
GP_5_17_FN, FN_IP16_5_3,
GP_5_16_FN, FN_IP16_2_0,
GP_5_15_FN, FN_IP15_29_28,
GP_5_14_FN, FN_IP15_27_26,
GP_5_13_FN, FN_IP15_25_23,
GP_5_12_FN, FN_IP15_22_20,
GP_5_11_FN, FN_IP15_19_18,
GP_5_10_FN, FN_IP15_17_16,
GP_5_9_FN, FN_IP15_15_14,
GP_5_8_FN, FN_IP15_13_12,
GP_5_7_FN, FN_IP15_11_9,
GP_5_6_FN, FN_IP15_8_6,
GP_5_5_FN, FN_IP15_5_3,
GP_5_4_FN, FN_IP15_2_0,
GP_5_3_FN, FN_IP14_30_28,
GP_5_2_FN, FN_IP14_27_25,
GP_5_1_FN, FN_IP14_24_22,
GP_5_0_FN, FN_IP14_21_19 }
},
/*IPSR0 - IPSR5*/
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
/* IP6_31_29 [3] */
FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
/* IP6_28_26 [3] */
FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
/* IP6_25_23 [3] */
FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
/* IP6_22_20 [3] */
FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
/* IP6_19_17 [3] */
FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
/* IP6_16_14 [3] */
FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
FN_SCL2_CIS_E, 0,
/* IP6_13_11 [3] */
FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
/* IP6_10_9 [2] */
FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
/* IP6_8_6 [3] */
FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
FN_SSI_SDATA8_C, 0, 0, 0,
/* IP6_5_3 [3] */
FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
/* IP6_2_0 [3] */
FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
},
{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
/* IP7_31 [1] */
0, 0,
/* IP7_30_29 [2] */
FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
FN_MII_RXD2,
/* IP7_28_27 [2] */
FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
/* IP7_26_25 [2] */
FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
/* IP7_24_22 [3] */
FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
0, 0, 0,
/* IP7_21_19 [3] */
FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
/* IP7_18_16 [3] */
FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
FN_GLO_SS_C, 0, 0, 0,
/* IP7_15_13 [3] */
FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
/* IP7_12_10 [3] */
FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
FN_GLO_SCLK_C, 0, 0, 0,
/* IP7_9_8 [2] */
FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
/* IP7_7_6 [2] */
FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
/* IP7_5_3 [3] */
FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
0, 0, 0,
/* IP7_2_0 [3] */
FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
},
/*IPSR8 - IPSR16*/
{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
0, 0,
0, 0,
GP_1_29_IN, GP_1_29_OUT,
GP_1_28_IN, GP_1_28_OUT,
GP_1_27_IN, GP_1_27_OUT,
GP_1_26_IN, GP_1_26_OUT,
GP_1_25_IN, GP_1_25_OUT,
GP_1_24_IN, GP_1_24_OUT,
GP_1_23_IN, GP_1_23_OUT,
GP_1_22_IN, GP_1_22_OUT,
GP_1_21_IN, GP_1_21_OUT,
GP_1_20_IN, GP_1_20_OUT,
GP_1_19_IN, GP_1_19_OUT,
GP_1_18_IN, GP_1_18_OUT,
GP_1_17_IN, GP_1_17_OUT,
GP_1_16_IN, GP_1_16_OUT,
GP_1_15_IN, GP_1_15_OUT,
GP_1_14_IN, GP_1_14_OUT,
GP_1_13_IN, GP_1_13_OUT,
GP_1_12_IN, GP_1_12_OUT,
GP_1_11_IN, GP_1_11_OUT,
GP_1_10_IN, GP_1_10_OUT,
GP_1_9_IN, GP_1_9_OUT,
GP_1_8_IN, GP_1_8_OUT,
GP_1_7_IN, GP_1_7_OUT,
GP_1_6_IN, GP_1_6_OUT,
GP_1_5_IN, GP_1_5_OUT,
GP_1_4_IN, GP_1_4_OUT,
GP_1_3_IN, GP_1_3_OUT,
GP_1_2_IN, GP_1_2_OUT,
GP_1_1_IN, GP_1_1_OUT,
GP_1_0_IN, GP_1_0_OUT, }
},
{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
0, 0,
0, 0,
GP_2_29_IN, GP_2_29_OUT,
GP_2_28_IN, GP_2_28_OUT,
GP_2_27_IN, GP_2_27_OUT,
GP_2_26_IN, GP_2_26_OUT,
GP_2_25_IN, GP_2_25_OUT,
GP_2_24_IN, GP_2_24_OUT,
GP_2_23_IN, GP_2_23_OUT,
GP_2_22_IN, GP_2_22_OUT,
GP_2_21_IN, GP_2_21_OUT,
GP_2_20_IN, GP_2_20_OUT,
GP_2_19_IN, GP_2_19_OUT,
GP_2_18_IN, GP_2_18_OUT,
GP_2_17_IN, GP_2_17_OUT,
GP_2_16_IN, GP_2_16_OUT,
GP_2_15_IN, GP_2_15_OUT,
GP_2_14_IN, GP_2_14_OUT,
GP_2_13_IN, GP_2_13_OUT,
GP_2_12_IN, GP_2_12_OUT,
GP_2_11_IN, GP_2_11_OUT,
GP_2_10_IN, GP_2_10_OUT,
GP_2_9_IN, GP_2_9_OUT,
GP_2_8_IN, GP_2_8_OUT,
GP_2_7_IN, GP_2_7_OUT,
GP_2_6_IN, GP_2_6_OUT,
GP_2_5_IN, GP_2_5_OUT,
GP_2_4_IN, GP_2_4_OUT,
GP_2_3_IN, GP_2_3_OUT,
GP_2_2_IN, GP_2_2_OUT,
GP_2_1_IN, GP_2_1_OUT,
GP_2_0_IN, GP_2_0_OUT, }
},
{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
0, 0, GP_1_29_DATA, GP_1_28_DATA,
GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
},
{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
0, 0, GP_2_29_DATA, GP_2_28_DATA,
GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
},
{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
{ },
};
static struct pinmux_info r8a7790_pinmux_info = {
.name = "r8a7790_pfc",
.unlock_reg = 0xe6060000, /* PMMR */
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_GP_0_0,
.last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
void r8a7790_pinmux_init(void)
{
register_pinmux(&r8a7790_pinmux_info);
}

92
arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h Normal file
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@ -0,0 +1,92 @@
/*
* arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __PFC_R8A7790_H__
#define __PFC_R8A7790_H__
#include <sh_pfc.h>
#include <asm/gpio.h>
#define CPU_32_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_1(fn, pfx##31, sfx)
#define CPU_32_PORT2(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx)
#if defined(CONFIG_R8A7790)
#define CPU_32_PORT1(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx) \
/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT(fn, pfx##_0_, sfx), \
CPU_32_PORT1(fn, pfx##_1_, sfx), \
CPU_32_PORT2(fn, pfx##_2_, sfx), \
CPU_32_PORT(fn, pfx##_3_, sfx), \
CPU_32_PORT(fn, pfx##_4_, sfx), \
CPU_32_PORT(fn, pfx##_5_, sfx)
#elif defined(CONFIG_R8A7791)
#define CPU_32_PORT1(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
/*
* GP_0_0_DATA -> GP_7_25_DATA
* (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
* GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
*/
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT(fn, pfx##_0_, sfx), \
CPU_32_PORT1(fn, pfx##_1_, sfx), \
CPU_32_PORT(fn, pfx##_2_, sfx), \
CPU_32_PORT(fn, pfx##_3_, sfx), \
CPU_32_PORT(fn, pfx##_4_, sfx), \
CPU_32_PORT(fn, pfx##_5_, sfx), \
CPU_32_PORT(fn, pfx##_6_, sfx), \
CPU_32_PORT1(fn, pfx##_7_, sfx)
#else
#error "NO support"
#endif
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
GP##pfx##_IN, GP##pfx##_OUT)
#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
#define PORT_10_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
#define CPU_32_PORT_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
PORT_10_REV(fn, pfx, sfx)
#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
#endif /* __PFC_R8A7790_H__ */

1117
arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c Normal file
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File diff suppressed because it is too large Load Diff

8
arch/arm/cpu/armv7/rmobile/timer.c
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@ -6,6 +6,7 @@
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/arch-armv7/globaltimer.h>
#include <asm/arch/rmobile.h>
@ -38,13 +39,16 @@ static u64 get_time_us(void)
u64 timer = get_cpu_global_timer();
timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
return timer;
}
static ulong get_time_ms(void)
{
return (ulong)(get_time_us() / 1000);
u64 us = get_time_us();
do_div(us, 1000);
return us;
}
int timer_init(void)

2
arch/arm/cpu/armv7/socfpga/Makefile
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@ -9,4 +9,4 @@
obj-y := lowlevel_init.o
obj-y += misc.o timer.o reset_manager.o system_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o

215
arch/arm/cpu/armv7/socfpga/freeze_controller.c Normal file
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@ -0,0 +1,215 @@
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/freeze_controller.h>
#include <asm/arch/timer.h>
#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_freeze_controller *freeze_controller_base =
(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
/*
* Default state from cold reset is FREEZE_ALL; the global
* flag is set to TRUE to indicate the IO banks are frozen
*/
static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
= { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
/* Freeze HPS IOs */
void sys_mgr_frzctrl_freeze_req(void)
{
u32 ioctrl_reg_offset;
u32 reg_value;
u32 reg_cfg_mask;
u32 channel_id;
/* select software FSM */
writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
/* Freeze channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset = (u32)(
&freeze_controller_base->vioctrl +
(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
/*
* Assert active low enrnsl, plniotri
* and niotri signals
*/
reg_cfg_mask =
SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
| SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
/*
* Note: Delay for 20ns at min
* Assert active low bhniotri signal and de-assert
* active high csrdone
*/
reg_cfg_mask
= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
/* Set global flag to indicate channel is frozen */
frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
}
/* Freeze channel 3 */
/*
* Assert active low enrnsl, plniotri and
* niotri signals
*/
reg_cfg_mask
= SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
| SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
/*
* assert active low bhniotri & nfrzdrv signals,
* de-assert active high csrdone and assert
* active high frzreg and nfrzdrv signals
*/
reg_value = readl(&freeze_controller_base->hioctrl);
reg_cfg_mask
= SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
reg_value
= (reg_value & ~reg_cfg_mask)
| SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
| SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
writel(reg_value, &freeze_controller_base->hioctrl);
/*
* assert active high reinit signal and de-assert
* active high pllbiasen signals
*/
reg_value = readl(&freeze_controller_base->hioctrl);
reg_value
= (reg_value &
~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
| SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
writel(reg_value, &freeze_controller_base->hioctrl);
/* Set global flag to indicate channel is frozen */
frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
}
/* Unfreeze/Thaw HPS IOs */
void sys_mgr_frzctrl_thaw_req(void)
{
u32 ioctrl_reg_offset;
u32 reg_cfg_mask;
u32 reg_value;
u32 channel_id;
/* select software FSM */
writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
/* Thaw channel 0 to 2 */
for (channel_id = 0; channel_id <= 2; channel_id++) {
ioctrl_reg_offset
= (u32)(&freeze_controller_base->vioctrl
+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
/*
* Assert active low bhniotri signal and
* de-assert active high csrdone
*/
reg_cfg_mask
= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
/*
* Note: Delay for 20ns at min
* de-assert active low plniotri and niotri signals
*/
reg_cfg_mask
= SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
/*
* Note: Delay for 20ns at min
* de-assert active low enrnsl signal
*/
setbits_le32(ioctrl_reg_offset,
SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
/* Set global flag to indicate channel is thawed */
frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
}
/* Thaw channel 3 */
/* de-assert active high reinit signal */
clrbits_le32(&freeze_controller_base->hioctrl,
SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
/*
* Note: Delay for 40ns at min
* assert active high pllbiasen signals
*/
setbits_le32(&freeze_controller_base->hioctrl,
SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
/*
* Delay 1000 intosc. intosc is based on eosc1
* Use worst case which is fatest eosc1=50MHz, delay required
* is 1/50MHz * 1000 = 20us
*/
udelay(20);
/*
* de-assert active low bhniotri signals,
* assert active high csrdone and nfrzdrv signal
*/
reg_value = readl(&freeze_controller_base->hioctrl);
reg_value = (reg_value
| SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
& ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
writel(reg_value, &freeze_controller_base->hioctrl);
/*
* Delay 33 intosc
* Use worst case which is fatest eosc1=50MHz, delay required
* is 1/50MHz * 33 = 660ns ~= 1us
*/
udelay(1);
/* de-assert active low plniotri and niotri signals */
reg_cfg_mask
= SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
/*
* Note: Delay for 40ns at min
* de-assert active high frzreg signal
*/
clrbits_le32(&freeze_controller_base->hioctrl,
SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
/*
* Note: Delay for 40ns at min
* de-assert active low enrnsl signal
*/
setbits_le32(&freeze_controller_base->hioctrl,
SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
/* Set global flag to indicate channel is thawed */
frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
}

9
arch/arm/cpu/armv7/socfpga/spl.c
View File

@ -13,6 +13,7 @@
#include <asm/arch/reset_manager.h>
#include <spl.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/freeze_controller.h>
DECLARE_GLOBAL_DATA_PTR;
@ -27,6 +28,10 @@ u32 spl_boot_device(void)
void spl_board_init(void)
{
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
/* configure the pin muxing through system manager */
sysmgr_pinmux_init();
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
@ -34,6 +39,10 @@ void spl_board_init(void)
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
debug("Unfreezing/Thaw all I/O banks\n");
/* unfreeze / thaw all IO banks */
sys_mgr_frzctrl_thaw_req();
/* enable console uart printing */
preloader_console_init();
}

9
arch/arm/cpu/armv7/zynq/cpu.c
View File

@ -16,23 +16,24 @@ void lowlevel_init(void)
int arch_cpu_init(void)
{
zynq_slcr_unlock();
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
#if (CONFIG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
writel(0x1F, &slcr_base->ocm_cfg);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
writel(0x0, &slcr_base->fpga_rst_ctrl);
/* TZ_DDR_RAM, Set DDR trust zone non-secure */
writel(0xFFFFFFFF, &slcr_base->trust_zone);
/* Set urgent bits with register */
writel(0x0, &slcr_base->ddr_urgent_sel);
/* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent);
#endif
zynq_slcr_lock();

12
arch/arm/cpu/at91-common/Makefile Normal file
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@ -0,0 +1,12 @@
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2013 Atmel Corporation
# Bo Shen <voice.shen@atmel.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o

124
arch/arm/cpu/at91-common/mpddrc.c Normal file
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@ -0,0 +1,124 @@
/*
* Copyright (C) 2013 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/atmel_mpddrc.h>
static inline void atmel_mpddr_op(int mode, u32 ram_address)
{
struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
writel(mode, &mpddr->mr);
writel(0, ram_address);
}
int ddr2_init(const unsigned int ram_address,
const struct atmel_mpddr *mpddr_value)
{
struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
u32 ba_off, cr;
/* Compute bank offset according to NC in configuration register */
ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
/* Program the memory device type into the memory device register */
writel(mpddr_value->md, &mpddr->md);
/* Program the configuration register */
writel(mpddr_value->cr, &mpddr->cr);
/* Program the timing register */
writel(mpddr_value->tpr0, &mpddr->tpr0);
writel(mpddr_value->tpr1, &mpddr->tpr1);
writel(mpddr_value->tpr2, &mpddr->tpr2);
/* Issue a NOP command */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
/* A 200 us is provided to precede any signal toggle */
udelay(200);
/* Issue a NOP command */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
/* Issue an all banks precharge command */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
/* Issue an extended mode register set(EMRS2) to choose operation */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x2 << ba_off));
/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x3 << ba_off));
/*
* Issue an extended mode register set(EMRS1) to enable DLL and
* program D.I.C (output driver impedance control)
*/
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x1 << ba_off));
/* Enable DLL reset */
cr = readl(&mpddr->cr);
writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
/* A mode register set(MRS) cycle is issued to reset DLL */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
/* Issue an all banks precharge command */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
/* Two auto-refresh (CBR) cycles are provided */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
/* Disable DLL reset */
cr = readl(&mpddr->cr);
writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
/* A mode register set (MRS) cycle is issued to disable DLL reset */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
/* Set OCD calibration in default state */
cr = readl(&mpddr->cr);
writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
/*
* An extended mode register set (EMRS1) cycle is issued
* to OCD default value
*/
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x1 << ba_off));
/* OCD calibration mode exit */
cr = readl(&mpddr->cr);
writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
/*
* An extended mode register set (EMRS1) cycle is issued
* to enable OCD exit
*/
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x1 << ba_off));
/* A nornal mode command is provided */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
/* Perform a write access to any DDR2-SDRAM address */
writel(0, ram_address);
/* Write the refresh rate */
writel(mpddr_value->rtr, &mpddr->rtr);
return 0;
}

57
arch/arm/cpu/at91-common/phy.c Normal file
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@ -0,0 +1,57 @@
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2012
* Markus Hubig <mhubig@imko.de>
* IMKO GmbH <www.imko.de>
*
* Copyright (C) 2013 DENX Software Engineering, hs@denx.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/sizes.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <watchdog.h>
void at91_phy_reset(void)
{
unsigned long erstl;
unsigned long start = get_timer(0);
unsigned long const timeout = 1000; /* 1000ms */
at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/*
* Need to reset PHY -> 500ms reset
* Reset PHY by pulling the NRST line for 500ms to low. To do so
* disable user reset for low level on NRST pin and poll the NRST
* level in reset status register.
*/
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end of hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
/* avoid shutdown by watchdog */
WATCHDOG_RESET();
mdelay(10);
/* timeout for not getting stuck in an endless loop */
if (get_timer(start) >= timeout) {
puts("*** ERROR: Timeout waiting for PHY reset!\n");
break;
}
};
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
}

90
arch/arm/cpu/at91-common/spl.c Normal file
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@ -0,0 +1,90 @@
/*
* Copyright (C) 2013 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_wdt.h>
#include <asm/arch/clk.h>
#include <spl.h>
static void at91_disable_wdt(void)
{
struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
writel(AT91_WDT_MR_WDDIS, &wdt->mr);
}
void at91_plla_init(u32 pllar)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(pllar, &pmc->pllar);
while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
;
}
void at91_mck_init(u32 mckr)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
tmp = readl(&pmc->mckr);
tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
AT91_PMC_MCKR_MDIV_MASK |
AT91_PMC_MCKR_PLLADIV_2);
tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
AT91_PMC_MCKR_MDIV_MASK |
AT91_PMC_MCKR_PLLADIV_2);
writel(tmp, &pmc->mckr);
while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
;
}
u32 spl_boot_device(void)
{
#ifdef CONFIG_SYS_USE_MMC
return BOOT_DEVICE_MMC1;
#endif
return BOOT_DEVICE_NONE;
}
u32 spl_boot_mode(void)
{
switch (spl_boot_device()) {
#ifdef CONFIG_SYS_USE_MMC
case BOOT_DEVICE_MMC1:
return MMCSD_MODE_FAT;
break;
#endif
case BOOT_DEVICE_NONE:
default:
hang();
}
}
void s_init(void)
{
/* disable watchdog */
at91_disable_wdt();
/* PMC configuration */
at91_pmc_init();
at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
timer_init();
board_early_init_f();
preloader_console_init();
mem_init();
}

50
arch/arm/cpu/at91-common/u-boot-spl.lds Normal file
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@ -0,0 +1,50 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*
* (C) 2013 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
.text :
{
__start = .;
arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
__image_copy_end = .;
_end = .;
.bss :
{
. = ALIGN(4);
__bss_start = .;
*(.bss*)
. = ALIGN(4);
__bss_end = .;
} >.sdram
}

15
arch/arm/cpu/ixp/u-boot.lds
View File

@ -79,10 +79,13 @@ SECTIONS
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
.dynsym _end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

15
arch/arm/cpu/u-boot-spl.lds
View File

@ -51,12 +51,15 @@ SECTIONS
__bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
.dynsym _end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}
#if defined(CONFIG_SPL_MAX_SIZE)

18
arch/arm/cpu/u-boot.lds
View File

@ -91,12 +91,14 @@ SECTIONS
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.ARM.exidx*) }
/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
.dynsym _end : { *(.dynsym) }
.hash : { *(.hash) }
.got.plt : { *(.got.plt) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

37
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -18,7 +18,6 @@
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
#define PHY_EN_DYN_PWRDN (0x1 << 20)
@ -29,7 +28,6 @@
#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
#define MT47H128M16RT25E_RATIO 0x80
#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
@ -38,7 +36,6 @@
#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
@ -49,7 +46,6 @@
#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
#define MT41J128MJT125_EMIF_SDREF 0x0000093B
#define MT41J128MJT125_ZQ_CFG 0x50074BE4
#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
#define MT41J128MJT125_RATIO 0x40
#define MT41J128MJT125_INVERT_CLKOUT 0x1
#define MT41J128MJT125_RD_DQS 0x3B
@ -58,6 +54,12 @@
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
/* Micron MT41J64M16JT-125 */
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
/* Micron MT41J256M16JT-125 */
#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
/* Micron MT41J256M8HX-15E */
#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
@ -66,7 +68,6 @@
#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
#define MT41J256M8HX15E_RATIO 0x40
#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
#define MT41J256M8HX15E_RD_DQS 0x3B
@ -83,7 +84,6 @@
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
#define MT41K256M16HA125E_RD_DQS 0x38
@ -100,7 +100,6 @@
#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
#define MT41J512M8RH125_RATIO 0x80
#define MT41J512M8RH125_INVERT_CLKOUT 0x0
#define MT41J512M8RH125_RD_DQS 0x3B
@ -117,7 +116,6 @@
#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
#define K4B2G1646EBIH9_RATIO 0x80
#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
#define K4B2G1646EBIH9_RD_DQS 0x35
@ -149,18 +147,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr);
struct ddr_cmd_regs {
unsigned int resv0[7];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int resv1[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int resv1[3];
unsigned int cm0iclkout; /* offset 0x02C */
unsigned int resv2[8];
unsigned int cm1csratio; /* offset 0x050 */
unsigned int resv3[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int resv3[3];
unsigned int cm1iclkout; /* offset 0x060 */
unsigned int resv4[8];
unsigned int cm2csratio; /* offset 0x084 */
unsigned int resv5[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int resv5[3];
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv6[3];
};
@ -197,24 +192,21 @@ struct ddr_regs {
unsigned int cm0configclk; /* offset 0x010 */
unsigned int resv1[2];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int resv2[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int resv2[3];
unsigned int cm0iclkout; /* offset 0x02C */
unsigned int resv3[4];
unsigned int cm1config; /* offset 0x040 */
unsigned int cm1configclk; /* offset 0x044 */
unsigned int resv4[2];
unsigned int cm1csratio; /* offset 0x050 */
unsigned int resv5[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int resv5[3];
unsigned int cm1iclkout; /* offset 0x060 */
unsigned int resv6[4];
unsigned int cm2config; /* offset 0x074 */
unsigned int cm2configclk; /* offset 0x078 */
unsigned int resv7[2];
unsigned int cm2csratio; /* offset 0x084 */
unsigned int resv8[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int resv8[3];
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv9[12];
unsigned int dt0rdsratio0; /* offset 0x0C8 */
@ -243,17 +235,14 @@ struct cmd_control {
unsigned long cmd0csratio;
unsigned long cmd0csforce;
unsigned long cmd0csdelay;
unsigned long cmd0dldiff;
unsigned long cmd0iclkout;
unsigned long cmd1csratio;
unsigned long cmd1csforce;
unsigned long cmd1csdelay;
unsigned long cmd1dldiff;
unsigned long cmd1iclkout;
unsigned long cmd2csratio;
unsigned long cmd2csforce;
unsigned long cmd2csdelay;
unsigned long cmd2dldiff;
unsigned long cmd2iclkout;
};
@ -267,8 +256,6 @@ struct ddr_data {
unsigned long datagiratio0;
unsigned long datafwsratio0;
unsigned long datawrsratio0;
unsigned long datauserank0delay;
unsigned long datadldiff0;
};
/**

5
arch/arm/include/asm/arch-at91/at91_common.h
View File

@ -22,5 +22,10 @@ void at91_spi1_hw_init(unsigned long cs_mask);
void at91_udp_hw_init(void);
void at91_uhp_hw_init(void);
void at91_lcd_hw_init(void);
void at91_plla_init(u32 pllar);
void at91_mck_init(u32 mckr);
void at91_pmc_init(void);
void mem_init(void);
void at91_phy_reset(void);
#endif /* AT91_COMMON_H */

33
arch/arm/include/asm/arch-at91/at91_pio.h
View File

@ -151,37 +151,4 @@ int at91_get_pio_value(unsigned port, unsigned pin);
#define AT91_PIO_PORTD 0x3
#define AT91_PIO_PORTE 0x4
#ifdef CONFIG_AT91_LEGACY
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#endif
#endif

16
arch/arm/include/asm/arch-at91/at91_pit.h
View File

@ -25,20 +25,4 @@ typedef struct at91_pit {
#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK)
#ifdef CONFIG_AT91_LEGACY
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
#endif /* CONFIG_AT91_LEGACY */
#endif

59
arch/arm/include/asm/arch-at91/at91_pmc.h
View File

@ -14,13 +14,15 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
#ifdef __ASSEMBLY__
#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
#ifndef __ASSEMBLY__
#else
#include <asm/types.h>
@ -73,7 +75,11 @@ typedef struct at91_pmc {
#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF)
#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8)
#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14)
#ifdef CONFIG_SAMA5D3
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7F) << 18)
#else
#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16)
#endif
#define AT91_PMC_PLLAR_29 0x20000000
#define AT91_PMC_PLLBR_USBDIV_1 0x00000000
#define AT91_PMC_PLLBR_USBDIV_2 0x10000000
@ -124,8 +130,8 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
#endif
#define AT91_PMC_MCKR_PLLADIV_1 0x00001000
#define AT91_PMC_MCKR_PLLADIV_2 0x00002000
#define AT91_PMC_MCKR_PLLADIV_1 0x00000000
#define AT91_PMC_MCKR_PLLADIV_2 0x00001000
#define AT91_PMC_IXR_MOSCS 0x00000001
#define AT91_PMC_IXR_LOCKA 0x00000002
@ -137,13 +143,6 @@ typedef struct at91_pmc {
#define AT91_PMC_IXR_PCKRDY2 0x00000400
#define AT91_PMC_IXR_PCKRDY3 0x00000800
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#endif
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@ -159,34 +158,18 @@ typedef struct at91_pmc {
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
#endif
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#endif
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#endif
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#ifdef CONFIG_AT91_LEGACY
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#endif
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
@ -198,9 +181,6 @@ typedef struct at91_pmc {
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#endif
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
@ -228,9 +208,6 @@ typedef struct at91_pmc {
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */
#endif
#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
@ -238,13 +215,6 @@ typedef struct at91_pmc {
#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#endif
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
@ -255,13 +225,6 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
#endif
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
#ifdef CONFIG_AT91_LEGACY
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
#endif /* CONFIG_AT91_LEGACY */
#endif

2
arch/arm/include/asm/arch-at91/at91_spi.h
View File

@ -118,6 +118,6 @@ typedef struct at91_spi {
#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
#endif /* CONFIG_AT91_LEGACY */
#endif /* CONFIG_ATMEL_LEGACY */
#endif

21
arch/arm/include/asm/arch-at91/at91_wdt.h
View File

@ -40,25 +40,4 @@ typedef struct at91_wdt {
#define AT91_WDT_MR_WDDBGHLT 0x10000000
#define AT91_WDT_MR_WDIDLEHLT 0x20000000
#ifdef CONFIG_AT91_LEGACY
#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
#endif /* CONFIG_AT91_LEGACY */
#endif

69
arch/arm/include/asm/arch-at91/at91cap9.h
View File

@ -55,75 +55,6 @@
#define AT91_RSTC_BASE 0xfffffd00
#define AT91_PIT_BASE 0xfffffd30
#ifdef CONFIG_AT91_LEGACY
/*
* User Peripheral physical base addresses.
*/
#define AT91CAP9_BASE_UDPHS 0xfff78000
#define AT91CAP9_BASE_TCB0 0xfff7c000
#define AT91CAP9_BASE_TC0 0xfff7c000
#define AT91CAP9_BASE_TC1 0xfff7c040
#define AT91CAP9_BASE_TC2 0xfff7c080
#define AT91CAP9_BASE_MCI0 0xfff80000
#define AT91CAP9_BASE_MCI1 0xfff84000
#define AT91CAP9_BASE_TWI 0xfff88000
#define AT91CAP9_BASE_US0 0xfff8c000
#define AT91CAP9_BASE_US1 0xfff90000
#define AT91CAP9_BASE_US2 0xfff94000
#define AT91CAP9_BASE_SSC0 0xfff98000
#define AT91CAP9_BASE_SSC1 0xfff9c000
#define AT91CAP9_BASE_AC97C 0xfffa0000
#define AT91CAP9_BASE_SPI0 0xfffa4000
#define AT91CAP9_BASE_SPI1 0xfffa8000
#define AT91CAP9_BASE_CAN 0xfffac000
#define AT91CAP9_BASE_PWMC 0xfffb8000
#define AT91CAP9_BASE_EMAC 0xfffbc000
#define AT91CAP9_BASE_ADC 0xfffc0000
#define AT91CAP9_BASE_ISI 0xfffc4000
#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
/*
* SCKCR flags
*/
#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
#endif /* CONFIG_AT91_LEGACY */
/*
* Internal Memory.
*/

60
arch/arm/include/asm/arch-at91/at91sam9_smc.h
View File

@ -73,64 +73,4 @@ typedef struct at91_smc {
#define AT91_SMC_MODE_PS_16 0x20000000
#define AT91_SMC_MODE_PS_32 0x30000000
#ifdef CONFIG_AT91_LEGACY
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28) /* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#endif
#endif
#endif

115
arch/arm/include/asm/arch-at91/atmel_mpddrc.h Normal file
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@ -0,0 +1,115 @@
/*
* Copyright (C) 2013 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ATMEL_MPDDRC_H__
#define __ATMEL_MPDDRC_H__
/*
* Only define the needed register in mpddr
* If other register needed, will add them later
*/
struct atmel_mpddr {
u32 mr;
u32 rtr;
u32 cr;
u32 tpr0;
u32 tpr1;
u32 tpr2;
u32 reserved[2];
u32 md;
};
int ddr2_init(const unsigned int ram_address,
const struct atmel_mpddr *mpddr);
/* Bit field in mode register */
#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2
#define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3
#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4
#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5
#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6
#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7
/* Bit field in configuration register */
#define ATMEL_MPDDRC_CR_NC_MASK 0x3
#define ATMEL_MPDDRC_CR_NC_COL_9 0x0
#define ATMEL_MPDDRC_CR_NC_COL_10 0x1
#define ATMEL_MPDDRC_CR_NC_COL_11 0x2
#define ATMEL_MPDDRC_CR_NC_COL_12 0x3
#define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2)
#define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2)
#define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2)
#define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2)
#define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2)
#define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4)
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4)
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4)
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4)
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4)
#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4)
#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7)
#define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8)
#define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9)
#define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12)
#define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17)
#define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20)
#define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21)
#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22)
#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23)
/* Bit field in timing parameter 0 register */
#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0
#define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf
#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4
#define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf
#define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8
#define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf
#define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12
#define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf
#define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16
#define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf
#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20
#define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf
#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24
#define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7
#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27
#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1
#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28
#define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf
/* Bit field in timing parameter 1 register */
#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0
#define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f
#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8
#define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff
#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16
#define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff
#define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24
#define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf
/* Bit field in timing parameter 2 register */
#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0
#define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf
#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4
#define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf
#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8
#define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf
#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12
#define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7
#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16
#define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf
/* Bit field in Memory Device Register */
#define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3
#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4)
#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4)
#endif

26
arch/arm/include/asm/arch-at91/gpio.h
View File

@ -16,7 +16,7 @@
#ifdef CONFIG_ATMEL_LEGACY
#define PIN_BASE 32
#define PIN_BASE 0
#define MAX_GPIO_BANKS 5
@ -231,4 +231,26 @@ static inline unsigned pin_to_mask(unsigned pin)
#define at91_set_gpio_value(x, y) at91_set_pio_value(x, y)
#define at91_get_gpio_value(x) at91_get_pio_value(x)
#endif
#endif
#define GPIO_PIOA_BASE (0)
#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x))
#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x))
#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x))
#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x))
#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x))
static inline unsigned at91_gpio_to_port(unsigned gpio)
{
return gpio / 32;
}
static inline unsigned at91_gpio_to_pin(unsigned gpio)
{
return gpio % 32;
}
#endif /* __ASM_ARCH_AT91_GPIO_H */

3
arch/arm/include/asm/arch-at91/sama5d3.h
View File

@ -79,6 +79,7 @@
#define ARCH_EXID_SAMA5D33 0x00414300
#define ARCH_EXID_SAMA5D34 0x00414301
#define ARCH_EXID_SAMA5D35 0x00584300
#define ARCH_EXID_SAMA5D36 0x00004301
#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3)
#define cpu_is_sama5d31() (cpu_is_sama5d3() && \
@ -89,6 +90,8 @@
(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
#define cpu_is_sama5d35() (cpu_is_sama5d3() && \
(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
#define cpu_is_sama5d36() (cpu_is_sama5d3() && \
(get_extension_chip_id() == ARCH_EXID_SAMA5D36))
/*
* User Peripherals physical base addresses.

20
arch/arm/include/asm/arch-at91/spl.h Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (C) 2013 Atmel Corporation
* Bo Shen <voice.shen@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
enum {
BOOT_DEVICE_NONE,
#ifdef CONFIG_SYS_USE_MMC
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC2,
BOOT_DEVICE_MMC2_2,
#endif
};
#endif

3
arch/arm/include/asm/arch-davinci/hardware.h
View File

@ -478,8 +478,9 @@ struct davinci_syscfg_regs {
dv_reg rsvd[13];
dv_reg kick0;
dv_reg kick1;
dv_reg rsvd1[53];
dv_reg rsvd1[52];
dv_reg mstpri[3];
dv_reg rsvd2;
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;

4
arch/arm/include/asm/arch-exynos/dwmmc.h
View File

@ -6,10 +6,6 @@
*/
#define DWMCI_CLKSEL 0x09C
#define DWMCI_SHIFT_0 0x0
#define DWMCI_SHIFT_1 0x1
#define DWMCI_SHIFT_2 0x2
#define DWMCI_SHIFT_3 0x3
#define DWMCI_SET_SAMPLE_CLK(x) (x)
#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)

2
arch/arm/include/asm/arch-exynos/mmc.h
View File

@ -55,7 +55,7 @@
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
static inline int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() +
(S5P_MMC_DEV_OFFSET * index);

2
arch/arm/include/asm/arch-exynos/power.h
View File

@ -16,7 +16,7 @@ struct exynos4_power {
unsigned int gnss_rtc_out_ctrl;
unsigned char res2[0x1ec];
unsigned int system_power_down_ctrl;
unsigned char res3[0x1];
unsigned int res3;
unsigned int system_power_down_option;
unsigned char res4[0x1f4];
unsigned int swreset;

1
arch/arm/include/asm/arch-exynos/spi.h
View File

@ -30,6 +30,7 @@ struct exynos_spi {
#define EXYNOS_SPI_MAX_FREQ 50000000
#define SPI_TIMEOUT_MS 10
#define SF_READ_DATA_CMD 0x3
/* SPI_CHCFG */
#define SPI_CH_HS_EN (1 << 6)

2
arch/arm/include/asm/arch-omap3/clock.h
View File

@ -27,8 +27,6 @@
#define ICK_DSS_ON 0x00000001
#define FCK_CAM_ON 0x00000001
#define ICK_CAM_ON 0x00000001
#define FCK_PER_ON 0x0003ffff
#define ICK_PER_ON 0x0003ffff
/* Used to index into DPLL parameter tables */
typedef struct {

1
arch/arm/include/asm/arch-omap3/omap3.h
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@ -55,6 +55,7 @@ struct control_prog_io {
#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
/* General Purpose Timers */
#define OMAP34XX_GPT1 0x48318000

4
arch/arm/include/asm/arch-omap4/sys_proto.h
View File

@ -16,6 +16,10 @@
DECLARE_GLOBAL_DATA_PTR;
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
struct omap_sysinfo {
char *board_string;
};

3
arch/arm/include/asm/arch-omap5/clock.h
View File

@ -137,6 +137,9 @@
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)

4
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -64,6 +64,9 @@
/* QSPI */
#define QSPI_BASE 0x4B300000
/* SATA */
#define DWC_AHSATA_BASE 0x4A140000
/*
* Hardware Register Details
*/
@ -239,6 +242,7 @@ struct ctrl_ioregs {
u32 ctrl_ddrio_1;
u32 ctrl_ddrio_2;
u32 ctrl_emif_sdram_config_ext;
u32 ctrl_emif_sdram_config_ext_final;
u32 ctrl_ddr_ctrl_ext_0;
};

48
arch/arm/include/asm/arch-omap5/sata.h Normal file
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@ -0,0 +1,48 @@
/*
* SATA Wrapper Register map
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TI_SATA_H
#define _TI_SATA_H
/* SATA Wrapper module */
#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100)
/* SATA PHY Module */
#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800)
/* SATA Wrapper register offsets */
#define TI_SATA_SYSCONFIG 0x00
#define TI_SATA_CDRLOCK 0x04
/* Register Set */
#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16)
#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4)
#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2)
/* Standby modes */
#define TI_SATA_STANDBY_FORCE 0x0
#define TI_SATA_STANDBY_NO (0x1 << 4)
#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4)
#define TI_SATA_STANDBY_SMART (0x2 << 4)
/* Idle modes */
#define TI_SATA_IDLE_FORCE 0x0
#define TI_SATA_IDLE_NO (0x1 << 2)
#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2)
#define TI_SATA_IDLE_SMART (0x2 << 2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int omap_sata_init(void);
#else
static inline int omap_sata_init(void)
{
return 0;
}
#endif /* CONFIG_SCSI_AHCI_PLAT */
#endif /* _TI_SATA_H */

6
arch/arm/include/asm/arch-rmobile/gpio.h
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@ -7,6 +7,12 @@ void sh73a0_pinmux_init(void);
#elif defined(CONFIG_R8A7740)
#include "r8a7740-gpio.h"
void r8a7740_pinmux_init(void);
#elif defined(CONFIG_R8A7790)
#include "r8a7790-gpio.h"
void r8a7790_pinmux_init(void);
#elif defined(CONFIG_R8A7791)
#include "r8a7791-gpio.h"
void r8a7791_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */

387
arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h Normal file
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@ -0,0 +1,387 @@
#ifndef __ASM_R8A7790_H__
#define __ASM_R8A7790_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
GPIO_GP_1_28, GPIO_GP_1_29,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
GPIO_GP_2_28, GPIO_GP_2_29,
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS,
GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2,
GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2,
/* IPSR0 */
GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5,
GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2,
GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B,
GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4,
GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4,
GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5,
GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5,
GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6,
GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B,
GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C,
GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C,
GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0,
GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0,
/* IPSR1 */
GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1,
GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10,
GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2,
GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11,
GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3,
GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3,
GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4,
GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4,
GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N,
GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14,
GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B,
GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6,
GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B,
GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7,
GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4,
/* IPSR2 */
GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3,
GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B,
GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1,
GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7,
GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3,
GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4,
GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B,
GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5,
GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B,
GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6,
GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B,
/* IPSR3 */
GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0,
GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B,
GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1,
GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B,
GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2,
GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2,
GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B,
GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15,
GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16,
GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N,
GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19,
GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20,
GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4,
/* IPSR4 */
GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B,
GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5,
GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2,
GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24,
GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB,
GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6,
GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N,
GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B,
GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B,
GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B,
GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B,
GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK,
GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B,
GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B,
GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2,
/* IPSR5 */
GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1,
GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N,
GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N,
GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B,
GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX,
GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2,
GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N,
GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B,
GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N,
GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3,
GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B,
GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK,
GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B,
GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4,
GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B,
GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N,
GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B,
GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N,
GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C,
GPIO_FN_SSI_WS78_B,
/* IPSR6 */
GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B,
GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C,
GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B,
GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1,
GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C,
GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B,
GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N,
GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B,
GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B,
GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E,
GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER,
GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C,
GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0,
GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C,
GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1,
GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B,
GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G,
GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E,
GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E,
GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E,
GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F,
/* IPSR7 */
GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E,
GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1,
GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F,
GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C,
GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC,
GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0,
GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C,
GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B,
GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0,
GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C,
GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C,
GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C,
GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C,
GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN,
GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK,
GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1,
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2,
GPIO_FN_MII_RXD2,
/* IPSR8 */
GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3,
GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N,
GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N,
GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N,
GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1,
GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER,
GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK,
GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV,
GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D,
GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1,
GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC,
GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO,
GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D,
GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D,
GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5,
GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK,
GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD,
GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B,
/* IPSR9 */
GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B,
GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B,
GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B,
GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B,
GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP,
GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B,
GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP,
GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN,
GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B,
GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK,
GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD,
GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B,
GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK,
GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK,
GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2,
GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B,
GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0,
GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6,
GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B,
GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B,
GPIO_FN_VI3_CLK_B,
/* IPSR10 */
GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN,
GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D,
GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK,
GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B,
GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D,
GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D,
GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B,
GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B,
GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D,
GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B,
GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA,
GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D,
GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B,
GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK,
GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B,
GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3,
GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B,
GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B,
GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4,
GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0,
GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B,
GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B,
/* IPSR11 */
GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN,
GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D,
GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B,
GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD,
GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N,
GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2,
GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3,
GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1,
GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP,
GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C,
GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F,
GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B,
GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B,
GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN,
GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C,
GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B,
GPIO_FN_MOUT0,
/* IPSR12 */
GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1,
GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2,
GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5,
GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6,
GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK,
GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34,
GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC,
GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0,
GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK,
GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N,
GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0,
GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N,
GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1,
GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD,
GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK,
GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS,
GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD,
GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE,
GPIO_FN_CAN_DEBUGOUT4,
/* IPSR13 */
GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2,
GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6,
GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C,
GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6,
GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6,
GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4,
GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6,
GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5,
GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1,
GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6,
GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1,
GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7,
GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7,
GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N,
GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11,
GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B,
GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8,
GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C,
GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9,
GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1,
GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA,
GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14,
/* IPSR14 */
GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D,
GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15,
GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0,
GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C,
GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0,
GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1,
GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N,
GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3,
GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C,
GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS,
GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B,
GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1,
GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1,
GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK,
GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK,
GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS,
GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE,
GPIO_FN_HRTS0_N_C,
/* IPSR15 */
GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7,
GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN,
GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS,
GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17,
GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0,
GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0,
GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3,
GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4,
GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5,
GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK,
GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0,
GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23,
GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0,
GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1,
GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14,
/* IPSR16 */
GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2,
GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B,
GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2,
GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C,
GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC,
GPIO_FN_TCLK1_B,
};
#endif /* __ASM_R8A7790_H__ */

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arch/arm/include/asm/arch-rmobile/r8a7790.h Normal file
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/*
* arch/arm/include/asm/arch-rmobile/r8a7790.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7790_H
#define __ASM_ARCH_R8A7790_H
/*
* R8A7790 I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xFEC00200
#define DBSC3_0_BASE 0xE6790000
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define S3C_QOS_DCACHE_BASE 0xE6784BDC
#define S3C_QOS_CCI0_BASE 0xE6784C00
#define S3C_QOS_CCI1_BASE 0xE6784C24
#define S3C_QOS_MXI_BASE 0xE6784C48
#define S3C_QOS_AXI_BASE 0xE6784C6C
#define DBSC3_0_QOS_R0_BASE 0xE6791000
#define DBSC3_0_QOS_R1_BASE 0xE6791100
#define DBSC3_0_QOS_R2_BASE 0xE6791200
#define DBSC3_0_QOS_R3_BASE 0xE6791300
#define DBSC3_0_QOS_R4_BASE 0xE6791400
#define DBSC3_0_QOS_R5_BASE 0xE6791500
#define DBSC3_0_QOS_R6_BASE 0xE6791600
#define DBSC3_0_QOS_R7_BASE 0xE6791700
#define DBSC3_0_QOS_R8_BASE 0xE6791800
#define DBSC3_0_QOS_R9_BASE 0xE6791900
#define DBSC3_0_QOS_R10_BASE 0xE6791A00
#define DBSC3_0_QOS_R11_BASE 0xE6791B00
#define DBSC3_0_QOS_R12_BASE 0xE6791C00
#define DBSC3_0_QOS_R13_BASE 0xE6791D00
#define DBSC3_0_QOS_R14_BASE 0xE6791E00
#define DBSC3_0_QOS_R15_BASE 0xE6791F00
#define DBSC3_0_QOS_W0_BASE 0xE6792000
#define DBSC3_0_QOS_W1_BASE 0xE6792100
#define DBSC3_0_QOS_W2_BASE 0xE6792200
#define DBSC3_0_QOS_W3_BASE 0xE6792300
#define DBSC3_0_QOS_W4_BASE 0xE6792400
#define DBSC3_0_QOS_W5_BASE 0xE6792500
#define DBSC3_0_QOS_W6_BASE 0xE6792600
#define DBSC3_0_QOS_W7_BASE 0xE6792700
#define DBSC3_0_QOS_W8_BASE 0xE6792800
#define DBSC3_0_QOS_W9_BASE 0xE6792900
#define DBSC3_0_QOS_W10_BASE 0xE6792A00
#define DBSC3_0_QOS_W11_BASE 0xE6792B00
#define DBSC3_0_QOS_W12_BASE 0xE6792C00
#define DBSC3_0_QOS_W13_BASE 0xE6792D00
#define DBSC3_0_QOS_W14_BASE 0xE6792E00
#define DBSC3_0_QOS_W15_BASE 0xE6792F00
#define DBSC3_0_DBADJ2 0xE67900C8
#define CCI_400_MAXOT_1 0xF0091110
#define CCI_400_MAXOT_2 0xF0092110
#define CCI_400_QOSCNTL_1 0xF009110C
#define CCI_400_QOSCNTL_2 0xF009210C
#define MXI_BASE 0xFE960000
#define MXI_QOS_BASE 0xFE960300
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
#define SYS_AXI_IMUX0_BASE 0xFF800600
#define SYS_AXI_IMUX1_BASE 0xFF800640
#define SYS_AXI_IMUX2_BASE 0xFF800680
#define SYS_AXI_LBS_BASE 0xFF8006C0
#define SYS_AXI_MMUDS_BASE 0xFF800700
#define SYS_AXI_MMUM_BASE 0xFF800740
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_RDS_BASE 0xFF8101C0
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
#define MP_AXI_ASDS1_BASE 0xFF820200
#define MP_AXI_MLP_BASE 0xFF820240
#define MP_AXI_MMUMP_BASE 0xFF820280
#define MP_AXI_SPU_BASE 0xFF8202C0
#define MP_AXI_SPUC_BASE 0xFF820300
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
#define CCI_AXI_MMUR_BASE 0xFF880180
#define CCI_AXI_MMUDS_BASE 0xFF8801C0
#define CCI_AXI_MMUM_BASE 0xFF880200
#define CCI_AXI_MXI_BASE 0xFF880240
#define CCI_AXI_MMUS1_BASE 0xFF880280
#define CCI_AXI_MMUMP_BASE 0xFF8802C0
#define MEDIA_AXI_JPR_BASE 0xFE964100
#define MEDIA_AXI_JPW_BASE 0xFE966100
#define MEDIA_AXI_GCU0R_BASE 0xFE964140
#define MEDIA_AXI_GCU0W_BASE 0xFE966140
#define MEDIA_AXI_GCU1R_BASE 0xFE964180
#define MEDIA_AXI_GCU1W_BASE 0xFE966180
#define MEDIA_AXI_TDMR_BASE 0xFE964500
#define MEDIA_AXI_TDMW_BASE 0xFE966500
#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
#define MEDIA_AXI_IMSW_BASE 0xFE966D80
#define MEDIA_AXI_VSP1R_BASE 0xFE965100
#define MEDIA_AXI_VSP1W_BASE 0xFE967100
#define MEDIA_AXI_FDP1R_BASE 0xFE965140
#define MEDIA_AXI_FDP1W_BASE 0xFE967140
#define MEDIA_AXI_IMRR_BASE 0xFE965180
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
#define MEDIA_AXI_VPC0R_BASE 0xFE965980
#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
#define SYS_AXI_CSDMSCR 0xFF802014
#define SYS_AXI_DDMDMSCR 0xFF802018
#define SYS_AXI_ETHDMSCR 0xFF80201C
#define SYS_AXI_G2DDMSCR 0xFF802020
#define SYS_AXI_IMP0DMSCR 0xFF802024
#define SYS_AXI_IMP1DMSCR 0xFF802028
#define SYS_AXI_LBSDMSCR 0xFF80202C
#define SYS_AXI_MMUDSDMSCR 0xFF802030
#define SYS_AXI_MMUMXDMSCR 0xFF802034
#define SYS_AXI_MMURDDMSCR 0xFF802038
#define SYS_AXI_MMUS0DMSCR 0xFF80203C
#define SYS_AXI_MMUS1DMSCR 0xFF802040
#define SYS_AXI_MPXDMSCR 0xFF802044
#define SYS_AXI_MTSB0DMSCR 0xFF802048
#define SYS_AXI_MTSB1DMSCR 0xFF80204C
#define SYS_AXI_PCIDMSCR 0xFF802050
#define SYS_AXI_RTXDMSCR 0xFF802054
#define SYS_AXI_SAT0DMSCR 0xFF802058
#define SYS_AXI_SAT1DMSCR 0xFF80205C
#define SYS_AXI_SDM0DMSCR 0xFF802060
#define SYS_AXI_SDM1DMSCR 0xFF802064
#define SYS_AXI_SDS0DMSCR 0xFF802068
#define SYS_AXI_SDS1DMSCR 0xFF80206C
#define SYS_AXI_ETRABDMSCR 0xFF802070
#define SYS_AXI_ETRKFDMSCR 0xFF802074
#define SYS_AXI_UDM0DMSCR 0xFF802078
#define SYS_AXI_UDM1DMSCR 0xFF80207C
#define SYS_AXI_USB20DMSCR 0xFF802080
#define SYS_AXI_USB21DMSCR 0xFF802084
#define SYS_AXI_USB22DMSCR 0xFF802088
#define SYS_AXI_USB30DMSCR 0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
#define SYS_AXI_LBSSLVDMSCR 0xFF802128
#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
#define SYS_AXI_MPXSLVDMSCR 0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
#define SYS_AXI_MXTSLVDMSCR 0xFF802140
#define SYS_AXI_PCISLVDMSCR 0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
#define RT_AXI_RDMDMSCR 0xFF812008
#define RT_AXI_RDSDMSCR 0xFF81200C
#define RT_AXI_STRDMSCR 0xFF812010
#define RT_AXI_SY2RTDMSCR 0xFF812014
#define RT_AXI_CBSSLVDMSCR 0xFF812100
#define RT_AXI_DBSSLVDMSCR 0xFF812104
#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
#define MP_AXI_ADSPDMSCR 0xFF822000
#define MP_AXI_ASDM0DMSCR 0xFF822004
#define MP_AXI_ASDM1DMSCR 0xFF822008
#define MP_AXI_ASDS0DMSCR 0xFF82200C
#define MP_AXI_ASDS1DMSCR 0xFF822010
#define MP_AXI_MLPDMSCR 0xFF822014
#define MP_AXI_MMUMPDMSCR 0xFF822018
#define MP_AXI_SPUDMSCR 0xFF82201C
#define MP_AXI_SPUCDMSCR 0xFF822020
#define MP_AXI_SY2MPDMSCR 0xFF822024
#define MP_AXI_ADSPSLVDMSCR 0xFF822100
#define MP_AXI_MLMSLVDMSCR 0xFF822104
#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
#define MP_AXI_SPUSLVDMSCR 0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
#define ADM_AXI_ASDM0DMSCR 0xFF842000
#define ADM_AXI_ASDM1DMSCR 0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
#define DM_AXI_RAP5SLVDMSCR 0xFF852110
#define DM_AXI_SAP4SLVDMSCR 0xFF852114
#define DM_AXI_SAP5SLVDMSCR 0xFF852118
#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
#define DM_AXI_SAP65SLVDMSCR 0xFF852120
#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
#define SYS_AXI256_MXIDMSCR 0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
#define MXT_FDPSLVDMSCR 0xFF87210C
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VPC0SLVDMSCR 0xFF872118
#define MXT_VPC1SLVDMSCR 0xFF87211C
#define MXT_VSP0SLVDMSCR 0xFF872120
#define MXT_VSP1SLVDMSCR 0xFF872124
#define MXT_VSPD0SLVDMSCR 0xFF872128
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
#define CCI_AXI_MMURDMSCR 0xFF882008
#define CCI_AXI_MMUDSDMSCR 0xFF88200C
#define CCI_AXI_MMUMDMSCR 0xFF882010
#define CCI_AXI_MXIDMSCR 0xFF882014
#define CCI_AXI_MMUS1DMSCR 0xFF882018
#define CCI_AXI_MMUMPDMSCR 0xFF88201C
#define CCI_AXI_DVMDMSCR 0xFF882020
#define CCI_AXI_CCISLVDMSCR 0xFF882100
#define CCI_AXI_IPMMUIDVMCR 0xFF880400
#define CCI_AXI_IPMMURDVMCR 0xFF880404
#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7790_rwdt {
u32 rwtcnt; /* 0x00 */
u32 rwtcsra; /* 0x04 */
u16 rwtcsrb; /* 0x08 */
};
/* SWDT */
struct r8a7790_swdt {
u32 swtcnt; /* 0x00 */
u32 swtcsra; /* 0x04 */
u16 swtcsrb; /* 0x08 */
};
/* LBSC */
struct r8a7790_lbsc {
u32 cs0ctrl;
u32 cs1ctrl;
u32 ecs0ctrl;
u32 ecs1ctrl;
u32 ecs2ctrl;
u32 ecs3ctrl;
u32 ecs4ctrl;
u32 ecs5ctrl;
u32 dummy0[4]; /* 0x20 .. 0x2C */
u32 cswcr0;
u32 cswcr1;
u32 ecswcr0;
u32 ecswcr1;
u32 ecswcr2;
u32 ecswcr3;
u32 ecswcr4;
u32 ecswcr5;
u32 exdmawcr0;
u32 exdmawcr1;
u32 exdmawcr2;
u32 dummy1[9]; /* 0x5C .. 0x7C */
u32 cspwcr0;
u32 cspwcr1;
u32 ecspwcr0;
u32 ecspwcr1;
u32 ecspwcr2;
u32 ecspwcr3;
u32 ecspwcr4;
u32 ecspwcr5;
u32 exwtsync;
u32 dummy2[3]; /* 0xA4 .. 0xAC */
u32 cs0bstctl;
u32 cs0btph;
u32 dummy3[2]; /* 0xB8 .. 0xBC */
u32 cs1gdst;
u32 ecs0gdst;
u32 ecs1gdst;
u32 ecs2gdst;
u32 ecs3gdst;
u32 ecs4gdst;
u32 ecs5gdst;
u32 dummy4[5]; /* 0xDC .. 0xEC */
u32 exdmaset0;
u32 exdmaset1;
u32 exdmaset2;
u32 dummy5[5]; /* 0xFC .. 0x10C */
u32 exdmcr0;
u32 exdmcr1;
u32 exdmcr2;
u32 dummy6[5]; /* 0x11C .. 0x12C */
u32 bcintsr;
u32 bcintcr;
u32 bcintmr;
u32 dummy7; /* 0x13C */
u32 exbatlv;
u32 exwtsts;
u32 dummy8[14]; /* 0x148 .. 0x17C */
u32 atacsctrl;
u32 dummy9[15]; /* 0x184 .. 0x1BC */
u32 exbct;
u32 extct;
};
/* DBSC3 */
struct r8a7790_dbsc3 {
u32 dummy0[3]; /* 0x00 .. 0x08 */
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2C */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3C */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4C */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xAC */
u32 dbbl;
u32 dummy5[3]; /* 0xB4 .. 0xBC */
u32 dbadj0;
u32 dummy6; /* 0xC4 */
u32 dbadj2;
u32 dummy7[5]; /* 0xCC .. 0xDC */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dummy8[2]; /* 0xEC .. 0xF0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy9; /* 0xFC */
u32 dbrnk0;
u32 dummy10[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy11[47]; /* 0x184 ..0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[14]; /* 0x248 .. 0x27C */
u32 dbpdlck;
u32 dummy13[3]; /* 0x284 .. 0x28C */
u32 dbpdrga;
u32 dummy14[3]; /* 0x294 .. 0x29C */
u32 dbpdrgd;
u32 dummy15[24]; /* 0x2A4 .. 0x300 */
u32 dbbs0cnt1;
u32 dummy16[30]; /* 0x308 .. 0x37C */
u32 dbwt0cnf0;
u32 dbwt0cnf1;
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
};
/* GPIO */
struct r8a7790_gpio {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 indt;
u32 intdt;
u32 intclr;
u32 intmsk;
u32 posneg;
u32 edglevel;
u32 filonoff;
u32 intmsks;
u32 mskclrs;
u32 outdtsel;
u32 outdth;
u32 outdtl;
u32 bothedge;
};
/* S3C(QoS) */
struct r8a7790_s3c {
u32 s3cexcladdmsk;
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
u32 s3carcr11;
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;
u32 dummy1[2]; /* 0x20 .. 0x24 */
u32 s3cmctr;
u32 dummy2; /* 0x2C */
u32 cconf0;
u32 cconf1;
u32 cconf2;
u32 cconf3;
};
struct r8a7790_s3c_qos {
u32 s3cqos0;
u32 s3cqos1;
u32 s3cqos2;
u32 s3cqos3;
u32 s3cqos4;
u32 s3cqos5;
u32 s3cqos6;
u32 s3cqos7;
u32 s3cqos8;
};
/* DBSC(QoS) */
struct r8a7790_dbsc3_qos {
u32 dblgcnt;
u32 dbtmval0;
u32 dbtmval1;
u32 dbtmval2;
u32 dbtmval3;
u32 dbrqctr;
u32 dbthres0;
u32 dbthres1;
u32 dbthres2;
u32 dummy0; /* 0x24 */
u32 dblgqon;
};
/* MXI(QoS) */
struct r8a7790_mxi {
u32 mxsaar0;
u32 mxsaar1;
u32 dummy0[7]; /* 0x08 .. 0x20 */
u32 mxaxiracr;
u32 mxs3cracr;
u32 dummy1[2]; /* 0x2C .. 0x30 */
u32 mxaxiwacr;
u32 mxs3cwacr;
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
};
struct r8a7790_mxi_qos {
u32 vspdu0;
u32 vspdu1;
u32 du0;
u32 du1;
};
/* AXI(QoS) */
struct r8a7790_axi_qos {
u32 qosconf;
u32 qosctset0;
u32 qosctset1;
u32 qosctset2;
u32 qosctset3;
u32 qosreqctr;
u32 qosthres0;
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
};
#endif
#endif /* __ASM_ARCH_R8A7790_H */

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arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h Normal file
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#ifndef __ASM_R8A7791_H__
#define __ASM_R8A7791_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
*/
enum {
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
GPIO_GP_1_24, GPIO_GP_1_25,
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19,
GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23,
GPIO_GP_7_24, GPIO_GP_7_25,
GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA,
GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0,
GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2,
GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5,
GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7,
GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
/* IPSR0 */
GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10,
GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15,
GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B,
GPIO_FN_SCL0_C, GPIO_FN_PWM2_B,
GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B,
GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B,
GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK,
/* IPSR1 */
GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8,
GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0,
GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0,
GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D,
GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D,
GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D,
GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D,
GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN,
GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D,
GPIO_FN_A15, GPIO_FN_BPFCLK_C,
GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B,
GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C,
GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C,
/* IPSR2 */
GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C,
GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B,
GPIO_FN_A20, GPIO_FN_SPCLK,
GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0,
GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B,
GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD,
GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B,
GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD,
GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3,
GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD,
GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C,
GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD,
GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1,
GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1,
GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK,
GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC,
GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD,
GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1,
/* IPSR3 */
GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N,
GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2,
GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1,
GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B,
GPIO_FN_PWM1, GPIO_FN_TPU_TO1,
GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2,
GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B,
GPIO_FN_PWM2, GPIO_FN_TPU_TO2,
GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B,
GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D,
GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B,
GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B,
GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B,
GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B,
GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3,
GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON,
GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C,
GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B,
GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D,
GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C,
GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C,
GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C,
GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C,
/* IPSR4 */
GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B,
GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C,
GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B,
GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D,
GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B,
GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D,
GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B,
GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C,
GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B,
GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E,
GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B,
GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E,
GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B,
GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E,
GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3,
GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D,
GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D,
GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D,
GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C,
GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0,
GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B,
/* IPSR5 */
GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0,
GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B,
GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0,
GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B,
GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0,
GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B,
GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK,
GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B,
GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B,
GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B,
GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS,
GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON,
GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B,
GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B,
GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D,
GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D,
GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D,
/* IPSR6 */
GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B,
GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E,
GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B,
GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B,
GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD,
GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N,
GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N,
GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N,
GPIO_FN_IRQ3, GPIO_FN_SCL4_C,
GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N,
GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C,
GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N,
GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E,
GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B,
GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E,
GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B,
GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D,
GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B,
GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D,
/* IPSR7 */
GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D,
GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D,
GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B,
GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B,
GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B,
GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B,
GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B,
GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B,
GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B,
GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B,
GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B,
GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B,
GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B,
GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B,
GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B,
GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B,
GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B,
GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B,
/* IPSR8 */
GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11,
GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B,
GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B,
GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B,
GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B,
GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B,
GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B,
GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B,
GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B,
GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B,
GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B,
GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B,
GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B,
GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B,
GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B,
GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B,
GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B,
GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20,
GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX,
GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3,
GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX,
/* IPSR9 */
GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C,
GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD,
GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C,
GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK,
GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS,
GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK,
GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX,
GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4,
GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS,
GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE,
GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B,
GPIO_FN_DU1_DISP, GPIO_FN_QPOLA,
GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B,
GPIO_FN_VI0_CLKENB, GPIO_FN_TX4,
GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D,
GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D,
GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5,
GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D,
GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5,
GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D,
GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B,
GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4,
GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N,
/* IPSR10 */
GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4,
GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N,
GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C,
GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N,
GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C,
GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N,
GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C,
GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D,
GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C,
GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E,
GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D,
GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D,
GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D,
GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B,
GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N,
GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B,
GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N,
GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3,
GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C,
GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4,
GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C,
GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B,
GPIO_FN_TX0_C, GPIO_FN_SCL1_D,
/* IPSR11 */
GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B,
GPIO_FN_RX0_C, GPIO_FN_SDA1_D,
GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B,
GPIO_FN_TX1_C, GPIO_FN_SCL4_B,
GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E,
GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D,
GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B,
GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B,
GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B,
GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B,
GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B,
GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B,
GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5,
GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6,
GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7,
GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER,
GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO,
GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV,
GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC,
GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC,
GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C,
GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C,
/* IPSR12 */
GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7,
GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7,
GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C,
GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E,
GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C,
GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E,
GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B,
GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E,
GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B,
GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E,
GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3,
GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B,
GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C,
GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C,
GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C,
GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D,
GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C,
GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D,
GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C,
/* IPSR13 */
GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C,
GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C,
GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK,
GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C,
GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL,
GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C,
GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B,
GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C,
GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B,
GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B,
GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B,
GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B,
GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B,
GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F,
GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C,
GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F,
GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C,
GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B,
GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B,
GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B,
GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B,
GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C,
/* IPSR14 */
GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C,
GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD,
GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1,
GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3,
GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C,
GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C,
GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C,
GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C,
GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA,
GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B,
GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP,
GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B,
GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK,
GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B,
GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0,
GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B,
GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E,
GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B,
GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E,
GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B,
/* IPSR15 */
GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D,
GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C,
GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D,
GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B,
GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C,
GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5,
GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C,
GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6,
GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C,
GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C,
GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C,
GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N,
GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C,
GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK,
GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C,
GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C,
GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C,
GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C,
GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C,
/* IPSR16 */
GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B,
GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C,
GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B,
GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C,
GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C,
GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N,
GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B,
GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N,
GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
};
#endif /* __ASM_R8A7791_H__ */

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arch/arm/include/asm/arch-rmobile/r8a7791.h Normal file
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/*
* arch/arm/include/asm/arch-rmobile/r8a7791.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_ARCH_R8A7791_H
#define __ASM_ARCH_R8A7791_H
/*
* R8A7791 I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define LBSC_BASE 0xFEC00200
#define DBSC3_0_BASE 0xE6790000
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define S3C_QOS_DCACHE_BASE 0xE6784BDC
#define S3C_QOS_CCI0_BASE 0xE6784C00
#define S3C_QOS_CCI1_BASE 0xE6784C24
#define S3C_QOS_MXI_BASE 0xE6784C48
#define S3C_QOS_AXI_BASE 0xE6784C6C
#define DBSC3_0_QOS_R0_BASE 0xE6791000
#define DBSC3_0_QOS_R1_BASE 0xE6791100
#define DBSC3_0_QOS_R2_BASE 0xE6791200
#define DBSC3_0_QOS_R3_BASE 0xE6791300
#define DBSC3_0_QOS_R4_BASE 0xE6791400
#define DBSC3_0_QOS_R5_BASE 0xE6791500
#define DBSC3_0_QOS_R6_BASE 0xE6791600
#define DBSC3_0_QOS_R7_BASE 0xE6791700
#define DBSC3_0_QOS_R8_BASE 0xE6791800
#define DBSC3_0_QOS_R9_BASE 0xE6791900
#define DBSC3_0_QOS_R10_BASE 0xE6791A00
#define DBSC3_0_QOS_R11_BASE 0xE6791B00
#define DBSC3_0_QOS_R12_BASE 0xE6791C00
#define DBSC3_0_QOS_R13_BASE 0xE6791D00
#define DBSC3_0_QOS_R14_BASE 0xE6791E00
#define DBSC3_0_QOS_R15_BASE 0xE6791F00
#define DBSC3_0_QOS_W0_BASE 0xE6792000
#define DBSC3_0_QOS_W1_BASE 0xE6792100
#define DBSC3_0_QOS_W2_BASE 0xE6792200
#define DBSC3_0_QOS_W3_BASE 0xE6792300
#define DBSC3_0_QOS_W4_BASE 0xE6792400
#define DBSC3_0_QOS_W5_BASE 0xE6792500
#define DBSC3_0_QOS_W6_BASE 0xE6792600
#define DBSC3_0_QOS_W7_BASE 0xE6792700
#define DBSC3_0_QOS_W8_BASE 0xE6792800
#define DBSC3_0_QOS_W9_BASE 0xE6792900
#define DBSC3_0_QOS_W10_BASE 0xE6792A00
#define DBSC3_0_QOS_W11_BASE 0xE6792B00
#define DBSC3_0_QOS_W12_BASE 0xE6792C00
#define DBSC3_0_QOS_W13_BASE 0xE6792D00
#define DBSC3_0_QOS_W14_BASE 0xE6792E00
#define DBSC3_0_QOS_W15_BASE 0xE6792F00
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
#define DBSC3_1_QOS_R3_BASE 0xE67A1300
#define DBSC3_1_QOS_R4_BASE 0xE67A1400
#define DBSC3_1_QOS_R5_BASE 0xE67A1500
#define DBSC3_1_QOS_R6_BASE 0xE67A1600
#define DBSC3_1_QOS_R7_BASE 0xE67A1700
#define DBSC3_1_QOS_R8_BASE 0xE67A1800
#define DBSC3_1_QOS_R9_BASE 0xE67A1900
#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
#define DBSC3_1_QOS_W0_BASE 0xE67A2000
#define DBSC3_1_QOS_W1_BASE 0xE67A2100
#define DBSC3_1_QOS_W2_BASE 0xE67A2200
#define DBSC3_1_QOS_W3_BASE 0xE67A2300
#define DBSC3_1_QOS_W4_BASE 0xE67A2400
#define DBSC3_1_QOS_W5_BASE 0xE67A2500
#define DBSC3_1_QOS_W6_BASE 0xE67A2600
#define DBSC3_1_QOS_W7_BASE 0xE67A2700
#define DBSC3_1_QOS_W8_BASE 0xE67A2800
#define DBSC3_1_QOS_W9_BASE 0xE67A2900
#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
#define DBSC3_0_DBADJ2 0xE67900C8
#define CCI_400_MAXOT_1 0xF0091110
#define CCI_400_MAXOT_2 0xF0092110
#define CCI_400_QOSCNTL_1 0xF009110C
#define CCI_400_QOSCNTL_2 0xF009210C
#define MXI_BASE 0xFE960000
#define MXI_QOS_BASE 0xFE960300
#define SYS_AXI_SYX64TO128_BASE 0xFF800300
#define SYS_AXI_AVB_BASE 0xFF800340
#define SYS_AXI_G2D_BASE 0xFF800540
#define SYS_AXI_IMP0_BASE 0xFF800580
#define SYS_AXI_IMP1_BASE 0xFF8005C0
#define SYS_AXI_IMUX0_BASE 0xFF800600
#define SYS_AXI_IMUX1_BASE 0xFF800640
#define SYS_AXI_IMUX2_BASE 0xFF800680
#define SYS_AXI_LBS_BASE 0xFF8006C0
#define SYS_AXI_MMUDS_BASE 0xFF800700
#define SYS_AXI_MMUM_BASE 0xFF800740
#define SYS_AXI_MMUR_BASE 0xFF800780
#define SYS_AXI_MMUS0_BASE 0xFF8007C0
#define SYS_AXI_MMUS1_BASE 0xFF800800
#define SYS_AXI_MTSB0_BASE 0xFF800880
#define SYS_AXI_MTSB1_BASE 0xFF8008C0
#define SYS_AXI_PCI_BASE 0xFF800900
#define SYS_AXI_RTX_BASE 0xFF800940
#define SYS_AXI_SDS0_BASE 0xFF800A80
#define SYS_AXI_SDS1_BASE 0xFF800AC0
#define SYS_AXI_USB20_BASE 0xFF800C00
#define SYS_AXI_USB21_BASE 0xFF800C40
#define SYS_AXI_USB22_BASE 0xFF800C80
#define SYS_AXI_USB30_BASE 0xFF800CC0
#define SYS_AXI_AX2M_BASE 0xFF800380
#define SYS_AXI_CC50_BASE 0xFF8003C0
#define SYS_AXI_CCI_BASE 0xFF800440
#define SYS_AXI_CS_BASE 0xFF800480
#define SYS_AXI_DDM_BASE 0xFF8004C0
#define SYS_AXI_ETH_BASE 0xFF800500
#define SYS_AXI_MPXM_BASE 0xFF800840
#define SYS_AXI_SAT0_BASE 0xFF800980
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
#define SYS_AXI_TRAB_BASE 0xFF800B00
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#define RT_AXI_SHX_BASE 0xFF810100
#define RT_AXI_DBG_BASE 0xFF810140
#define RT_AXI_RDM_BASE 0xFF810180
#define RT_AXI_RDS_BASE 0xFF8101C0
#define RT_AXI_RTX64TO128_BASE 0xFF810200
#define RT_AXI_STPRO_BASE 0xFF810240
#define RT_AXI_SY2RT_BASE 0xFF810280
#define MP_AXI_ADSP_BASE 0xFF820100
#define MP_AXI_ASDS0_BASE 0xFF8201C0
#define MP_AXI_ASDS1_BASE 0xFF820200
#define MP_AXI_MLP_BASE 0xFF820240
#define MP_AXI_MMUMP_BASE 0xFF820280
#define MP_AXI_SPU_BASE 0xFF8202C0
#define MP_AXI_SPUC_BASE 0xFF820300
#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
#define SYS_AXI256_SYX_BASE 0xFF860140
#define SYS_AXI256_MPX_BASE 0xFF860180
#define SYS_AXI256_MXI_BASE 0xFF8601C0
#define CCI_AXI_MMUS0_BASE 0xFF880100
#define CCI_AXI_SYX2_BASE 0xFF880140
#define CCI_AXI_MMUR_BASE 0xFF880180
#define CCI_AXI_MMUDS_BASE 0xFF8801C0
#define CCI_AXI_MMUM_BASE 0xFF880200
#define CCI_AXI_MXI_BASE 0xFF880240
#define CCI_AXI_MMUS1_BASE 0xFF880280
#define CCI_AXI_MMUMP_BASE 0xFF8802C0
#define MEDIA_AXI_MXR_BASE 0xFE960080
#define MEDIA_AXI_MXW_BASE 0xFE9600C0
#define MEDIA_AXI_JPR_BASE 0xFE964100
#define MEDIA_AXI_JPW_BASE 0xFE966100
#define MEDIA_AXI_GCU0R_BASE 0xFE964140
#define MEDIA_AXI_GCU0W_BASE 0xFE966140
#define MEDIA_AXI_GCU1R_BASE 0xFE964180
#define MEDIA_AXI_GCU1W_BASE 0xFE966180
#define MEDIA_AXI_TDMR_BASE 0xFE964500
#define MEDIA_AXI_TDMW_BASE 0xFE966500
#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
#define MEDIA_AXI_VIN0W_BASE 0xFE966900
#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
#define MEDIA_AXI_IMSR_BASE 0xFE964D80
#define MEDIA_AXI_IMSW_BASE 0xFE966D80
#define MEDIA_AXI_VSP1R_BASE 0xFE965100
#define MEDIA_AXI_VSP1W_BASE 0xFE967100
#define MEDIA_AXI_FDP1R_BASE 0xFE965140
#define MEDIA_AXI_FDP1W_BASE 0xFE967140
#define MEDIA_AXI_IMRR_BASE 0xFE965180
#define MEDIA_AXI_IMRW_BASE 0xFE967180
#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
#define MEDIA_AXI_DU0R_BASE 0xFE965580
#define MEDIA_AXI_DU0W_BASE 0xFE967580
#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
#define MEDIA_AXI_VPC0R_BASE 0xFE965980
#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_CC50DMSCR 0xFF802008
#define SYS_AXI_CC51DMSCR 0xFF80200C
#define SYS_AXI_CCIDMSCR 0xFF802010
#define SYS_AXI_CSDMSCR 0xFF802014
#define SYS_AXI_DDMDMSCR 0xFF802018
#define SYS_AXI_ETHDMSCR 0xFF80201C
#define SYS_AXI_G2DDMSCR 0xFF802020
#define SYS_AXI_IMP0DMSCR 0xFF802024
#define SYS_AXI_IMP1DMSCR 0xFF802028
#define SYS_AXI_LBSDMSCR 0xFF80202C
#define SYS_AXI_MMUDSDMSCR 0xFF802030
#define SYS_AXI_MMUMXDMSCR 0xFF802034
#define SYS_AXI_MMURDDMSCR 0xFF802038
#define SYS_AXI_MMUS0DMSCR 0xFF80203C
#define SYS_AXI_MMUS1DMSCR 0xFF802040
#define SYS_AXI_MPXDMSCR 0xFF802044
#define SYS_AXI_MTSB0DMSCR 0xFF802048
#define SYS_AXI_MTSB1DMSCR 0xFF80204C
#define SYS_AXI_PCIDMSCR 0xFF802050
#define SYS_AXI_RTXDMSCR 0xFF802054
#define SYS_AXI_SAT0DMSCR 0xFF802058
#define SYS_AXI_SAT1DMSCR 0xFF80205C
#define SYS_AXI_SDM0DMSCR 0xFF802060
#define SYS_AXI_SDM1DMSCR 0xFF802064
#define SYS_AXI_SDS0DMSCR 0xFF802068
#define SYS_AXI_SDS1DMSCR 0xFF80206C
#define SYS_AXI_ETRABDMSCR 0xFF802070
#define SYS_AXI_ETRKFDMSCR 0xFF802074
#define SYS_AXI_UDM0DMSCR 0xFF802078
#define SYS_AXI_UDM1DMSCR 0xFF80207C
#define SYS_AXI_USB20DMSCR 0xFF802080
#define SYS_AXI_USB21DMSCR 0xFF802084
#define SYS_AXI_USB22DMSCR 0xFF802088
#define SYS_AXI_USB30DMSCR 0xFF80208C
#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
#define SYS_AXI_AVBSLVDMSCR 0xFF802108
#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
#define SYS_AXI_ETHSLVDMSCR 0xFF802110
#define SYS_AXI_GICSLVDMSCR 0xFF802114
#define SYS_AXI_IMPSLVDMSCR 0xFF802118
#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
#define SYS_AXI_LBSSLVDMSCR 0xFF802128
#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
#define SYS_AXI_MPXSLVDMSCR 0xFF802134
#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
#define SYS_AXI_MXTSLVDMSCR 0xFF802140
#define SYS_AXI_PCISLVDMSCR 0xFF802144
#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
#define SYS_AXI_RTXSLVDMSCR 0xFF802150
#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
#define SYS_AXI_SGXSLVDMSCR 0xFF802180
#define SYS_AXI_STBSLVDMSCR 0xFF802188
#define SYS_AXI_STMSLVDMSCR 0xFF80218C
#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
#define RT_AXI_CBMDMSCR 0xFF812000
#define RT_AXI_DBDMSCR 0xFF812004
#define RT_AXI_RDMDMSCR 0xFF812008
#define RT_AXI_RDSDMSCR 0xFF81200C
#define RT_AXI_STRDMSCR 0xFF812010
#define RT_AXI_SY2RTDMSCR 0xFF812014
#define RT_AXI_CBSSLVDMSCR 0xFF812100
#define RT_AXI_DBSSLVDMSCR 0xFF812104
#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
#define MP_AXI_ADSPDMSCR 0xFF822000
#define MP_AXI_ASDM0DMSCR 0xFF822004
#define MP_AXI_ASDM1DMSCR 0xFF822008
#define MP_AXI_ASDS0DMSCR 0xFF82200C
#define MP_AXI_ASDS1DMSCR 0xFF822010
#define MP_AXI_MLPDMSCR 0xFF822014
#define MP_AXI_MMUMPDMSCR 0xFF822018
#define MP_AXI_SPUDMSCR 0xFF82201C
#define MP_AXI_SPUCDMSCR 0xFF822020
#define MP_AXI_SY2MPDMSCR 0xFF822024
#define MP_AXI_ADSPSLVDMSCR 0xFF822100
#define MP_AXI_MLMSLVDMSCR 0xFF822104
#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
#define MP_AXI_SPUSLVDMSCR 0xFF822128
#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
#define ADM_AXI_ASDM0DMSCR 0xFF842000
#define ADM_AXI_ASDM1DMSCR 0xFF842004
#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
#define DM_AXI_RDMDMSCR 0xFF852000
#define DM_AXI_SDM0DMSCR 0xFF852004
#define DM_AXI_SDM1DMSCR 0xFF852008
#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
#define DM_AXI_RAP5SLVDMSCR 0xFF852110
#define DM_AXI_SAP4SLVDMSCR 0xFF852114
#define DM_AXI_SAP5SLVDMSCR 0xFF852118
#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
#define DM_AXI_SAP65SLVDMSCR 0xFF852120
#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
#define SYS_AXI256_SYXDMSCR 0xFF862000
#define SYS_AXI256_MPXDMSCR 0xFF862004
#define SYS_AXI256_MXIDMSCR 0xFF862008
#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
#define MXT_SYXDMSCR 0xFF872000
#define MXT_CMM0SLVDMSCR 0xFF872100
#define MXT_CMM1SLVDMSCR 0xFF872104
#define MXT_CMM2SLVDMSCR 0xFF872108
#define MXT_FDPSLVDMSCR 0xFF87210C
#define MXT_IMRSLVDMSCR 0xFF872110
#define MXT_VINSLVDMSCR 0xFF872114
#define MXT_VPC0SLVDMSCR 0xFF872118
#define MXT_VPC1SLVDMSCR 0xFF87211C
#define MXT_VSP0SLVDMSCR 0xFF872120
#define MXT_VSP1SLVDMSCR 0xFF872124
#define MXT_VSPD0SLVDMSCR 0xFF872128
#define MXT_VSPD1SLVDMSCR 0xFF87212C
#define MXT_MAP1SLVDMSCR 0xFF872130
#define MXT_MAP2SLVDMSCR 0xFF872134
#define CCI_AXI_MMUS0DMSCR 0xFF882000
#define CCI_AXI_SYX2DMSCR 0xFF882004
#define CCI_AXI_MMURDMSCR 0xFF882008
#define CCI_AXI_MMUDSDMSCR 0xFF88200C
#define CCI_AXI_MMUMDMSCR 0xFF882010
#define CCI_AXI_MXIDMSCR 0xFF882014
#define CCI_AXI_MMUS1DMSCR 0xFF882018
#define CCI_AXI_MMUMPDMSCR 0xFF88201C
#define CCI_AXI_DVMDMSCR 0xFF882020
#define CCI_AXI_CCISLVDMSCR 0xFF882100
#define CCI_AXI_IPMMUIDVMCR 0xFF880400
#define CCI_AXI_IPMMURDVMCR 0xFF880404
#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7791_rwdt {
u32 rwtcnt; /* 0x00 */
u32 rwtcsra; /* 0x04 */
u16 rwtcsrb; /* 0x08 */
};
/* SWDT */
struct r8a7791_swdt {
u32 swtcnt; /* 0x00 */
u32 swtcsra; /* 0x04 */
u16 swtcsrb; /* 0x08 */
};
/* LBSC */
struct r8a7791_lbsc {
u32 cs0ctrl;
u32 cs1ctrl;
u32 ecs0ctrl;
u32 ecs1ctrl;
u32 ecs2ctrl;
u32 ecs3ctrl;
u32 ecs4ctrl;
u32 ecs5ctrl;
u32 dummy0[4]; /* 0x20 .. 0x2C */
u32 cswcr0;
u32 cswcr1;
u32 ecswcr0;
u32 ecswcr1;
u32 ecswcr2;
u32 ecswcr3;
u32 ecswcr4;
u32 ecswcr5;
u32 exdmawcr0;
u32 exdmawcr1;
u32 exdmawcr2;
u32 dummy1[9]; /* 0x5C .. 0x7C */
u32 cspwcr0;
u32 cspwcr1;
u32 ecspwcr0;
u32 ecspwcr1;
u32 ecspwcr2;
u32 ecspwcr3;
u32 ecspwcr4;
u32 ecspwcr5;
u32 exwtsync;
u32 dummy2[3]; /* 0xA4 .. 0xAC */
u32 cs0bstctl;
u32 cs0btph;
u32 dummy3[2]; /* 0xB8 .. 0xBC */
u32 cs1gdst;
u32 ecs0gdst;
u32 ecs1gdst;
u32 ecs2gdst;
u32 ecs3gdst;
u32 ecs4gdst;
u32 ecs5gdst;
u32 dummy4[5]; /* 0xDC .. 0xEC */
u32 exdmaset0;
u32 exdmaset1;
u32 exdmaset2;
u32 dummy5[5]; /* 0xFC .. 0x10C */
u32 exdmcr0;
u32 exdmcr1;
u32 exdmcr2;
u32 dummy6[5]; /* 0x11C .. 0x12C */
u32 bcintsr;
u32 bcintcr;
u32 bcintmr;
u32 dummy7; /* 0x13C */
u32 exbatlv;
u32 exwtsts;
u32 dummy8[14]; /* 0x148 .. 0x17C */
u32 atacsctrl;
u32 dummy9[15]; /* 0x184 .. 0x1BC */
u32 exbct;
u32 extct;
};
/* DBSC3 */
struct r8a7791_dbsc3 {
u32 dummy0[3]; /* 0x00 .. 0x08 */
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2C */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3C */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4C */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xAC */
u32 dbbl;
u32 dummy5[3]; /* 0xB4 .. 0xBC */
u32 dbadj0;
u32 dummy6; /* 0xC4 */
u32 dbadj2;
u32 dummy7[5]; /* 0xCC .. 0xDC */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dummy8[2]; /* 0xEC .. 0xF0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy9; /* 0xFC */
u32 dbrnk0;
u32 dummy10[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy11[47]; /* 0x184 ..0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[14]; /* 0x248 .. 0x27C */
u32 dbpdlck;
u32 dummy13[3]; /* 0x284 .. 0x28C */
u32 dbpdrga;
u32 dummy14[3]; /* 0x294 .. 0x29C */
u32 dbpdrgd;
u32 dummy15[24]; /* 0x2A4 .. 0x300 */
u32 dbbs0cnt1;
u32 dummy16[30]; /* 0x308 .. 0x37C */
u32 dbwt0cnf0;
u32 dbwt0cnf1;
u32 dbwt0cnf2;
u32 dbwt0cnf3;
u32 dbwt0cnf4;
};
/* GPIO */
struct r8a7791_gpio {
u32 iointsel;
u32 inoutsel;
u32 outdt;
u32 indt;
u32 intdt;
u32 intclr;
u32 intmsk;
u32 posneg;
u32 edglevel;
u32 filonoff;
u32 intmsks;
u32 mskclrs;
u32 outdtsel;
u32 outdth;
u32 outdtl;
u32 bothedge;
};
/* S3C(QoS) */
struct r8a7791_s3c {
u32 s3cexcladdmsk;
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
u32 dummy0; /* 0x10 */
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;
u32 dummy1[2]; /* 0x20 .. 0x24 */
u32 s3cmctr;
u32 dummy2; /* 0x2C */
u32 cconf0;
u32 cconf1;
u32 cconf2;
u32 cconf3;
};
struct r8a7791_s3c_qos {
u32 s3cqos0;
u32 s3cqos1;
u32 s3cqos2;
u32 s3cqos3;
u32 s3cqos4;
u32 s3cqos5;
u32 s3cqos6;
u32 s3cqos7;
u32 s3cqos8;
};
/* DBSC(QoS) */
struct r8a7791_dbsc3_qos {
u32 dblgcnt;
u32 dbtmval0;
u32 dbtmval1;
u32 dbtmval2;
u32 dbtmval3;
u32 dbrqctr;
u32 dbthres0;
u32 dbthres1;
u32 dbthres2;
u32 dummy0; /* 0x24 */
u32 dblgqon;
};
/* MXI(QoS) */
struct r8a7791_mxi {
u32 mxsaar0;
u32 mxsaar1;
u32 dummy0[8]; /* 0x08 .. 0x24 */
u32 mxs3cracr;
u32 dummy1[3]; /* 0x2C .. 0x34 */
u32 mxs3cwacr;
u32 dummy2; /* 0x3C */
u32 mxrtcr;
u32 mxwtcr;
};
struct r8a7791_mxi_qos {
u32 vspdu0;
u32 vspdu1;
u32 du0;
u32 du1;
};
/* AXI(QoS) */
struct r8a7791_axi_qos {
u32 qosconf;
u32 qosctset0;
u32 qosctset1;
u32 qosctset2;
u32 qosctset3;
u32 qosreqctr;
u32 qosthres0;
u32 qosthres1;
u32 qosthres2;
u32 qosqon;
};
#endif
#endif /* __ASM_ARCH_R8A7791_H */

4
arch/arm/include/asm/arch-rmobile/rmobile.h
View File

@ -6,6 +6,10 @@
#include <asm/arch/sh73a0.h>
#elif defined(CONFIG_R8A7740)
#include <asm/arch/r8a7740.h>
#elif defined(CONFIG_R8A7790)
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
#else
#error "SOC Name not defined"
#endif

2
arch/arm/include/asm/arch-s5pc1xx/mmc.h
View File

@ -55,7 +55,7 @@
int s5p_sdhci_init(u32 regbase, int index, int bus_width);
static inline unsigned int s5p_mmc_init(int index, int bus_width)
static inline int s5p_mmc_init(int index, int bus_width)
{
unsigned int base = samsung_get_base_mmc() +
(S5P_MMC_DEV_OFFSET * index);

50
arch/arm/include/asm/arch-socfpga/freeze_controller.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _FREEZE_CONTROLLER_H_
#define _FREEZE_CONTROLLER_H_
struct socfpga_freeze_controller {
u32 vioctrl;
u32 padding[3];
u32 hioctrl;
u32 src;
u32 hwctrl;
};
#define FREEZE_CHANNEL_NUM (4)
typedef enum {
FREEZE_CTRL_FROZEN = 0,
FREEZE_CTRL_THAWED = 1
} FREEZE_CTRL_CHAN_STATE;
#define SYSMGR_FRZCTRL_ADDRESS 0x40
#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
void sys_mgr_frzctrl_freeze_req(void);
void sys_mgr_frzctrl_thaw_req(void);
#endif /* _FREEZE_CONTROLLER_H_ */

14
arch/arm/include/asm/emif.h
View File

@ -581,7 +581,6 @@
(0xFF << EMIF_SYS_ADDR_SHIFT))
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
/* Reg mapping structure */
struct emif_reg_struct {
@ -641,7 +640,9 @@ struct emif_reg_struct {
u32 emif_ddr_phy_ctrl_2;
u32 padding7[12];
u32 emif_rd_wr_exec_thresh;
u32 padding8[55];
u32 padding8[7];
u32 emif_ddr_phy_status[21];
u32 padding9[27];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@ -690,6 +691,9 @@ struct emif_reg_struct {
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
u32 padding[22];
u32 emif_ddr_fifo_misaligned_clear_1;
u32 emif_ddr_fifo_misaligned_clear_2;
};
struct dmm_lisa_map_regs {
@ -1139,6 +1143,11 @@ struct lpddr2_mr_regs {
s8 mr16;
};
struct read_write_regs {
u32 read_reg;
u32 write_reg;
};
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })
@ -1167,4 +1176,5 @@ extern u32 *const T_den;
void config_data_eye_leveling_samples(u32 emif_base);
u32 emif_sdram_type(void);
const struct read_write_regs *get_bug_regs(u32 *iterations);
#endif

10
arch/arm/include/asm/omap_common.h
View File

@ -226,6 +226,7 @@ struct prcm_regs {
u32 cm_l3init_hsusbotg_clkctrl;
u32 cm_l3init_hsusbtll_clkctrl;
u32 cm_l3init_p1500_clkctrl;
u32 cm_l3init_sata_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
@ -366,6 +367,7 @@ struct omap_sys_ctrl_regs {
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
u32 control_usbotghs_ctrl;
u32 control_phy_power_sata;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
@ -605,6 +607,14 @@ static inline u8 is_omap54xx(void)
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
}
#define DRA7XX 0x07000000
static inline u8 is_dra7xx(void)
{
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == DRA7XX);
}
#endif
/*

23
board/BuS/vl_ma2sc/vl_ma2sc.c
View File

@ -10,13 +10,13 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_common.h>
@ -66,35 +66,22 @@ static void vl_ma2sc_nand_hw_init(void)
/* Configure RDY/BSY */
#ifdef CONFIG_SYS_NAND_READY_PIN
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
#endif
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void vl_ma2sc_macb_hw_init(void)
{
unsigned long erstl;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
/* Enable clock */
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_phy_reset();
at91_macb_hw_init();
}

15
board/actux1/u-boot.lds
View File

@ -87,10 +87,13 @@ SECTIONS
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
.dynsym _end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

15
board/actux2/u-boot.lds
View File

@ -87,10 +87,13 @@ SECTIONS
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
.dynsym _end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

15
board/actux3/u-boot.lds
View File

@ -87,10 +87,13 @@ SECTIONS
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
.dynsym _end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.hash : { *(.hash*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

18
board/afeb9260/afeb9260.c
View File

@ -13,7 +13,6 @@
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
@ -67,8 +66,6 @@ static void afeb9260_macb_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
unsigned long erstl;
/* Enable EMAC clock */
@ -94,20 +91,7 @@ static void afeb9260_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA28),
&pioa->pudr);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
&rstc->mr);
at91_phy_reset();
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA14) |

19
board/atmel/at91sam9260ek/at91sam9260ek.c
View File

@ -12,7 +12,6 @@
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <atmel_mci.h>
@ -73,8 +72,6 @@ static void at91sam9260ek_macb_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
unsigned long erstl;
/* Enable EMAC clock */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@ -98,21 +95,7 @@ static void at91sam9260ek_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA28),
&pioa->pudr);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
&rstc->mr);
at91_phy_reset();
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA14) |

19
board/atmel/at91sam9263ek/at91sam9263ek.c
View File

@ -12,7 +12,6 @@
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
@ -82,10 +81,9 @@ static void at91sam9263ek_nand_hw_init(void)
#ifdef CONFIG_MACB
static void at91sam9263ek_macb_hw_init(void)
{
unsigned long erstl;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
/* Enable clock */
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
@ -97,23 +95,10 @@ static void at91sam9263ek_macb_hw_init(void)
*
* PHY has internal pull-down
*/
writel(1 << 25, &pio->pioc.pudr);
writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_phy_reset();
/* Re-enable pull-up */
writel(1 << 25, &pio->pioc.puer);

19
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
View File

@ -12,7 +12,6 @@
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
@ -88,8 +87,6 @@ static void at91sam9m10g45ek_macb_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
unsigned long erstl;
/* Enable clock */
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
@ -107,21 +104,7 @@ static void at91sam9m10g45ek_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA13),
&pioa->pudr);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
&rstc->mr);
at91_phy_reset();
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA15) |

91
board/atmel/sama5d3xek/sama5d3xek.c
View File

@ -20,6 +20,9 @@
#include <micrel.h>
#include <net.h>
#include <netdev.h>
#include <spl.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/at91_wdt.h>
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
#include <asm/arch/atmel_usba_udc.h>
@ -159,6 +162,12 @@ void lcd_show_board_info(void)
int board_early_init_f(void)
{
at91_periph_clk_enable(ATMEL_ID_PIOA);
at91_periph_clk_enable(ATMEL_ID_PIOB);
at91_periph_clk_enable(ATMEL_ID_PIOC);
at91_periph_clk_enable(ATMEL_ID_PIOD);
at91_periph_clk_enable(ATMEL_ID_PIOE);
at91_seriald_hw_init();
return 0;
@ -291,3 +300,85 @@ void spi_cs_deactivate(struct spi_slave *slave)
}
}
#endif /* CONFIG_ATMEL_SPI */
/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
sama5d3xek_mci_hw_init();
#endif
}
static void ddr2_conf(struct atmel_mpddr *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
ATMEL_MPDDRC_CR_NR_ROW_14 |
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
ATMEL_MPDDRC_CR_ENRDM_ON |
ATMEL_MPDDRC_CR_NB_8BANKS |
ATMEL_MPDDRC_CR_NDQS_DISABLED |
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
/*
* As the DDR2-SDRAm device requires a refresh time is 7.8125us
* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
*/
ddr2->rtr = 0x411;
ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr ddr2;
ddr2_conf(&ddr2);
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(0x4, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
}
void at91_pmc_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
u32 tmp;
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(43) |
AT91_PMC_PLLXR_DIV(1);
at91_plla_init(tmp);
writel(0x3 << 8, &pmc->pllicpr);
tmp = AT91_PMC_MCKR_MDIV_4 |
AT91_PMC_MCKR_CSS_PLLA;
at91_mck_init(tmp);
}
#endif

16
board/bluewater/snapper9260/snapper9260.c
View File

@ -14,7 +14,6 @@
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <net.h>
#include <netdev.h>
@ -31,8 +30,6 @@ static void macb_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
unsigned long erstl;
/* Enable clock */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@ -54,18 +51,7 @@ static void macb_hw_init(void)
/* Enable ethernet power */
pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
/* Need to reset PHY -> 500ms reset */
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_phy_reset();
/* Bring the ethernet out of reset */
pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);

19
board/calao/sbc35_a9g20/sbc35_a9g20.c
View File

@ -15,7 +15,6 @@
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@ -77,8 +76,6 @@ static void sbc35_a9g20_macb_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
unsigned long erstl;
/* Enable EMAC clock */
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@ -102,21 +99,7 @@ static void sbc35_a9g20_macb_hw_init(void)
pin_to_mask(AT91_PIN_PA28),
&pioa->pudr);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
&rstc->mr);
at91_phy_reset();
/* Re-enable pull-up */
writel(pin_to_mask(AT91_PIN_PA14) |

14
board/calao/usb_a9263/Makefile Normal file
View File

@ -0,0 +1,14 @@
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008
# Stelian Pop <stelian@popies.net>
# Lead Tech Design <www.leadtechdesign.com>
#
# (C) Copyright 2013
# Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
#
# SPDX-License-Identifier: GPL-2.0+
obj-y += usb_a9263.o

148
board/calao/usb_a9263/usb_a9263.c Normal file
View File

@ -0,0 +1,148 @@
/*
* (C) Copyright 2007-2013
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
* Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
* Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm-generic/gpio.h>
#include <asm/io.h>
#include <net.h>
#include <netdev.h>
#include <dataflash.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_HAS_DATAFLASH
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00004000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
};
#endif
#ifdef CONFIG_CMD_NAND
static void usb_a9263_nand_hw_init(void)
{
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
/* Enable CS3 */
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer);
/* Configure RDY/BSY */
gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void usb_a9263_macb_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
/* Enable clock */
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
* RXDV (PC25) => PHY normal mode (not Test mode)
* ERX0 (PE25) => PHY ADDR0
* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal weak pull-up/pull-down
*/
gpio_request(GPIO_PIN_PC(25), "PHY mode");
gpio_direction_input(GPIO_PIN_PC(25));
gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
gpio_direction_input(GPIO_PIN_PE(25));
gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
gpio_direction_input(GPIO_PIN_PE(26));
at91_phy_reset();
/* It will set proper pinmux for ports PC25, PE25-26 */
at91_macb_hw_init();
}
#endif
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
usb_a9263_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
usb_a9263_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
at91_uhp_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
#endif
return rc;
}

10
board/compulab/cm_t335/Makefile Normal file
View File

@ -0,0 +1,10 @@
#
# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
#
# Author: Ilya Ledvich <ilya@compulab.co.il>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += $(BOARD).o
obj-$(CONFIG_SPL_BUILD) += mux.o spl.o

162
board/compulab/cm_t335/cm_t335.c Normal file
View File

@ -0,0 +1,162 @@
/*
* Board functions for Compulab CM-T335 board
*
* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
*
* Author: Ilya Ledvich <ilya@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <miiphy.h>
#include <cpsw.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware_am33xx.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
#endif
return 0;
}
#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slave = {
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = &cpsw_slave,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
/* PHY reset GPIO */
#define GPIO_PHY_RST GPIO_PIN(3, 7)
static void board_phy_init(void)
{
gpio_request(GPIO_PHY_RST, "phy_rst");
gpio_direction_output(GPIO_PHY_RST, 0);
mdelay(2);
gpio_set_value(GPIO_PHY_RST, 1);
mdelay(2);
}
static void get_efuse_mac_addr(uchar *enetaddr)
{
uint32_t mac_hi, mac_lo;
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
enetaddr[0] = mac_hi & 0xFF;
enetaddr[1] = (mac_hi & 0xFF00) >> 8;
enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
enetaddr[4] = mac_lo & 0xFF;
enetaddr[5] = (mac_lo & 0xFF00) >> 8;
}
/*
* Routine: handle_mac_address
* Description: prepare MAC address for on-board Ethernet.
*/
static int handle_mac_address(void)
{
uchar enetaddr[6];
int rv;
rv = eth_getenv_enetaddr("ethaddr", enetaddr);
if (rv)
return 0;
rv = cl_eeprom_read_mac_addr(enetaddr);
if (rv)
get_efuse_mac_addr(enetaddr);
if (!is_valid_ether_addr(enetaddr))
return -1;
return eth_setenv_enetaddr("ethaddr", enetaddr);
}
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
const char *devname;
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
rv = handle_mac_address();
if (rv)
printf("No MAC address found!\n");
writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
board_phy_init();
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
/*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the AR8051 PHY. Since we only support a single ethernet
* device, we only do this for the first instance.
*/
devname = miiphy_get_current_dev();
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
AR8051_DEBUG_RGMII_CLK_DLY_REG);
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
AR8051_RGMII_TX_CLK_DLY);
return n;
}
#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */

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board/compulab/cm_t335/mux.c Normal file
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/*
* Pinmux configuration for Compulab CM-T335 board
*
* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
*
* Author: Ilya Ledvich <ilya@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux uart1_pin_mux[] = {
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
{OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
{-1},
};
static struct module_pin_mux i2c1_pin_mux[] = {
/* I2C_DATA */
{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
/* I2C_SCLK */
{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
{-1},
};
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
static struct module_pin_mux eth_phy_rst_pin_mux[] = {
{OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */
{-1},
};
static struct module_pin_mux status_led_pin_mux[] = {
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */
{-1},
};
void set_uart_mux_conf(void)
{
configure_module_pin_mux(uart0_pin_mux);
configure_module_pin_mux(uart1_pin_mux);
}
void set_mux_conf_regs(void)
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(eth_phy_rst_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(nand_pin_mux);
configure_module_pin_mux(status_led_pin_mux);
}

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