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board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations

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As written in comment, P2020 has two possible SD switch configurations.
Extend code to detect both of them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Pali Rohár
2022-04-07 12:16:15 +02:00
committed by Priyanka Jain
parent ccad59dc5c
commit 4aceaec585
2 changed files with 6 additions and 1 deletions
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4
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@@ -216,6 +216,10 @@ int checkboard(void)
puts("rom_loc: "); puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
puts("sd"); puts("sd");
#ifdef __SW_BOOT_SD2
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
puts("sd");
#endif
#ifdef __SW_BOOT_SPI #ifdef __SW_BOOT_SPI
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
puts("spi"); puts("spi");

3
include/configs/p1_p2_rdb_pc.h
View File

@@ -57,7 +57,8 @@
#define __SW_BOOT_MASK 0x03 #define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_NOR 0xc8
#define __SW_BOOT_SPI 0x28 #define __SW_BOOT_SPI 0x28
#define __SW_BOOT_SD 0x68 /* or 0x18 */ #define __SW_BOOT_SD 0x68
#define __SW_BOOT_SD2 0x18
#define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8 #define __SW_BOOT_PCIE 0xa8
#define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_L2_SIZE (512 << 10)