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cmd: zynqrsa: Added support to load non-encrypted bitstream

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zynqrsa programs the PL when a partition includes an authenticated
and encrypted bitstream. However, if the partition is only
authenticated there is no PL programming operation because
there was no support to load only authenticated bitstream.

This patch added support to load only authenticated bitstream.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Vipul Kumar
2018-05-09 19:10:31 +05:30
committed by Michal Simek
parent de5f011561
commit 4686f263f6
3 changed files with 16 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
cmd/zynq_rsa.c
View File

@@ -548,7 +548,7 @@ static int do_zynq_verify_image(cmd_tbl_t *cmdtp, int flag, int argc,
debug("Authentication Done\r\n");
}
if (encrypt_part_flag) {
if (encrypt_part_flag || signed_part_flag) {
debug("DECRYPTION \r\n");
part_dst_addr = part_load_addr;
@@ -568,7 +568,8 @@ static int do_zynq_verify_image(cmd_tbl_t *cmdtp, int flag, int argc,
part_img_len,
part_dst_addr,
part_data_len,
bstype);
bstype,
encrypt_part_flag);
if (status != 0) {
printf("DECRYPTION_FAIL\r\n");
return -1;

20
drivers/fpga/zynqpl.c
View File

@@ -507,7 +507,7 @@ struct xilinx_fpga_op zynq_op = {
* place it back the decrypted image into dstaddr.
*/
int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
u8 bstype)
u8 bstype, bool encrypt_part_flag)
{
u32 isr_status, ts;
@@ -517,10 +517,13 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
return FPGA_FAIL;
}
/* Check AES engine is enabled */
if (!(readl(&devcfg_base->ctrl) & DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
printf("%s: AES engine is not enabled\n", __func__);
return FPGA_FAIL;
if (encrypt_part_flag) {
/* Check AES engine is enabled */
if (!(readl(&devcfg_base->ctrl) &
DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
printf("%s: AES engine is not enabled\n", __func__);
return FPGA_FAIL;
}
}
if (zynq_dma_xfer_init(bstype)) {
@@ -528,8 +531,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
return FPGA_FAIL;
}
writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
&devcfg_base->ctrl);
if (encrypt_part_flag)
writel((readl(&devcfg_base->ctrl) |
DEVCFG_CTRL_PCAP_RATE_EN_MASK), &devcfg_base->ctrl);
debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
debug("%s: Size = %zu\n", __func__, srclen);
@@ -633,7 +637,7 @@ static int do_zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc,
dstlen = roundup(dstlen, 4);
status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2,
imgtype);
imgtype, true);
if (status != 0)
return -1;

2
include/zynqpl.h
View File

@@ -14,7 +14,7 @@
#ifdef CONFIG_CMD_ZYNQ_AES
extern int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
u8 bstype);
u8 bstype, bool encrypt_part_flag);
#endif
#if defined(CONFIG_FPGA_ZYNQPL)
extern struct xilinx_fpga_op zynq_op;