85xx: Socrates: Major code update.
- Update the local bus ranges in the FDT for Linux for the various devices connected to the local bus via chip-select. - Set the LCRR_DBYP bit in the LCRR for local bus frequencies lower than 66 MHz and uses I/O accessor functions consequently. - UPM data update. - Update of default environment and configuration. Use I2C multibus as we do have two I2C buses. Also enable sdram and ext2 commands. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Detlev Zundel
Wolfgang Denk
parent
e8d18541c6
commit
3e79b588b5
@ -37,9 +37,8 @@
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#include <fdt_support.h>
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#include <asm/io.h>
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#if defined(CFG_FPGA_BASE)
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#include "upm_table.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[]; /* FLASH chips info */
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@ -50,6 +49,7 @@ ulong flash_get_size (ulong base, int banknum);
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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char *src;
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int f;
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char *s = getenv("serial#");
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@ -79,10 +79,6 @@ int checkboard (void)
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* Initialize local bus.
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*/
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local_bus_init ();
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#if defined(CFG_FPGA_BASE)
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/* Init UPMA for FPGA access */
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upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
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#endif
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return 0;
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}
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@ -149,15 +145,34 @@ int misc_init_r (void)
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*/
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void local_bus_init (void)
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{
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volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
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volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
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sys_info_t sysinfo;
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uint clkdiv;
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uint lbc_mhz;
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uint lcrr = CFG_LBC_LCRR;
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
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ecm->eedr = 0xffffffff; /* Clear ecm errors */
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ecm->eeer = 0xffffffff; /* Enable ecm errors */
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get_sys_info (&sysinfo);
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clkdiv = lbc->lcrr & 0x0f;
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lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
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if (lbc_mhz >= 66)
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lcrr &= ~LCRR_DBYP; /* DLL Enabled */
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else
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lcrr |= LCRR_DBYP; /* DLL Bypass */
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out_be32 (&lbc->lcrr, lcrr);
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asm ("sync;isync;msync");
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out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
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out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
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out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
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out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
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/* Init UPMA for FPGA access */
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out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
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upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
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}
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#if defined(CONFIG_PCI)
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@ -197,9 +212,14 @@ void pci_init_board (void)
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#ifdef CONFIG_BOARD_EARLY_INIT_R
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int board_early_init_r (void)
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{
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#ifdef CONFIG_PS2MULT
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ps2mult_early_init();
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#endif /* CONFIG_PS2MULT */
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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/* set and reset the GPIO pin 2 which will reset the W83782G chip */
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out_8((unsigned char*)&gur->gpoutdr, 0x3F );
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out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
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udelay(200);
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out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
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return (0);
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}
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#endif /* CONFIG_BOARD_EARLY_INIT_R */
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@ -208,31 +228,27 @@ int board_early_init_r (void)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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u32 val[4];
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int rc;
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u32 val[12];
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int rc, i = 0;
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ft_cpu_setup(blob, bd);
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/* Fixup NOR mapping */
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val[0] = 0; /* chip select number */
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val[1] = 0; /* always 0 */
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val[2] = gd->bd->bi_flashstart;
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val[3] = gd->bd->bi_flashsize;
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/* Fixup NOR FLASH mapping */
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val[i++] = 0; /* chip select number */
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val[i++] = 0; /* always 0 */
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val[i++] = gd->bd->bi_flashstart;
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val[i++] = gd->bd->bi_flashsize;
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/* Fixup FPGA mapping */
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val[i++] = 3; /* chip select number */
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val[i++] = 0; /* always 0 */
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val[i++] = CFG_FPGA_BASE;
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val[i++] = CFG_FPGA_SIZE;
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rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
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val, sizeof(val), 1);
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val, i * sizeof(u32), 1);
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if (rc)
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printf("Unable to update property NOR mapping, err=%s\n",
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printf("Unable to update localbus ranges, err=%s\n",
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fdt_strerror(rc));
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#if defined (CFG_FPGA_BASE)
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memset(val, 0, sizeof(val));
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val[0] = CFG_FPGA_BASE;
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rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg",
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val, sizeof(val), 1);
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if (rc)
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printf("Unable to update property \"fpga\", err=%s\n",
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fdt_strerror(rc));
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#endif
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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@ -34,22 +34,22 @@
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/* UPM Table Configuration Code for FPGA access */
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static const unsigned int UPMTableA[] =
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{
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, /* Words 0 to 3 */
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, /* Words 4 to 7 */
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0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, /* Words 8 to 11 */
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0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, /* Words 12 to 15 */
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0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, /* Words 16 to 19 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
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0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, /* Words 24 to 27 */
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0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, /* Words 28 to 31 */
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0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 32 to 35 */
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0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 36 to 39 */
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0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
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0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */
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0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */
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0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */
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0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */
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0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */
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0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */
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0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */
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0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */
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0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */
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0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */
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0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */
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0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */
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0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */
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0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */
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0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */
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0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */
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0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */
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};
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#endif
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@ -45,6 +45,7 @@
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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@ -141,13 +142,12 @@
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#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
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#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */
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#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */
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#define CFG_OR0_PRELIM 0xfe000030 /* 32MB Flash */
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#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */
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#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
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#define CFG_OR1_PRELIM 0xfe000030 /* 32MB Flash */
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#define CFG_FLASH_CFI /* flash is CFI compat. */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
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#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
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@ -157,7 +157,7 @@
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
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#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
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#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
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#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
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@ -171,8 +171,20 @@
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
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#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
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/* FPGA and NAND */
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#define CFG_FPGA_BASE 0xc0000000
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#define CFG_FPGA_SIZE 0x00100000 /* 1 MB */
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#define CFG_HMI_BASE 0xc0010000
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#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
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#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */
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#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70)
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_CMD_NAND
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/* Serial Port */
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@ -204,11 +216,14 @@
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SPEED 102124 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CFG_I2C2_OFFSET 0x3100
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/* I2C RTC */
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#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
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#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */
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@ -302,18 +317,18 @@
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#define CONFIG_CMD_DTT
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#undef CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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@ -357,50 +372,69 @@
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#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo Welcome on the ABB Socrates Board;" \
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"echo"
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootfile=$hostname/uImage\0" \
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"netdev=eth0\0" \
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"consdev=ttyS0\0" \
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"hostname=socrates\0" \
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"uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
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"bootfile=/home/tftp/syscon3/uImage\0" \
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"fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
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"initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
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"uboot_addr=FFFA0000\0" \
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"kernel_addr=FE000000\0" \
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"fdt_addr=FE1E0000\0" \
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"ramdisk_addr=FE200000\0" \
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"fdt_addr_r=B00000\0" \
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"kernel_addr_r=200000\0" \
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"ramdisk_addr_r=400000\0" \
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"rootpath=/opt/eldk/ppc_85xxDP\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addcons=setenv bootargs $bootargs " \
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"console=$consdev,$baudrate\0" \
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"addip=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
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":$hostname:$netdev:off panic=1\0" \
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"addcons=setenv bootargs $bootargs " \
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"console=$consdev,$baudrate\0" \
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"flash_self=run ramargs addip addcons;" \
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"boot_nor=run ramargs addcons;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"flash_nfs=run nfsargs addip addcons;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
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"tftp ${fdt_addr_r} ${fdt_file}; " \
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"run nfsargs addip addcons;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"fdt_file=$hostname/socrates.dtb\0" \
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"fdt_addr_r=B00000\0" \
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"fdt_addr=FC1E0000\0" \
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"rootpath=/opt/eldk/ppc_85xxDP\0" \
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"kernel_addr=FC000000\0" \
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"kernel_addr_r=200000\0" \
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"ramdisk_addr=FC200000\0" \
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"ramdisk_addr_r=400000\0" \
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"load=tftp 100000 $hostname/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b 100000 fffc0000 40000;" \
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"update_uboot=tftp 100000 ${uboot_file};" \
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"protect off fffa0000 ffffffff;" \
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"era fffa0000 ffffffff;" \
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"cp.b 100000 fffa0000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"update_kernel=tftp 100000 ${bootfile};" \
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"era fe000000 fe1dffff;" \
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"cp.b 100000 fe000000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"update_fdt=tftp 100000 ${fdt_file};" \
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"era fe1e0000 fe1fffff;" \
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"cp.b 100000 fe1e0000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"update_initrd=tftp 100000 ${initrd_file};" \
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"era fe200000 fe9fffff;" \
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"cp.b 100000 fe200000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"clean_data=era fea00000 fff5ffff\0" \
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"usbargs=setenv bootargs root=/dev/sda1 rw\0" \
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"load_usb=usb start;" \
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"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
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"boot_usb=run load_usb usbargs addcons;" \
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"bootm ${kernel_addr_r} - ${fdt_addr};" \
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||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
#define CONFIG_BOOTCOMMAND "run boot_nor"
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
@ -417,14 +451,4 @@
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
|
||||
/* FPGA and NAND */
|
||||
#define CFG_FPGA_BASE 0xc0000000
|
||||
#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
|
||||
#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */
|
||||
|
||||
#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70)
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user