arm64: versal: Add a2197 base board support with x-prc01/02 cards
There is generic defconfig designed for autodetection (not added yet) and then separate defconfigs directly used for certain x-prc card. Octal SPI dts is added but not wired for x-prc specific defconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
This commit is contained in:
Michal Simek
@@ -210,7 +210,11 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
|
||||
versal-mini-qspi-x1-single.dtb \
|
||||
versal-mini-qspi-x1-stacked.dtb \
|
||||
versal-mini-qspi-x2-single.dtb \
|
||||
versal-mini-qspi-x2-stacked.dtb
|
||||
versal-mini-qspi-x2-stacked.dtb \
|
||||
versal-vc-p-a2197-00-revA.dtb \
|
||||
versal-vc-p-a2197-00-revA-x-prc-01-revA.dtb \
|
||||
versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi.dtb \
|
||||
versal-vc-p-a2197-00-revA-x-prc-02-revA.dtb
|
||||
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
|
||||
zynqmp-r5.dtb
|
||||
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \
|
||||
|
||||
160
arch/arm/dts/versal-fixed.dtsi
Normal file
160
arch/arm/dts/versal-fixed.dtsi
Normal file
@@ -0,0 +1,160 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal fixed clock default configuration
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/ {
|
||||
clk60: clk60 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <60000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
clk100: clk100 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
clk125: clk125 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
clk150: clk150 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <150000000>;
|
||||
};
|
||||
|
||||
clk160: clk160 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <160000000>;
|
||||
};
|
||||
|
||||
clk200: clk200 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
clk250: clk250 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
clk300: clk300 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
clocks = <&clk160 &clk100>;
|
||||
};
|
||||
|
||||
&can1 {
|
||||
clocks = <&clk160 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan0 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan1 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan2 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan3 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan4 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan5 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan6 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&lpd_dma_chan7 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&gpio {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
clocks = <&clk100 &clk125 &clk125 &clk125 &clk250>;
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
clocks = <&clk100 &clk125 &clk125 &clk125 &clk250>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
clocks = <&clk300 &clk100>;
|
||||
};
|
||||
|
||||
&ospi {
|
||||
clocks = <&clk200 &clk100>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
clocks = <&clk100 &clk100>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
clocks = <&clk200 &clk200>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
clocks = <&clk60 &clk60>;
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
clocks = <&clk100>;
|
||||
};
|
||||
@@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal X-PRC-01 revA (SE1)
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "versal-vc-p-a2197-00-revA-x-prc-01-revA.dts"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1";
|
||||
stdout-path = "serial0:115200";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/* Mutually exclusive */
|
||||
&ospi {
|
||||
status = "okay"; /* U97 MT35XU02G */
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "disabled";
|
||||
};
|
||||
110
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-01-revA.dts
Normal file
110
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-01-revA.dts
Normal file
@@ -0,0 +1,110 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal X-PRC-01 revA (SE1)
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "versal-vc-p-a2197-00-revA.dts"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused";
|
||||
stdout-path = "serial0:115200";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
ethernet0 = &gem0;
|
||||
ethernet1 = &gem1;
|
||||
i2c0 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
gpio0 = &gpio;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay"; /* u93 and u92 */
|
||||
num-cs = <0x1>;
|
||||
is-dual = <0x1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "m25p80", "spi-flash";
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 { /* U104 */
|
||||
status = "okay";
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy1>; /* u128 */
|
||||
phy-mode = "rgmii-id";
|
||||
phy1: phy@1 {
|
||||
reg = <1>;
|
||||
ti,rx-internal-delay = <0xb>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <1>;
|
||||
ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */
|
||||
};
|
||||
phy2: phy@2 {
|
||||
reg = <2>;
|
||||
ti,rx-internal-delay = <0xb>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <1>;
|
||||
ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */
|
||||
};
|
||||
};
|
||||
|
||||
&gem1 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy2>; /* u134 */
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
eeprom_versal: eeprom@51 { /* U116 */
|
||||
compatible = "st,24c128", "atmel,24c128";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
/* FIXME - U117 and U118 */
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
xlnx,usb-polarity = <0x0>;
|
||||
xlnx,usb-reset-mode = <0x0>;
|
||||
};
|
||||
|
||||
&dwc3_0 { /* USB 2.0 host - U99 */
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
maximum-speed = "high-speed";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,usb3_lpm_capable;
|
||||
phy-names = "usb3-phy";
|
||||
};
|
||||
115
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-02-revA.dts
Normal file
115
arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-02-revA.dts
Normal file
@@ -0,0 +1,115 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal X-PRC-02 revA (SE2)
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "versal-vc-p-a2197-00-revA.dts"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused";
|
||||
stdout-path = "serial0:115200";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
ethernet0 = &gem0;
|
||||
i2c0 = &i2c1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
spi0 = &spi0;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem0 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>; /* u9 */
|
||||
phy-mode = "rgmii-id";
|
||||
phy0: phy@1 { /* Marvell 88E1512; U9 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
xlnx,mio_bank = <1>;
|
||||
};
|
||||
|
||||
&sdhci1 { /* U1A */
|
||||
status = "okay";
|
||||
non-removable;
|
||||
disable-wp;
|
||||
bus-width = <8>;
|
||||
xlnx,mio_bank = <0>;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
xlnx,usb-polarity = <0>;
|
||||
xlnx,usb-reset-mode = <0>;
|
||||
};
|
||||
|
||||
&dwc3_0 { /* U4 */
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
/* U12 Catalyst EEPROM - AT24 should be equivalent */
|
||||
eeprom_versal: eeprom@51 {
|
||||
compatible = "atmel,24c128";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
/* FIXME - U13 and U15 */
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
|
||||
flash@0 { /* U18 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25vf016b", "m25p80", "spi-flash";
|
||||
spi-max-frequency = <50000000>; /* FIXME */
|
||||
reg = <0x0>;
|
||||
|
||||
partition@0 {
|
||||
label = "spi0-flash0";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */
|
||||
|
||||
flash@1 { /* U19 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p80", "spi-flash";
|
||||
spi-max-frequency = <50000000>; /* FIXME */
|
||||
reg = <0x0>;
|
||||
|
||||
partition@1 {
|
||||
label = "spi1-flash0";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
27
arch/arm/dts/versal-vc-p-a2197-00-revA.dts
Normal file
27
arch/arm/dts/versal-vc-p-a2197-00-revA.dts
Normal file
@@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal
|
||||
*
|
||||
* (C) Copyright 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "versal.dtsi"
|
||||
#include "versal-fixed.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,versal-vc-p-a2197-00-revA",
|
||||
"xlnx,versal-vc-p-a2197-00",
|
||||
"xlnx,versal-vc-p-a2197", "xlnx,versal";
|
||||
model = "Xilinx Versal A2197 Processor board revA";
|
||||
|
||||
memory: memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
430
arch/arm/dts/versal.dtsi
Normal file
430
arch/arm/dts/versal.dtsi
Normal file
@@ -0,0 +1,430 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* dts file for Xilinx Versal
|
||||
*
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "xlnx,versal";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
model = "Xilinx Versal";
|
||||
|
||||
cpus: cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
dcc: dcc {
|
||||
compatible = "arm,dcc";
|
||||
status = "disabled";
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 13 4>,
|
||||
<1 14 4>,
|
||||
<1 11 4>,
|
||||
<1 10 4>;
|
||||
};
|
||||
|
||||
amba_apu: amba_apu {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@f9000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0 0xf9000000 0 0x80000>, /* GICD */
|
||||
<0 0xf9080000 0 0x80000>; /* GICR */
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <1 9 4>;
|
||||
};
|
||||
};
|
||||
|
||||
amba: amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-parent = <&gic>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
can0: can@ff060000 {
|
||||
compatible = "xlnx,canfd-2.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xff060000 0 0x6000>;
|
||||
interrupts = <0 20 1>;
|
||||
clock-names = "can_clk", "s_axi_aclk";
|
||||
rx-fifo-depth = <0x40>;
|
||||
tx-mailbox-count = <0x20>;
|
||||
};
|
||||
|
||||
can1: can@ff070000 {
|
||||
compatible = "xlnx,canfd-2.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xff070000 0 0x6000>;
|
||||
interrupts = <0 21 1>;
|
||||
clock-names = "can_clk", "s_axi_aclk";
|
||||
rx-fifo-depth = <0x40>;
|
||||
tx-mailbox-count = <0x20>;
|
||||
};
|
||||
|
||||
cci: cci@fd000000 {
|
||||
compatible = "arm,cci-500";
|
||||
status = "disabled";
|
||||
reg = <0 0xfd000000 0 0x10000>;
|
||||
ranges = <0 0 0xfd000000 0xa0000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cci_pmu: pmu@10000 {
|
||||
compatible = "arm,cci-500-pmu,r0";
|
||||
reg = <0x10000 0x90000>;
|
||||
interrupts = <0 106 4>,
|
||||
<0 106 4>,
|
||||
<0 106 4>,
|
||||
<0 106 4>,
|
||||
<0 106 4>,
|
||||
<0 106 4>,
|
||||
<0 106 4>,
|
||||
<0 106 4>,
|
||||
<0 106 4>;
|
||||
};
|
||||
};
|
||||
|
||||
lpd_dma_chan0: dma@ffa80000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffa80000 0 0x1000>;
|
||||
interrupts = <0 60 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x210>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
lpd_dma_chan1: dma@ffa90000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffa90000 0 0x1000>;
|
||||
interrupts = <0 61 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x212>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
lpd_dma_chan2: dma@ffaa0000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffaa0000 0 0x1000>;
|
||||
interrupts = <0 62 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x214>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
|
||||
lpd_dma_chan3: dma@ffab0000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffab0000 0 0x1000>;
|
||||
interrupts = <0 63 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x216>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
lpd_dma_chan4: dma@ffac0000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffac0000 0 0x1000>;
|
||||
interrupts = <0 64 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x218>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
lpd_dma_chan5: dma@ffad0000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffad0000 0 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x21a>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
lpd_dma_chan6: dma@ffae0000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffae0000 0 0x1000>;
|
||||
interrupts = <0 66 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x21c>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
lpd_dma_chan7: dma@ffaf0000 {
|
||||
compatible = "xlnx,zynqmp-dma-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xffaf0000 0 0x1000>;
|
||||
interrupts = <0 67 4>;
|
||||
clock-names = "clk_main", "clk_apb";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x21e>; */
|
||||
xlnx,bus-width = <64>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
gem0: ethernet@ff0c0000 {
|
||||
compatible = "cdns,zynqmp-gem";
|
||||
status = "disabled";
|
||||
reg = <0 0xff0c0000 0 0x1000>;
|
||||
interrupts = <0 56 4>, <0 56 4>;
|
||||
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x234>; */
|
||||
/* dma-coherent; */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gem1: ethernet@ff0d0000 {
|
||||
compatible = "cdns,zynqmp-gem";
|
||||
status = "disabled";
|
||||
reg = <0 0xff0d0000 0 0x1000>;
|
||||
interrupts = <0 58 4>, <0 58 4>;
|
||||
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x235>; */
|
||||
/* dma-coherent; */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
gpio: gpio@ff0b0000 {
|
||||
compatible = "xlnx,versal-gpio-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xff0b0000 0 0x1000>;
|
||||
interrupts = <0 13 4>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
i2c0: i2c@ff020000 {
|
||||
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
reg = <0 0xff020000 0 0x1000>;
|
||||
interrupts = <0 14 4>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@ff030000 {
|
||||
compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
reg = <0 0xff030000 0 0x1000>;
|
||||
interrupts = <0 15 4>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
rtc: rtc@f12a0000 {
|
||||
compatible = "xlnx,zynqmp-rtc";
|
||||
status = "disabled";
|
||||
reg = <0 0xf12a0000 0 0x100>;
|
||||
interrupt-names = "alarm", "sec";
|
||||
interrupts = <0 142 4>, <0 143 4>;
|
||||
calibration = <0x8000>;
|
||||
};
|
||||
|
||||
sdhci0: sdhci@f1040000 {
|
||||
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
reg = <0 0xf1040000 0 0x10000>;
|
||||
interrupts = <0 126 4>, <0 126 4>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
xlnx,device_id = <0>;
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x242>; */
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
sdhci1: sdhci@f1050000 {
|
||||
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
|
||||
status = "disabled";
|
||||
reg = <0 0xf1050000 0 0x10000>;
|
||||
interrupts = <0 128 4>, <0 128 4>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
xlnx,device_id = <1>;
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x243>; */
|
||||
/* dma-coherent; */
|
||||
};
|
||||
|
||||
serial0: serial@ff000000 {
|
||||
compatible = "arm,pl011", "arm,sbsa-uart";
|
||||
status = "disabled";
|
||||
reg = <0 0xff000000 0 0x1000>;
|
||||
interrupts = <0 18 4>;
|
||||
clock-names = "uart_clk", "apb_clk";
|
||||
current-speed = <115200>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
serial1: serial@ff010000 {
|
||||
compatible = "arm,pl011", "arm,sbsa-uart";
|
||||
status = "disabled";
|
||||
reg = <0 0xff010000 0 0x1000>;
|
||||
interrupts = <0 19 4>;
|
||||
clock-names = "uart_clk", "apb_clk";
|
||||
current-speed = <115200>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
smmu: smmu@fd800000 {
|
||||
compatible = "arm,mmu-500";
|
||||
status = "disabled";
|
||||
reg = <0 0xfd800000 0 0x40000>;
|
||||
stream-match-mask = <0x7c00>;
|
||||
#iommu-cells = <1>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>,
|
||||
<0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>;
|
||||
};
|
||||
|
||||
ospi: spi@f1010000 {
|
||||
compatible = "cdns,qspi-nor";
|
||||
status = "disabled";
|
||||
reg = <0 0xf1010000 0 0x1000>;
|
||||
interrupts = <0 125 4>, <0 125 4>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
cdns,fifo-depth = <508>;
|
||||
cdns,fifo-width = <4>;
|
||||
cdns,is-dma = <1>;
|
||||
cdns,is-stig-pgm = <1>;
|
||||
cdns,trigger-address = <0x00000000>;
|
||||
#stream-id-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
qspi: spi@f1030000 {
|
||||
compatible = "xlnx,versal-qspi-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xf1030000 0 0x1000>;
|
||||
interrupts = <0 125 4>, <0 125 4>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x244>; */
|
||||
/* dma-coherent; */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
|
||||
spi0: spi@ff040000 {
|
||||
compatible = "cdns,spi-r1p6";
|
||||
status = "disabled";
|
||||
reg = <0 0xff040000 0 0x1000>;
|
||||
interrupts = <0 16 4>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@ff050000 {
|
||||
compatible = "cdns,spi-r1p6";
|
||||
status = "disabled";
|
||||
reg = <0 0xff050000 0 0x1000>;
|
||||
interrupts = <0 17 4>;
|
||||
clock-names = "ref_clk", "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
usb0: usb@ff9d0000 {
|
||||
compatible = "xlnx,versal-dwc3";
|
||||
status = "disabled";
|
||||
reg = <0 0xff9d0000 0 0x100>;
|
||||
clock-names = "bus_clk", "ref_clk";
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
dwc3_0: dwc3@fe200000 {
|
||||
compatible = "snps,dwc3";
|
||||
status = "disabled";
|
||||
reg = <0 0xfe200000 0 0x10000>;
|
||||
interrupt-names = "dwc_usb3", "otg";
|
||||
interrupts = <0 0x16 4>, <0 0x1A 4>;
|
||||
#stream-id-cells = <1>;
|
||||
/* iommus = <&smmu 0x230>; */
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@fd4d0000 {
|
||||
compatible = "xlnx,versal-wwdt-1.0";
|
||||
status = "disabled";
|
||||
reg = <0 0xfd4d0000 0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
@@ -187,7 +187,7 @@ marwell m88e1512 - SGMII */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
/* FIXME check alerts comming to SC */
|
||||
/* FIXME check alerts coming to SC */
|
||||
vcc_fmc: ina226@42 { /* u81 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x42>;
|
||||
@@ -291,7 +291,7 @@ marwell m88e1512 - SGMII */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
/* FIXME check alerts comming to SC */
|
||||
/* FIXME check alerts coming to SC */
|
||||
vccaux: ina226@40 { /* u89 */
|
||||
compatible = "ti,ina226";
|
||||
reg = <0x40>;
|
||||
|
||||
@@ -44,6 +44,9 @@ CONFIG_ISO_PARTITION=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_PARTITION_UUIDS is not set
|
||||
CONFIG_OF_BOARD=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="versal-vc-p-a2197-00-revA-x-prc-01-revA"
|
||||
CONFIG_OF_LIST="versal-vc-p-a2197-00-revA-x-prc-01-revA versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi versal-vc-p-a2197-00-revA-x-prc-02-revA"
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_DFU_RAM=y
|
||||
|
||||
Reference in New Issue
Block a user