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net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps

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For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.

The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.

Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.

Fix the check by using the bit width instead of hardcoded value(s).

Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Andreas Pretzsch 2018-11-29 20:04:53 +01:00 committed by Joe Hershberger
parent be09f5bc7c
commit 3b4cda34d4
1 changed files with 2 additions and 2 deletions
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4
drivers/net/phy/micrel_ksz90x1.c
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@ -123,8 +123,8 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
} else {
changed = 1; /* Value was changed in OF */
/* Calculate the register value and fix corner cases */
if (val[i] > ps_to_regval * 0xf) {
max = (1 << ofcfg->grp[i].size) - 1;
max = (1 << ofcfg->grp[i].size) - 1;
if (val[i] > ps_to_regval * max) {
regval |= max << offset;
} else {
regval |= (val[i] / ps_to_regval) << offset;