Merge branch 'master' of git://git.denx.de/u-boot-ti
This commit is contained in:
Tom Rini
@@ -249,6 +249,49 @@ enum {
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#define MICRON_RASWIDTH_200 14
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#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
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/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
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#define SAMSUNG_TDAL_165 5
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#define SAMSUNG_TDPL_165 2
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#define SAMSUNG_TRRD_165 2
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#define SAMSUNG_TRCD_165 3
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#define SAMSUNG_TRP_165 3
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#define SAMSUNG_TRAS_165 7
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#define SAMSUNG_TRC_165 10
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#define SAMSUNG_TRFC_165 12
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#define SAMSUNG_V_ACTIMA_165 \
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ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
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SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
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SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
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SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
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#define SAMSUNG_TWTR_165 1
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#define SAMSUNG_TCKE_165 2
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#define SAMSUNG_XSR_165 20
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#define SAMSUNG_TXP_165 5
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#define SAMSUNG_V_ACTIMB_165 \
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ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
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SAMSUNG_TXP_165, SAMSUNG_XSR_165)
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#define SAMSUNG_RASWIDTH_165 14
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#define SAMSUNG_V_MCFG_165(size) \
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V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
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V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
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V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
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/* TODO: find which register these were taken from */
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#define SAMSUNG_BL_165 0x2
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#define SAMSUNG_SIL_165 0x0
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#define SAMSUNG_CASL_165 0x3
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#define SAMSUNG_WBST_165 0x0
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#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
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(SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
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(SAMSUNG_BL_165))
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#define SAMSUNG_SHARING 0x00003700
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/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
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#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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@@ -51,6 +51,7 @@ typedef struct t2 {
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#define PBIASLITEPWRDNZ0 (1 << 1)
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#define PBIASSPEEDCTRL0 (1 << 2)
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#define PBIASLITEPWRDNZ1 (1 << 9)
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#define PBIASLITEVMODE0 (1 << 0)
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#define CTLPROGIO1SPEEDCTRL (1 << 20)
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@@ -15,6 +15,12 @@
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* SB_LOW - Standby mode configuration: Output low-level
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* SB_HI - Standby mode configuration: Output high-level
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* SB_HIZ - Standby mode configuration: Output hi-impedence
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* SB_PD - Standby mode pull-down enabled
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* SB_PU - Standby mode pull-up enabled
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* WKEN - Wakeup input enabled
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* M0 - Mode 0
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*/
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@@ -26,6 +32,13 @@
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#define EN (1 << 3)
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#define DIS (0 << 3)
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#define SB_LOW (1 << 9)
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#define SB_HI (5 << 9)
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#define SB_HIZ (2 << 9)
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#define SB_PD (1 << 12)
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#define SB_PU (3 << 12)
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#define WKEN (1 << 14)
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#define M0 0
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#define M1 1
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#define M2 2
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@@ -36,8 +49,8 @@
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#define M7 7
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/*
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* To get the actual address the offset has to added
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* with OMAP34XX_CTRL_BASE to get the actual address
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* To get the actual address the offset has to be added
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* to OMAP34XX_CTRL_BASE
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*/
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/*SDRC*/
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@@ -78,6 +91,33 @@
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#define CONTROL_PADCONF_SDRC_DQS1 0x0074
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#define CONTROL_PADCONF_SDRC_DQS2 0x0076
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#define CONTROL_PADCONF_SDRC_DQS3 0x0078
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#define CONTROL_PADCONF_SDRC_BA0 0x05A0
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#define CONTROL_PADCONF_SDRC_BA1 0x05A2
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#define CONTROL_PADCONF_SDRC_A0 0x05A4
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#define CONTROL_PADCONF_SDRC_A1 0x05A6
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#define CONTROL_PADCONF_SDRC_A2 0x05A8
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#define CONTROL_PADCONF_SDRC_A3 0x05AA
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#define CONTROL_PADCONF_SDRC_A4 0x05AC
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#define CONTROL_PADCONF_SDRC_A5 0x05AE
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#define CONTROL_PADCONF_SDRC_A6 0x05B0
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#define CONTROL_PADCONF_SDRC_A7 0x05B2
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#define CONTROL_PADCONF_SDRC_A8 0x05B4
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#define CONTROL_PADCONF_SDRC_A9 0x05B6
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#define CONTROL_PADCONF_SDRC_A10 0x05B8
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#define CONTROL_PADCONF_SDRC_A11 0x05BA
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#define CONTROL_PADCONF_SDRC_A12 0x05BC
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#define CONTROL_PADCONF_SDRC_A13 0x05BE
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#define CONTROL_PADCONF_SDRC_A14 0x05C0
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#define CONTROL_PADCONF_SDRC_NCS0 0x05C2
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#define CONTROL_PADCONF_SDRC_NCS1 0x05C4
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#define CONTROL_PADCONF_SDRC_NCLK 0x05C6
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#define CONTROL_PADCONF_SDRC_NRAS 0x05C8
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#define CONTROL_PADCONF_SDRC_NCAS 0x05CA
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#define CONTROL_PADCONF_SDRC_NWE 0x05CC
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#define CONTROL_PADCONF_SDRC_DM0 0x05CE
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#define CONTROL_PADCONF_SDRC_DM1 0x05D0
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#define CONTROL_PADCONF_SDRC_DM2 0x05D2
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#define CONTROL_PADCONF_SDRC_DM3 0x05D4
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/*GPMC*/
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#define CONTROL_PADCONF_GPMC_A1 0x007A
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#define CONTROL_PADCONF_GPMC_A2 0x007C
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@@ -89,6 +129,7 @@
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#define CONTROL_PADCONF_GPMC_A8 0x0088
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#define CONTROL_PADCONF_GPMC_A9 0x008A
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#define CONTROL_PADCONF_GPMC_A10 0x008C
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#define CONTROL_PADCONF_GPMC_A11 0x0264
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#define CONTROL_PADCONF_GPMC_D0 0x008E
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#define CONTROL_PADCONF_GPMC_D1 0x0090
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#define CONTROL_PADCONF_GPMC_D2 0x0092
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@@ -323,6 +364,8 @@
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#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
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#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
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#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
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#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
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#define CONTROL_PADCONF_JTAG_TDO 0x0A50
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/*Die to Die */
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#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
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#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
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@@ -433,6 +476,10 @@
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#define CONTROL_PADCONF_SYS_BOOT8 0x0226
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/* AM/DM37xx specific */
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#define CONTROL_PADCONF_GPIO112 0x0134
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#define CONTROL_PADCONF_GPIO113 0x0136
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#define CONTROL_PADCONF_GPIO114 0x0138
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#define CONTROL_PADCONF_GPIO115 0x013A
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#define CONTROL_PADCONF_GPIO127 0x0A54
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#define CONTROL_PADCONF_GPIO126 0x0A56
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#define CONTROL_PADCONF_GPIO128 0x0A58
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@@ -23,6 +23,7 @@ struct emu_hal_params {
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/* Board SDRC timing values */
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struct board_sdrc_timings {
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u32 sharing;
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u32 mcfg;
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u32 ctrla;
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u32 ctrlb;
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@@ -236,13 +236,20 @@
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#define VDD_MPU_ES2_LOW 880
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#define VDD_MM_ES2_LOW 880
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/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
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#define VDD_MPU_DRA752 1090
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/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
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#define VDD_MPU_DRA752 1100
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#define VDD_EVE_DRA752 1060
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#define VDD_GPU_DRA752 1060
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#define VDD_CORE_DRA752 1030
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#define VDD_CORE_DRA752 1060
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#define VDD_IVA_DRA752 1060
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/* DRA72x voltage settings in mv for OPP_NOM per DM */
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#define VDD_MPU_DRA72x 1100
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#define VDD_EVE_DRA72x 1060
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#define VDD_GPU_DRA72x 1060
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#define VDD_CORE_DRA72x 1060
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#define VDD_IVA_DRA72x 1060
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/* Efuse register offsets for DRA7xx platform */
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#define DRA752_EFUSE_BASE 0x4A002000
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#define DRA752_EFUSE_REGBITS 16
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@@ -284,6 +291,13 @@
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#define TPS659038_REG_ADDR_SMPS7 0x33
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#define TPS659038_REG_ADDR_SMPS8 0x37
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/* TPS65917 */
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#define TPS65917_I2C_SLAVE_ADDR 0x58
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#define TPS65917_REG_ADDR_SMPS1 0x23
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#define TPS65917_REG_ADDR_SMPS2 0x27
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#define TPS65917_REG_ADDR_SMPS3 0x2F
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/* TPS */
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#define TPS62361_I2C_SLAVE_ADDR 0x60
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#define TPS62361_REG_ADDR_SET0 0x0
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