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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Minkyu Kang 2010-11-02 14:09:18 +09:00
commit 37a3bda0c9
199 changed files with 6679 additions and 5945 deletions
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18
MAINTAINERS
View File

@ -102,7 +102,6 @@ Wolfgang Denk <wd@denx.de>
IVMS8_256 MPC860
LANTEC MPC850
LWMON MPC823
NC650 MPC852
R360MPI MPC823
RMU MPC850
RRvision MPC823
@ -573,6 +572,10 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Andreas Bießmann <andreas.devel@gmail.com>
at91rm9200ek at91rm9200
Cliff Brake <cliff.brake@gmail.com>
pxa255_idp xscale
@ -598,6 +601,10 @@ Thomas Elste <info@elste.org>
modnet50 ARM720T (NET+50)
Kristoffer Ericson <kristoffer.ericson@gmail.com>
jornada SA1110
Fabio Estevam <Fabio.Estevam@freescale.com>
mx31pdk i.MX31
@ -805,6 +812,15 @@ Greg Ungerer <greg.ungerer@opengear.com>
cm4116 ks8695p
cm4148 ks8695p
Marek Vasut <marek.vasut@gmail.com>
balloon3 xscale
colibri_pxa270 xscale
palmld xscale
palmtc xscale
vpac270 xscale
zipitz2 xscale
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
SFFSDR ARM926EJS

7
MAKEALL
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@ -468,12 +468,7 @@ LIST_at91=" \
## Xscale Systems
#########################################################################
LIST_pxa="$(boards_by_cpu pxa)
polaris \
trizepsiv \
vpac270_nor \
vpac270_onenand \
"
LIST_pxa="$(boards_by_cpu pxa)"
LIST_ixp="$(boards_by_cpu ixp)
pdnb3 \

36
Makefile
View File

@ -304,6 +304,21 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
#########################################################################
#########################################################################
ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
BOARD_SIZE_CHECK = \
@actual=`wc -c $@ | awk '{print $$1}'`; \
limit=$(CONFIG_BOARD_SIZE_LIMIT); \
if test $$actual -gt $$limit; then \
echo "$@ exceeds file size limit:"; \
echo " limit: $$limit bytes"; \
echo " actual: $$actual bytes"; \
echo " excess: $$((actual - limit)) bytes"; \
exit 1; \
fi
else
BOARD_SIZE_CHECK =
endif
# Always append ALL so that arch config.mk's can add custom ones
ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
@ -317,10 +332,12 @@ $(obj)u-boot.srec: $(obj)u-boot
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr: $(obj)u-boot
$(CREATE_LDR_ENV)
$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
$(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
@ -341,7 +358,7 @@ $(obj)u-boot.imx: $(obj)u-boot.bin
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(TEXT_BASE) -d $< $@
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
@ -1010,23 +1027,6 @@ scpu_config: unconfig
fi
@$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive
polaris_config \
trizepsiv_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring polaris,$@)" ] ; then \
echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
vpac270_nor_config \
vpac270_onenand_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring onenand,$@)" ] ; then \
echo "#define CONFIG_ONENAND_U_BOOT" \
>>$(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
#########################################################################
## ARM1136 Systems
#########################################################################

12
arch/arm/config.mk
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@ -33,11 +33,6 @@ STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
# needed for relocation
PLATFORM_RELFLAGS += -fPIC
endif
ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
endif
@ -72,3 +67,10 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
endif
endif
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
# needed for relocation
ifndef CONFIG_NAND_SPL
PLATFORM_LDFLAGS += -pie
endif
endif

7
arch/arm/cpu/arm1136/mx31/generic.c
View File

@ -93,17 +93,16 @@ void mx31_gpio_mux(unsigned long mode)
void mx31_set_pad(enum iomux_pins pin, u32 config)
{
u32 field, l;
void *reg;
u32 field, l, reg;
pin &= IOMUX_PADNUM_MASK;
reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
l = __raw_readl(reg);
l = __REG(reg);
l &= ~(0x1ff << (field * 10));
l |= config << (field * 10);
__raw_writel(l, reg);
__REG(reg) = l;
}

171
arch/arm/cpu/arm1136/start.S
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@ -89,48 +89,35 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end
_bss_end:
.word _end
.globl _bss_end_ofs
_bss_end_ofs:
.word _end - _start
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _datarel_start
_datarel_start:
.word __datarel_start
.globl _datarel_start_ofs
_datarel_start_ofs:
.word __datarel_start - _start
.globl _datarelrolocal_start
_datarelrolocal_start:
.word __datarelrolocal_start
.globl _datarelrolocal_start_ofs
_datarelrolocal_start_ofs:
.word __datarelrolocal_start - _start
.globl _datarellocal_start
_datarellocal_start:
.word __datarellocal_start
.globl _datarellocal_start_ofs
_datarellocal_start_ofs:
.word __datarellocal_start - _start
.globl _datarelro_start
_datarelro_start:
.word __datarelro_start
.globl _got_start
_got_start:
.word __got_start
.globl _got_end
_got_end:
.word __got_end
#endif
.globl _datarelro_start_ofs
_datarelro_start_ofs:
.word __datarelro_start - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@ -225,9 +212,8 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
@ -239,36 +225,54 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
ldr r1, _TEXT_BASE
mov r0, r7 /* reloc addr */
ldr r2, _got_start /* addr in Flash */
ldr r3, _got_end /* addr in Flash */
sub r3, r3, r1
add r3, r3, r0
sub r2, r2, r1
add r2, r2, r0
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r4, [r2]
sub r4, r4, r1
add r4, r4, r0
str r4, [r2]
add r2, r2, #4
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
bne fixloop
ble fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start
ldr r1, _bss_end
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
sub r0, r0, r3
add r0, r0, r4
sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -283,24 +287,34 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
ldr pc, _nand_boot
_nand_boot: .word nand_boot
ldr r0, _nand_boot_ofs
adr r1, _start
add pc, r0, r1
_nand_boot_ofs
: .word nand_boot - _start
#else
jump_2_ram:
ldr r0, _TEXT_BASE
ldr r2, _board_init_r
sub r2, r2, r0
add r2, r2, r7 /* position from board_init_r in RAM */
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
mov lr, r2
mov pc, lr
_board_init_r: .word board_init_r
_board_init_r_ofs:
.word board_init_r - _start
#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
@ -375,8 +389,11 @@ stack_setup:
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
adr r2, _start
ldr r0, _bss_start_ofs /* find start of bss segment */
add r0, r0, r2
ldr r1, _bss_end_ofs /* stop here */
add r1, r1, r2
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
@ -386,15 +403,19 @@ clbss_l:str r2, [r0] /* clear loop... */
bne clbss_l
#endif
ldr pc, _start_armboot
ldr r0, _start_armboot_ofs
adr r1, _start
add r0, r0, r1
ldr pc, r0
_start_armboot_ofs:
#ifdef CONFIG_NAND_SPL
_start_armboot: .word nand_boot
.word nand_boot - _start
#else
#ifdef CONFIG_ONENAND_IPL
_start_armboot: .word start_oneboot
.word start_oneboot - _start
#else
_start_armboot: .word start_armboot
.word start_armboot - _start
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_NAND_SPL */
@ -487,7 +508,7 @@ cpu_init_crit:
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
#else
ldr r2, _armboot_start
adr r2, _start
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#endif
@ -524,8 +545,8 @@ cpu_init_crit:
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
#else
ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
adr r13, _start @ setup our mode stack (enter in banked mode)
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
#endif

15
arch/arm/cpu/arm1136/u-boot.lds
View File

@ -59,11 +59,14 @@ SECTIONS
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
__dynsym_start = .;
.dynsym : { *(.dynsym) }
__got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
@ -73,4 +76,10 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

55
arch/arm/cpu/arm926ejs/at91/clock.c
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@ -11,47 +11,46 @@
* (at your option) any later version.
*/
#include <config.h>
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
static unsigned long cpu_clk_rate_hz;
static unsigned long main_clk_rate_hz;
static unsigned long mck_rate_hz;
static unsigned long plla_rate_hz;
static unsigned long pllb_rate_hz;
static u32 at91_pllb_usb_init;
#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
DECLARE_GLOBAL_DATA_PTR;
unsigned long get_cpu_clk_rate(void)
{
return cpu_clk_rate_hz;
return gd->cpu_clk_rate_hz;
}
unsigned long get_main_clk_rate(void)
{
return main_clk_rate_hz;
return gd->main_clk_rate_hz;
}
unsigned long get_mck_clk_rate(void)
{
return mck_rate_hz;
return gd->mck_rate_hz;
}
unsigned long get_plla_clk_rate(void)
{
return plla_rate_hz;
return gd->plla_rate_hz;
}
unsigned long get_pllb_clk_rate(void)
{
return pllb_rate_hz;
return gd->pllb_rate_hz;
}
u32 get_pllb_init(void)
{
return at91_pllb_usb_init;
return gd->at91_pllb_usb_init;
}
static unsigned long at91_css_to_rate(unsigned long css)
@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
case AT91_PMC_MCKR_CSS_SLOW:
return AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return main_clk_rate_hz;
return gd->main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
return plla_rate_hz;
return gd->plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
return pllb_rate_hz;
return gd->pllb_rate_hz;
}
return 0;
@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock)
main_clock = tmp * (AT91_SLOW_CLOCK / 16);
}
#endif
main_clk_rate_hz = main_clock;
gd->main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock)
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2;
pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
#endif
/*
@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock)
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* plla divisor by 2 */
plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = mck_rate_hz;
gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
/* mdiv */
mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#elif defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
cpu_clk_rate_hz = freq;
gd->cpu_clk_rate_hz = freq;
return 0;
}

85
arch/arm/cpu/arm926ejs/at91/timer.c
View File

@ -30,55 +30,63 @@
#include <asm/arch/io.h>
#include <div64.h>
#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
* (See the relevant data sheets to understand that this really works)
*
* We do also mimic the typical powerpc way of incrementing
* two 32 bit registers called tbl and tbu.
*
* Those registers increment at 1/16 the main clock rate.
*/
#define TIMER_LOAD_VAL 0xfffff
static ulong timestamp;
static ulong lastinc;
static ulong timer_freq;
#define TIMER_LOAD_VAL 0xfffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, timer_freq);
do_div(tick, gd->timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= timer_freq;
usec *= gd->timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
/* nothing really to do with interrupts, just starts up a counter. */
/*
* Use the PITC in full 32 bit incrementing mode
*/
int timer_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/*
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
/* Enable PITC Clock */
writel(1 << AT91_ID_SYS, &pmc->pcer);
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
reset_timer_masked();
timer_freq = get_mck_clk_rate() >> 4;
gd->timer_rate_hz = gd->mck_rate_hz / 16;
gd->tbu = gd->tbl = 0;
return 0;
}
/*
* timer without interrupts
* Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
@ -86,28 +94,11 @@ unsigned long long get_ticks(void)
ulong now = readl(&pit->piir);
if (now >= lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
timestamp += (now - lastinc);
else /* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
lastinc = now;
return timestamp;
}
void reset_timer_masked(void)
{
/* reset time */
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/* capture current incrementer value time */
lastinc = readl(&pit->piir);
timestamp = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked(void)
{
return tick_to_time(get_ticks());
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
gd->tbu++;
gd->tbl = now;
return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
@ -119,24 +110,32 @@ void __udelay(unsigned long usec)
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
;
}
/*
* reset_timer() and get_timer(base) are a pair of functions that are used by
* some timeout/sleep mechanisms in u-boot.
*
* reset_timer() marks the current time as epoch and
* get_timer(base) works relative to that epoch.
*
* The time is used in CONFIG_SYS_HZ units!
*/
void reset_timer(void)
{
reset_timer_masked();
gd->timer_reset_value = get_ticks();
}
ulong get_timer(ulong base)
{
return get_timer_masked () - base;
return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
* Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return timer_freq;
return gd->timer_rate_hz;
}

162
arch/arm/cpu/arm926ejs/start.S
View File

@ -10,6 +10,7 @@
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
* Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -118,22 +119,19 @@ _fiq:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end
_bss_end:
.word _end
.globl _bss_end_ofs
_bss_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@ -153,30 +151,6 @@ FIQ_STACK_START:
IRQ_STACK_START_IN:
.word 0x0badc0de
.globl _datarel_start
_datarel_start:
.word __datarel_start
.globl _datarelrolocal_start
_datarelrolocal_start:
.word __datarelrolocal_start
.globl _datarellocal_start
_datarellocal_start:
.word __datarellocal_start
.globl _datarelro_start
_datarelro_start:
.word __datarelro_start
.globl _got_start
_got_start:
.word __got_start
.globl _got_end
_got_end:
.word __got_end
/*
* the actual reset code
*/
@ -226,9 +200,8 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
@ -240,36 +213,54 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
ldr r1, _TEXT_BASE /* Text base */
mov r0, r7 /* reloc addr */
ldr r2, _got_start /* addr in Flash */
ldr r3, _got_end /* addr in Flash */
sub r3, r3, r1
add r3, r3, r0
sub r2, r2, r1
add r2, r2, r0
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r4, [r2]
sub r4, r4, r1
add r4, r4, r0
str r4, [r2]
add r2, r2, #4
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start
ldr r1, _bss_end
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
sub r0, r0, r3
add r0, r0, r4
sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -287,24 +278,33 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
ldr pc, _nand_boot
ldr r0, _nand_boot_ofs
mov pc, r0
_nand_boot: .word nand_boot
_nand_boot_ofs:
.word nand_boot
#else
ldr r0, _TEXT_BASE
ldr r2, _board_init_r
sub r2, r2, r0
add r2, r2, r7 /* position from board_init_r in RAM */
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
mov lr, r2
mov pc, lr
_board_init_r: .word board_init_r
_board_init_r_ofs:
.word board_init_r - _start
#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
@ -333,10 +333,8 @@ relocate: /* relocate U-Boot to RAM */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs /* r3 <- _bss_start - _start */
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
@ -360,8 +358,11 @@ stack_setup:
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
adr r2, _start
ldr r0, _bss_start_ofs /* find start of bss segment */
add r0, r0, r2
ldr r1, _bss_end_ofs /* stop here */
add r1, r1, r2
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
@ -374,13 +375,16 @@ clbss_l:str r2, [r0] /* clear loop... */
bl red_LED_on
#endif /* CONFIG_PRELOADER */
ldr pc, _start_armboot
ldr r0, _start_armboot_ofs
adr r1, _start
add r0, r0, r1
ldr pc, r0
_start_armboot:
_start_armboot_ofs:
#ifdef CONFIG_NAND_SPL
.word nand_boot
.word nand_boot - _start
#else
.word start_armboot
.word start_armboot - _start
#endif /* CONFIG_NAND_SPL */
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
@ -469,7 +473,7 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
adr r2, _start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
@ -507,7 +511,7 @@ cpu_init_crit:
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
adr r13, _start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else

26
arch/arm/cpu/arm926ejs/u-boot.lds
View File

@ -41,21 +41,19 @@ SECTIONS
. = ALIGN(4);
.data : {
*(.data)
__datarel_start = .;
*(.data.rel)
__datarelrolocal_start = .;
*(.data.rel.ro.local)
__datarellocal_start = .;
*(.data.rel.local)
__datarelro_start = .;
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__got_end = .;
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
__dynsym_start = .;
.dynsym : { *(.dynsym) }
. = ALIGN(4);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
@ -65,4 +63,10 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

0
arch/arm/cpu/armv7/mx51/Makefile → arch/arm/cpu/armv7/mx5/Makefile
View File

42
arch/arm/cpu/armv7/mx51/clock.c → arch/arm/cpu/armv7/mx5/clock.c
View File

@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void)
reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
MXC_CCM_CACRR_ARM_PODF_OFFSET;
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
return freq / (reg + 1);
}
@ -84,14 +84,14 @@ static u32 get_periph_clk(void)
reg = __raw_readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
reg = __raw_readl(&mxc_ccm->cbcmr);
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
case 0:
return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
case 1:
return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
default:
return 0;
}
@ -146,15 +146,15 @@ static u32 get_uart_clk(void)
MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
case 0x0:
freq = decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_MX51_HCLK_FREQ);
CONFIG_SYS_MX5_HCLK);
break;
case 0x1:
freq = decode_pll(mxc_plls[PLL2_CLOCK],
CONFIG_MX51_HCLK_FREQ);
CONFIG_SYS_MX5_HCLK);
break;
case 0x2:
freq = decode_pll(mxc_plls[PLL3_CLOCK],
CONFIG_MX51_HCLK_FREQ);
CONFIG_SYS_MX5_HCLK);
break;
default:
return 66500000;
@ -181,7 +181,7 @@ u32 get_lp_apm(void)
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
if (((ccsr >> 9) & 1) == 0)
ret_val = CONFIG_MX51_HCLK_FREQ;
ret_val = CONFIG_SYS_MX5_HCLK;
else
ret_val = ((32768 * 1024));
@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void)
switch (clk_sel) {
case 0:
ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_MX51_HCLK_FREQ) /
CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 1:
ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
CONFIG_MX51_HCLK_FREQ) /
CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 2:
ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
CONFIG_MX51_HCLK_FREQ) /
CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return imx_get_cspiclk();
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
CONFIG_MX51_HCLK_FREQ);
CONFIG_SYS_MX5_HCLK);
default:
break;
}
@ -269,16 +269,16 @@ u32 imx_get_fecclk(void)
/*
* Dump some core clockes.
*/
int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u32 freq;
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
printf("mx51 pll1: %dMHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
printf("mx51 pll2: %dMHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
printf("mx51 pll3: %dMHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
printf("pll1: %dMHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
printf("pll2: %dMHz\n", freq / 1000000);
freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
printf("pll3: %dMHz\n", freq / 1000000);
printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
/***************************************************/
U_BOOT_CMD(
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
"display mx51 clocks\n",
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
"display clocks\n",
""
);

2
arch/arm/cpu/armv7/mx51/iomux.c → arch/arm/cpu/armv7/mx5/iomux.c
View File

@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx51_pins.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>

14
arch/arm/cpu/armv7/mx51/lowlevel_init.S → arch/arm/cpu/armv7/mx5/lowlevel_init.S
View File

@ -257,20 +257,6 @@ lowlevel_init:
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
#ifdef ENABLE_IMPRECISE_ABORT
mrs r1, spsr /* save old spsr */
mrs r0, cpsr /* read out the cpsr */
bic r0, r0, #0x100 /* clear the A bit */
msr spsr, r0 /* update spsr */
add lr, pc, #0x8 /* update lr */
movs pc, lr /* update cpsr */
nop
nop
nop
nop
msr spsr, r1 /* restore old spsr */
#endif
init_l2cc
init_aips

28
arch/arm/cpu/armv7/mx51/soc.c → arch/arm/cpu/armv7/mx5/soc.c
View File

@ -33,28 +33,33 @@
#include <fsl_esdhc.h>
#endif
#if defined(CONFIG_MX51)
#define CPU_TYPE 0x51000
#else
#error "CPU_TYPE not defined"
#endif
u32 get_cpu_rev(void)
{
int reg;
int system_rev;
int system_rev = CPU_TYPE;
int reg = __raw_readl(ROM_SI_REV);
reg = __raw_readl(ROM_SI_REV);
switch (reg) {
case 0x02:
system_rev = 0x51000 | CHIP_REV_1_1;
system_rev |= CHIP_REV_1_1;
break;
case 0x10:
if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
system_rev = 0x51000 | CHIP_REV_2_5;
system_rev |= CHIP_REV_2_5;
else
system_rev = 0x51000 | CHIP_REV_2_0;
system_rev |= CHIP_REV_2_0;
break;
case 0x20:
system_rev = 0x51000 | CHIP_REV_3_0;
system_rev |= CHIP_REV_3_0;
break;
return system_rev;
default:
system_rev = 0x51000 | CHIP_REV_1_0;
system_rev |= CHIP_REV_1_0;
break;
}
return system_rev;
@ -67,9 +72,10 @@ int print_cpuinfo(void)
u32 cpurev;
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
(cpurev & 0xF0) >> 4,
(cpurev & 0x0F) >> 4,
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
(cpurev & 0xFF000) >> 12,
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
return 0;
}

0
arch/arm/cpu/armv7/mx51/speed.c → arch/arm/cpu/armv7/mx5/speed.c
View File

8
arch/arm/cpu/armv7/mx51/timer.c → arch/arm/cpu/armv7/mx5/timer.c
View File

@ -75,18 +75,18 @@ void reset_timer(void)
void reset_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
}
ulong get_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
if (val >= lastinc)
timestamp += (val - lastinc);
else
timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
- lastinc) + val;
lastinc = val;
return timestamp;
@ -106,7 +106,7 @@ void set_timer(ulong t)
void __udelay(unsigned long usec)
{
unsigned long now, start, tmo;
tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
if (!tmo)
tmo = 1;

0
arch/arm/cpu/armv7/mx51/u-boot.lds → arch/arm/cpu/armv7/mx5/u-boot.lds
View File

131
arch/arm/cpu/armv7/start.S
View File

@ -78,13 +78,13 @@ _armboot_start:
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end
_bss_end:
.word _end
.globl _bss_end_ofs
_bss_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@ -104,29 +104,29 @@ FIQ_STACK_START:
IRQ_STACK_START_IN:
.word 0x0badc0de
.globl _datarel_start
_datarel_start:
.word __datarel_start
.globl _datarel_start_ofs
_datarel_start_ofs:
.word __datarel_start - _start
.globl _datarelrolocal_start
_datarelrolocal_start:
.word __datarelrolocal_start
.globl _datarelrolocal_start_ofs
_datarelrolocal_start_ofs:
.word __datarelrolocal_start - _start
.globl _datarellocal_start
_datarellocal_start:
.word __datarellocal_start
.globl _datarellocal_start_ofs
_datarellocal_start_ofs:
.word __datarellocal_start - _start
.globl _datarelro_start
_datarelro_start:
.word __datarelro_start
.globl _datarelro_start_ofs
_datarelro_start_ofs:
.word __datarelro_start - _start
.globl _got_start
_got_start:
.word __got_start
.globl _got_start_ofs
_got_start_ofs:
.word __got_start - _start
.globl _got_end
_got_end:
.word __got_end
.globl _got_end_Ofs
_got_end_ofs:
.word __got_end - _start
/*
* the actual reset code
@ -198,9 +198,8 @@ stack_setup:
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
#ifndef CONFIG_PRELOADER
beq jump_2_ram
@ -213,33 +212,51 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
ldr r1, _TEXT_BASE
mov r0, r7 /* reloc addr */
ldr r2, _got_start /* addr in Flash */
ldr r3, _got_end /* addr in Flash */
sub r3, r3, r1
add r3, r3, r0
sub r2, r2, r1
add r2, r2, r0
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r4, [r2]
sub r4, r4, r1
add r4, r4, r0
str r4, [r2]
add r2, r2, #4
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
bne fixloop
blo fixloop
clear_bss:
ldr r0, _bss_start
ldr r1, _bss_end
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
sub r0, r0, r3
add r0, r0, r4
sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -255,18 +272,26 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
jump_2_ram:
ldr r0, _TEXT_BASE
ldr r2, _board_init_r
sub r2, r2, r0
add r2, r2, r7 /* position from board_init_r in RAM */
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
mov lr, r2
mov pc, lr
_board_init_r: .word board_init_r
_board_init_r_ofs:
.word board_init_r - _start
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code

7
arch/arm/cpu/armv7/u-boot.lds
View File

@ -53,6 +53,13 @@ SECTIONS
__datarelro_start = .;
*(.data.rel.ro)
}
. = ALIGN(4);
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
__dynsym_start = .;
.dynsym : { *(.dynsym) }
__got_start = .;
. = ALIGN(4);

257
arch/arm/cpu/pxa/cpu.c
View File

@ -30,10 +30,11 @@
* CPU specific code
*/
#include <common.h>
#include <command.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <asm/system.h>
#include <command.h>
#include <common.h>
#include <asm/arch/pxa-regs.h>
static void cache_flush(void);
@ -71,17 +72,249 @@ void set_GPIO_mode(int gpio_mode)
{
int gpio = gpio_mode & GPIO_MD_MASK_NR;
int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
int gafr;
int val;
/* This below changes direction setting of GPIO "gpio" */
val = readl(GPDR(gpio));
if (gpio_mode & GPIO_MD_MASK_DIR)
{
GPDR(gpio) |= GPIO_bit(gpio);
}
val |= GPIO_bit(gpio);
else
{
GPDR(gpio) &= ~GPIO_bit(gpio);
}
gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
val &= ~GPIO_bit(gpio);
writel(val, GPDR(gpio));
/* This below updates only AF of GPIO "gpio" */
val = readl(GAFR(gpio));
val &= ~(0x3 << (((gpio) & 0xf) * 2));
val |= fn << (((gpio) & 0xf) * 2);
writel(val, GAFR(gpio));
}
#endif /* CONFIG_CPU_MONAHANS */
void pxa_wait_ticks(int ticks)
{
writel(0, OSCR);
while (readl(OSCR) < ticks)
asm volatile("":::"memory");
}
inline void writelrb(uint32_t val, uint32_t addr)
{
writel(val, addr);
asm volatile("":::"memory");
readl(addr);
asm volatile("":::"memory");
}
void pxa_dram_init(void)
{
uint32_t tmp;
int i;
/*
* 1) Initialize Asynchronous static memory controller
*/
writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
/*
* 2) Initialize Card Interface
*/
/* MECR: Memory Expansion Card Register */
writelrb(CONFIG_SYS_MECR_VAL, MECR);
/* MCMEM0: Card Interface slot 0 timing */
writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
/* MCMEM1: Card Interface slot 1 timing */
writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
/*
* 3) Configure Fly-By DMA register
*/
writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
/*
* 4) Initialize Timing for Sync Memory (SDCLK0)
*/
/*
* Before accessing MDREFR we need a valid DRI field, so we set
* this to power on defaults + DRI field.
*/
/* Read current MDREFR config and zero out DRI */
tmp = readl(MDREFR) & ~0xfff;
/* Add user-specified DRI */
tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
/* Configure important bits */
tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
/* Write MDREFR back */
writelrb(tmp, MDREFR);
/*
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
*/
/* Initialize SXCNFG register. Assert the enable bits.
*
* Write SXMRS to cause an MRS command to all enabled banks of
* synchronous static memory. Note that SXLCR need not be written
* at this time.
*/
writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
/*
* 6) Initialize SDRAM
*/
writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
/*
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
* but not enable each SDRAM partition pair.
*/
writelrb(CONFIG_SYS_MDCNFG_VAL &
~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
pxa_wait_ticks(0x300);
/*
* 8) Trigger a number (usually 8) refresh cycles by attempting
* non-burst read or write accesses to disabled SDRAM, as commonly
* specified in the power up sequence documented in SDRAM data
* sheets. The address(es) used for this purpose must not be
* cacheable.
*/
for (i = 9; i >= 0; i--) {
writel(i, 0xa0000000);
asm volatile("":::"memory");
}
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
*/
tmp = CONFIG_SYS_MDCNFG_VAL &
(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
tmp |= readl(MDCNFG);
writelrb(tmp, MDCNFG);
/*
* 10) Write MDMRS.
*/
writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
/*
* 11) Enable APD
*/
if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
tmp = readl(MDREFR);
tmp |= MDREFR_APD;
writelrb(tmp, MDREFR);
}
}
void pxa_gpio_setup(void)
{
writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
#endif
writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
#endif
writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
#endif
writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
#endif
writel(CONFIG_SYS_PSSR_VAL, PSSR);
}
void pxa_interrupt_setup(void)
{
writel(0, ICLR);
writel(0, ICMR);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
writel(0, ICLR2);
writel(0, ICMR2);
#endif
}
void pxa_clock_setup(void)
{
#ifndef CONFIG_CPU_MONAHANS
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2));
#else
/* Set CKENA/CKENB/ACCR for MH */
#endif
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
while(!(readl(OSCC) & OSCC_OOK))
asm volatile("":::"memory");
}
void pxa_wakeup(void)
{
uint32_t rcsr;
rcsr = readl(RCSR);
writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
/* Wakeup */
if (rcsr & RCSR_SMR) {
writel(PSSR_PH, PSSR);
pxa_dram_init();
icache_disable();
dcache_disable();
asm volatile("mov pc, %0"::"r"(readl(PSSR)));
}
}
int arch_cpu_init(void)
{
pxa_gpio_setup();
// pxa_wait_ticks(0x8000);
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();
return 0;
}

69
arch/arm/cpu/pxa/i2c.c
View File

@ -33,6 +33,7 @@
/* FIXME: this file is PXA255 specific! What about other XScales? */
#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_HARD_I2C
@ -93,19 +94,21 @@ struct i2c_msg {
static void i2c_reset( void )
{
ICR &= ~ICR_IUE; /* disable unit */
ICR |= ICR_UR; /* reset the unit */
writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */
udelay(100);
ICR &= ~ICR_IUE; /* disable unit */
writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
#ifdef CONFIG_CPU_MONAHANS
CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
#else /* CONFIG_CPU_MONAHANS */
CKEN |= CKEN14_I2C; /* set the global I2C clock on */
/* set the global I2C clock on */
writel(readl(CKEN) | CKEN14_I2C, CKEN);
#endif
ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
ICR = I2C_ICR_INIT; /* set control register values */
ISR = I2C_ISR_INIT; /* set clear interrupt bits */
ICR |= ICR_IUE; /* enable unit */
writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
writel(I2C_ICR_INIT, ICR); /* set control reg values */
writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */
udelay(100);
}
@ -159,22 +162,26 @@ int i2c_transfer(struct i2c_msg *msg)
goto transfer_error_bus_busy;
/* start transmission */
ICR &= ~ICR_START;
ICR &= ~ICR_STOP;
IDBR = msg->data;
if (msg->condition == I2C_COND_START) ICR |= ICR_START;
if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
ICR &= ~ICR_ALDIE;
ICR |= ICR_TB;
writel(readl(ICR) & ~ICR_START, ICR);
writel(readl(ICR) & ~ICR_STOP, ICR);
writel(msg->data, IDBR);
if (msg->condition == I2C_COND_START)
writel(readl(ICR) | ICR_START, ICR);
if (msg->condition == I2C_COND_STOP)
writel(readl(ICR) | ICR_STOP, ICR);
if (msg->acknack == I2C_ACKNAK_SENDNAK)
writel(readl(ICR) | ICR_ACKNAK, ICR);
if (msg->acknack == I2C_ACKNAK_SENDACK)
writel(readl(ICR) & ~ICR_ACKNAK, ICR);
writel(readl(ICR) & ~ICR_ALDIE, ICR);
writel(readl(ICR) | ICR_TB, ICR);
/* transmit register empty? */
if (!i2c_isr_set_cleared(ISR_ITE,0))
goto transfer_error_transmit_timeout;
/* clear 'transmit empty' state */
ISR |= ISR_ITE;
writel(readl(ISR) | ISR_ITE, ISR);
/* wait for ACK from slave */
if (msg->acknack == I2C_ACKNAK_WAITACK)
@ -189,23 +196,27 @@ int i2c_transfer(struct i2c_msg *msg)
goto transfer_error_bus_busy;
/* start receive */
ICR &= ~ICR_START;
ICR &= ~ICR_STOP;
if (msg->condition == I2C_COND_START) ICR |= ICR_START;
if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
ICR &= ~ICR_ALDIE;
ICR |= ICR_TB;
writel(readl(ICR) & ~ICR_START, ICR);
writel(readl(ICR) & ~ICR_STOP, ICR);
if (msg->condition == I2C_COND_START)
writel(readl(ICR) | ICR_START, ICR);
if (msg->condition == I2C_COND_STOP)
writel(readl(ICR) | ICR_STOP, ICR);
if (msg->acknack == I2C_ACKNAK_SENDNAK)
writel(readl(ICR) | ICR_ACKNAK, ICR);
if (msg->acknack == I2C_ACKNAK_SENDACK)
writel(readl(ICR) & ~ICR_ACKNAK, ICR);
writel(readl(ICR) & ~ICR_ALDIE, ICR);
writel(readl(ICR) | ICR_TB, ICR);
/* receive register full? */
if (!i2c_isr_set_cleared(ISR_IRF,0))
goto transfer_error_receive_timeout;
msg->data = IDBR;
msg->data = readl(IDBR);
/* clear 'receive empty' state */
ISR |= ISR_IRF;
writel(readl(ISR) | ISR_IRF, ISR);
break;

365
arch/arm/cpu/pxa/pxafb.c
View File

@ -35,6 +35,7 @@
#include <stdio_dev.h>
#include <lcd.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
/* #define DEBUG */
@ -56,26 +57,26 @@
/* 640x480x16 @ 61 Hz */
vidinfo_t panel_info = {
vl_col: 640,
vl_row: 480,
vl_width: 640,
vl_height: 480,
vl_clkp: CONFIG_SYS_HIGH,
vl_oep: CONFIG_SYS_HIGH,
vl_hsp: CONFIG_SYS_HIGH,
vl_vsp: CONFIG_SYS_HIGH,
vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 0,
vl_clor: 0,
vl_tft: 1,
vl_hpw: 40,
vl_blw: 56,
vl_elw: 56,
vl_vpw: 20,
vl_bfw: 8,
vl_efw: 8,
.vl_col = 640,
.vl_row = 480,
.vl_width = 640,
.vl_height = 480,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 0,
.vl_clor = 0,
.vl_tft = 1,
.vl_hpw = 40,
.vl_blw = 56,
.vl_elw = 56,
.vl_vpw = 20,
.vl_bfw = 8,
.vl_efw = 8,
};
#endif /* CONFIG_PXA_VIDEO */
@ -90,26 +91,26 @@ vidinfo_t panel_info = {
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
vl_col: 640,
vl_row: 480,
vl_width: 157,
vl_height: 118,
vl_clkp: CONFIG_SYS_HIGH,
vl_oep: CONFIG_SYS_HIGH,
vl_hsp: CONFIG_SYS_HIGH,
vl_vsp: CONFIG_SYS_HIGH,
vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 1,
vl_clor: 1,
vl_tft: 0,
vl_hpw: 1,
vl_blw: 3,
vl_elw: 3,
vl_vpw: 1,
vl_bfw: 0,
vl_efw: 0,
.vl_col = 640,
.vl_row = 480,
.vl_width = 157,
.vl_height = 118,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 0,
.vl_hpw = 1,
.vl_blw = 3,
.vl_elw = 3,
.vl_vpw = 1,
.vl_bfw = 0,
.vl_efw = 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
/*----------------------------------------------------------------------*/
@ -123,26 +124,26 @@ vidinfo_t panel_info = {
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
vl_col: 640,
vl_row: 480,
vl_width: 157,
vl_height: 118,
vl_clkp: CONFIG_SYS_HIGH,
vl_oep: CONFIG_SYS_HIGH,
vl_hsp: CONFIG_SYS_HIGH,
vl_vsp: CONFIG_SYS_HIGH,
vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 1,
vl_clor: 1,
vl_tft: 1,
vl_hpw: 32,
vl_blw: 144,
vl_elw: 32,
vl_vpw: 2,
vl_bfw: 13,
vl_efw: 30,
.vl_col = 640,
.vl_row = 480,
.vl_width = 157,
.vl_height = 118,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 32,
.vl_blw = 144,
.vl_elw = 32,
.vl_vpw = 2,
.vl_bfw = 13,
.vl_efw = 30,
};
#endif /* CONFIG_VOIPAC_LCD */
@ -156,26 +157,26 @@ vidinfo_t panel_info = {
#define REG_LCCR3 0x0340FF20
vidinfo_t panel_info = {
vl_col: 320,
vl_row: 240,
vl_width: 167,
vl_height: 109,
vl_clkp: CONFIG_SYS_HIGH,
vl_oep: CONFIG_SYS_HIGH,
vl_hsp: CONFIG_SYS_HIGH,
vl_vsp: CONFIG_SYS_HIGH,
vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 1,
vl_splt: 0,
vl_clor: 1,
vl_tft: 0,
vl_hpw: 1,
vl_blw: 1,
vl_elw: 1,
vl_vpw: 7,
vl_bfw: 0,
vl_efw: 0,
.vl_col = 320,
.vl_row = 240,
.vl_width = 167,
.vl_height = 109,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 1,
.vl_splt = 0,
.vl_clor = 1,
.vl_tft = 0,
.vl_hpw = 1,
.vl_blw = 1,
.vl_elw = 1,
.vl_vpw = 7,
.vl_bfw = 0,
.vl_efw = 0,
};
#endif /* CONFIG_HITACHI_SX14 */
@ -190,31 +191,132 @@ vidinfo_t panel_info = {
# define REG_LCCR3 0x03b00009
vidinfo_t panel_info = {
vl_col: 240,
vl_row: 320,
vl_width: 240,
vl_height: 320,
vl_clkp: CONFIG_SYS_HIGH,
vl_oep: CONFIG_SYS_LOW,
vl_hsp: CONFIG_SYS_LOW,
vl_vsp: CONFIG_SYS_LOW,
vl_dp: CONFIG_SYS_HIGH,
vl_bpix: LCD_BPP,
vl_lbw: 0,
vl_splt: 1,
vl_clor: 1,
vl_tft: 1,
vl_hpw: 4,
vl_blw: 4,
vl_elw: 8,
vl_vpw: 4,
vl_bfw: 4,
vl_efw: 8,
.vl_col = 240,
.vl_row = 320,
.vl_width = 240,
.vl_height = 320,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 4,
.vl_blw = 4,
.vl_elw = 8,
.vl_vpw = 4,
.vl_bfw = 4,
.vl_efw = 8,
};
#endif /* CONFIG_LMS283GF05 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_ACX517AKN
# define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f9
# define REG_LCCR3 0x03700006
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 320,
.vl_width = 320,
.vl_height = 320,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 0x04,
.vl_blw = 0x1c,
.vl_elw = 0x08,
.vl_vpw = 0x01,
.vl_bfw = 0x07,
.vl_efw = 0x08,
};
#endif /* CONFIG_ACX517AKN */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LQ038J7DH53
# define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f9
# define REG_LCCR3 0x03700004
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 480,
.vl_width = 320,
.vl_height = 480,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 0x04,
.vl_blw = 0x20,
.vl_elw = 0x01,
.vl_vpw = 0x01,
.vl_bfw = 0x04,
.vl_efw = 0x01,
};
#endif /* CONFIG_ACX517AKN */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LITTLETON_LCD
# define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f8
# define REG_LCCR3 0x0300FF04
vidinfo_t panel_info = {
.vl_col = 480,
.vl_row = 640,
.vl_width = 480,
.vl_height = 640,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_HIGH,
.vl_hsp = CONFIG_SYS_HIGH,
.vl_vsp = CONFIG_SYS_HIGH,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 0,
.vl_clor = 0,
.vl_tft = 1,
.vl_hpw = 9,
.vl_blw = 8,
.vl_elw = 24,
.vl_vpw = 2,
.vl_bfw = 2,
.vl_efw = 4,
};
#endif /* CONFIG_LITTLETON_LCD */
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
#endif
@ -377,12 +479,14 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug("Setting GPIO for 4 bit data\n");
/* bits 58-61 */
GPDR1 |= (0xf << 26);
GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
writel(readl(GPDR1) | (0xf << 26), GPDR1);
writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
GAFR1_U);
/* bits 74-77 */
GPDR2 |= (0xf << 10);
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
writel(readl(GPDR2) | (0xf << 10), GPDR2);
writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
GAFR2_L);
}
/* 8 bit interface */
@ -391,15 +495,17 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug("Setting GPIO for 8 bit data\n");
/* bits 58-65 */
GPDR1 |= (0x3f << 26);
GPDR2 |= (0x3);
writel(readl(GPDR1) | (0x3f << 26), GPDR1);
writel(readl(GPDR2) | (0x3), GPDR2);
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
GAFR1_U);
writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
/* bits 74-77 */
GPDR2 |= (0xf << 10);
GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
writel(readl(GPDR2) | (0xf << 10), GPDR2);
writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
GAFR2_L);
}
/* 16 bit interface */
@ -407,11 +513,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug("Setting GPIO for 16 bit data\n");
/* bits 58-77 */
GPDR1 |= (0x3f << 26);
GPDR2 |= 0x00003fff;
writel(readl(GPDR1) | (0x3f << 26), GPDR1);
writel(readl(GPDR2) | 0x00003fff, GPDR2);
GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
GAFR1_U);
writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
}
else
{
@ -425,26 +532,26 @@ static void pxafb_enable_controller (vidinfo_t *vid)
debug("Enabling LCD controller\n");
/* Sequence from 11.7.10 */
LCCR3 = vid->pxa.reg_lccr3;
LCCR2 = vid->pxa.reg_lccr2;
LCCR1 = vid->pxa.reg_lccr1;
LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
FDADR0 = vid->pxa.fdadr0;
FDADR1 = vid->pxa.fdadr1;
LCCR0 |= LCCR0_ENB;
writel(vid->pxa.reg_lccr3, LCCR3);
writel(vid->pxa.reg_lccr2, LCCR2);
writel(vid->pxa.reg_lccr1, LCCR1);
writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
writel(vid->pxa.fdadr0, FDADR0);
writel(vid->pxa.fdadr1, FDADR1);
writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_1_LCD;
writel(readl(CKENA) | CKENA_1_LCD, CKENA);
#else
CKEN |= CKEN16_LCD;
writel(readl(CKEN) | CKEN16_LCD, CKEN);
#endif
debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
debug("FDADR0 = 0x%08x\n", readl(FDADR0));
debug("FDADR1 = 0x%08x\n", readl(FDADR1));
debug("LCCR0 = 0x%08x\n", readl(LCCR0));
debug("LCCR1 = 0x%08x\n", readl(LCCR1));
debug("LCCR2 = 0x%08x\n", readl(LCCR2));
debug("LCCR3 = 0x%08x\n", readl(LCCR3));
}
static int pxafb_init (vidinfo_t *vid)

344
arch/arm/cpu/pxa/start.S
View File

@ -31,6 +31,14 @@
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/macro.h>
/* takes care the CP15 update has taken place */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
.globl _start
_start: b reset
@ -86,11 +94,9 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
@ -115,7 +121,7 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif /* CONFIG_USE_IRQ */
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
#ifndef CONFIG_PRELOADER
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -159,12 +165,84 @@ reset:
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
* Enable MMU to use DCache as DRAM
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
/* Domain access -- enable for all CPs */
ldr r0, =0x0000ffff
mcr p15, 0, r0, c3, c0, 0
/* Point TTBR to MMU table */
ldr r0, =mmu_table
adr r2, _start
orr r0, r2
mcr p15, 0, r0, c2, c0, 0
/* !!! Hereby, check if the code is running from SRAM !!! */
/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
* is linked to 0x0 too, so this makes things easier. */
cmp r2, #0x5c000000
ldreq r1, [r0]
orreq r1, r2
streq r1, [r0]
/* Kick in MMU, ICache, DCache, BTB */
mrc p15, 0, r0, c1, c0, 0
bic r0, #0x1b00
bic r0, #0x0087
orr r0, #0x1800
orr r0, #0x0005
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
/* Unlock Icache, Dcache */
mcr p15, 0, r0, c9, c1, 1
mcr p15, 0, r0, c9, c2, 1
/* Flush Icache, Dcache, BTB */
mcr p15, 0, r0, c7, c7, 0
/* Unlock I-TLB, D-TLB */
mcr p15, 0, r0, c10, c4, 1
mcr p15, 0, r0, c10, c8, 1
/* Flush TLB */
mcr p15, 0, r0, c8, c7, 0
/* Allocate 4096 bytes of Dcache as RAM */
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r4, #0x00
mov r5, #0x00
mov r2, #0x01
mcr p15, 0, r0, c9, c2, 0
CPWAIT r0
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
mov r0, #128
mov r1, #0xa0000000
alloc:
mcr p15, 0, r1, c7, c2, 5
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
subs r0, #0x01
bne alloc
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r2, #0x00
mcr p15, 0, r2, c9, c2, 0
CPWAIT r0
/* Jump to 0x0 ( + offset) if running from SRAM */
adr r0, zerojmp
bic r0, #0x5c000000
mov pc, r0
zerojmp:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
@ -201,11 +279,13 @@ stack_setup:
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
stmfd sp!, {r0-r12}
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
stmia r6!, {r3-r5, r7-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
ldmfd sp!, {r0-r12}
#ifndef CONFIG_PRELOADER
/* fix got entries */
@ -274,218 +354,28 @@ _board_init_r: .word board_init_r
/****************************************************************************/
/* */
/* the actual reset code */
/* the actual reset code for OneNAND IPL */
/* */
/****************************************************************************/
#ifndef CONFIG_PXA27X
#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
#endif
reset:
mrs r0,cpsr /* set the CPU to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
/* Set CPU to SVC32 mode */
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from RAM!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit /* we do sys-critical inits */
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Point stack at the end of SRAM and leave 32 words for abort-stack */
ldr sp, =0x5c03ff80
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
#ifndef CONFIG_PRELOADER
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
#endif
/* Start OneNAND IPL */
ldr pc, =start_oneboot
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
#ifdef CONFIG_PRELOADER
sub sp, r0, #128 /* leave 32 words for abort-stack */
#else
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif /* CONFIG_USE_IRQ */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#endif
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
#endif
ldr pc, _start_armboot
#ifdef CONFIG_ONENAND_IPL
_start_armboot: .word start_oneboot
#else
_start_armboot: .word start_armboot
#endif
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/****************************************************************************/
/* */
/* CPU_init_critical registers */
/* */
/* - setup important registers */
/* - setup memory timing */
/* */
/****************************************************************************/
/* mk@tbd: Fix this! */
#undef RCSR
#undef ICMR
#undef OSMR3
#undef OSCR
#undef OWER
#undef OIER
#undef CCCR
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000
#define ICMR 0x04
/* Reset-Controller */
RST_BASE: .word 0x40f00030
#define RCSR 0x00
/* Operating System Timer */
OSTIMER_BASE: .word 0x40a00000
#define OSMR3 0x0C
#define OSCR 0x10
#define OWER 0x18
#define OIER 0x1C
/* Clock Manager Registers */
#ifdef CONFIG_CPU_MONAHANS
# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
# error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
# define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
#else /* !CONFIG_CPU_MONAHANS */
#ifdef CONFIG_SYS_CPUSPEED
CC_BASE: .word 0x41300000
#define CCCR 0x00
cpuspeed: .word CONFIG_SYS_CPUSPEED
#else /* !CONFIG_SYS_CPUSPEED */
#error "You have to define CONFIG_SYS_CPUSPEED!!"
#endif /* CONFIG_SYS_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/* takes care the CP15 update has taken place */
.macro CPWAIT reg
mrc p15,0,\reg,c2,c0,0
mov \reg,\reg
sub pc,pc,#4
.endm
cpu_init_crit:
/* mask all IRQs */
#ifndef CONFIG_CPU_MONAHANS
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
#else /* CONFIG_CPU_MONAHANS */
/* Step 1 - Enable CP6 permission */
mrc p15, 0, r1, c15, c1, 0 @ read CPAR
orr r1, r1, #0x40
mcr p15, 0, r1, c15, c1, 0
CPWAIT r1
/* Step 2 - Mask ICMR & ICMR2 */
mov r1, #0
mcr p6, 0, r1, c1, c0, 0 @ ICMR
mcr p6, 0, r1, c7, c0, 0 @ ICMR2
/* turn off all clocks but the ones we will definitly require */
ldr r1, =CKENA
ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
str r2, [r1]
ldr r1, =CKENB
ldr r2, =(CKENB_6_IRQ)
str r2, [r1]
#endif /* !CONFIG_CPU_MONAHANS */
/* set clock speed */
#ifdef CONFIG_CPU_MONAHANS
ldr r0, =ACCR
ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
str r1, [r0]
#else /* !CONFIG_CPU_MONAHANS */
#ifdef CONFIG_SYS_CPUSPEED
ldr r0, CC_BASE
ldr r1, cpuspeed
str r1, [r0, #CCCR]
mov r0, #2
mcr p14, 0, r0, c6, c0, 0
setspeed_done:
#endif /* CONFIG_SYS_CPUSPEED */
#endif /* CONFIG_CPU_MONAHANS */
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
bl lowlevel_init
mov lr, ip
/* Memory interfaces are working. Disable MMU and enable I-cache. */
/* mk: hmm, this is not in the monahans docs, leave it now but
* check here if it doesn't work :-) */
ldr r0, =0x2001 /* enable access to all coproc. */
mcr p15, 0, r0, c15, c1, 0
CPWAIT r0
mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
CPWAIT r0
mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
CPWAIT r0
mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
CPWAIT r0
/* Enable the Icache */
/*
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x1800
mcr p15, 0, r0, c1, c0, 0
CPWAIT
*/
mov pc, lr
#endif /* #if !defined(CONFIG_ONENAND_IPL) */
#ifndef CONFIG_PRELOADER
/****************************************************************************/
@ -676,6 +566,12 @@ fiq:
/* perform a watchdog timeout for a soft reset. */
/* */
/****************************************************************************/
/* Operating System Timer */
OSTIMER_BASE: .word 0x40a00000
#define OSMR3 0x0C
#define OSCR 0x10
#define OWER 0x18
#define OIER 0x1C
.align 5
.globl reset_cpu
@ -703,3 +599,25 @@ reset_cpu:
reset_endless:
b reset_endless
#ifndef CONFIG_PRELOADER
.section .mmudata, "a"
.align 14
.globl mmu_table
mmu_table:
/* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
.set __base, 0
.rept 0xa00
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
/* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
.word (0xa00 << 20) | 0x1c1e
.set __base, 0xa01
.rept 0x1000 - 0xa01
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
#endif

7
arch/arm/cpu/pxa/timer.c
View File

@ -26,8 +26,9 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <common.h>
#include <div64.h>
#ifdef CONFIG_USE_IRQ
@ -86,7 +87,7 @@ void __udelay (unsigned long usec)
void reset_timer_masked (void)
{
OSCR = 0;
writel(0, OSCR);
}
ulong get_timer_masked (void)
@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec)
*/
unsigned long long get_ticks(void)
{
return OSCR;
return readl(OSCR);
}
/*

63
arch/arm/cpu/pxa/usb.c
View File

@ -27,85 +27,78 @@
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <usb.h>
int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC);
writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
#if defined(CONFIG_PXA27X)
/* Enable USB host clock. */
CKEN |= CKEN10_USBHOST;
writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
#if defined(CONFIG_CPU_MONAHANS)
/* Configure Port 2 for Host (USB Client Registers) */
UP2OCR = 0x3000c;
writel(0x3000c, UP2OCR);
#endif
UHCHR |= UHCHR_FHR;
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
wait_ms(11);
UHCHR &= ~UHCHR_FHR;
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
UHCHR |= UHCHR_FSBIR;
while (UHCHR & UHCHR_FSBIR)
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (readl(UHCHR) & UHCHR_FSBIR)
udelay(1);
#if defined(CONFIG_CPU_MONAHANS)
UHCHR &= ~UHCHR_SSEP0;
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
UHCHR &= ~UHCHR_SSEP2;
writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
UHCHR &= ~UHCHR_SSEP1;
UHCHR &= ~UHCHR_SSE;
writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
return 0;
}
int usb_cpu_stop(void)
{
UHCHR |= UHCHR_FHR;
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
UHCHR &= ~UHCHR_FHR;
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
UHCCOMS |= 1;
writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
udelay(10);
#if defined(CONFIG_CPU_MONAHANS)
UHCHR |= UHCHR_SSEP0;
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
UHCHR |= UHCHR_SSEP2;
writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
#if defined(CONFIG_CPU_MONAHANS)
/* Disable USB host clock. */
writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
udelay(100);
#endif
#if defined(CONFIG_PXA27X)
/* Disable USB host clock. */
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
UHCHR |= UHCHR_SSEP1;
UHCHR |= UHCHR_SSE;
return 0;
}
int usb_cpu_init_fail(void)
{
UHCHR |= UHCHR_FHR;
udelay(11);
UHCHR &= ~UHCHR_FHR;
UHCCOMS |= 1;
udelay(10);
#if defined(CONFIG_CPU_MONAHANS)
UHCHR |= UHCHR_SSEP0;
#endif
#if defined(CONFIG_PXA27X)
UHCHR |= UHCHR_SSEP2;
#endif
UHCHR |= UHCHR_SSEP1;
UHCHR |= UHCHR_SSE;
return 0;
return usb_cpu_stop();
}
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */

1
arch/arm/include/asm/arch-at91/hardware.h
View File

@ -18,6 +18,7 @@
#if defined(CONFIG_AT91RM9200)
#include <asm/arch-at91/at91rm9200.h>
#define AT91_PMC_UHP AT91RM9200_PMC_UHP
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#include <asm/arch/at91sam9260.h>
#define AT91_BASE_MCI AT91SAM9260_BASE_MCI

1
arch/arm/include/asm/arch-mx31/mx31.h
View File

@ -27,6 +27,7 @@
extern u32 mx31_get_ipg_clk(void);
#define imx_get_uartclk mx31_get_ipg_clk
extern void mx31_gpio_mux(unsigned long mode);
extern void mx31_set_pad(enum iomux_pins pin, u32 config);
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);

0
arch/arm/include/asm/arch-mx51/asm-offsets.h → arch/arm/include/asm/arch-mx5/asm-offsets.h
View File

0
arch/arm/include/asm/arch-mx51/clock.h → arch/arm/include/asm/arch-mx5/clock.h
View File

0
arch/arm/include/asm/arch-mx51/crm_regs.h → arch/arm/include/asm/arch-mx5/crm_regs.h
View File

0
arch/arm/include/asm/arch-mx51/imx-regs.h → arch/arm/include/asm/arch-mx5/imx-regs.h
View File

8
arch/arm/include/asm/arch-mx51/iomux.h → arch/arm/include/asm/arch-mx5/iomux.h
View File

@ -20,13 +20,13 @@
* MA 02111-1307 USA
*/
#ifndef __MACH_MX51_IOMUX_H__
#define __MACH_MX51_IOMUX_H__
#ifndef __MACH_MX5_IOMUX_H__
#define __MACH_MX5_IOMUX_H__
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx51_pins.h>
#include <asm/arch/mx5x_pins.h>
typedef unsigned int iomux_pin_name_t;
@ -190,4 +190,4 @@ void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
#endif /* __MACH_MX51_IOMUX_H__ */
#endif /* __MACH_MX5_IOMUX_H__ */

6
arch/arm/include/asm/arch-mx51/mx51_pins.h → arch/arm/include/asm/arch-mx5/mx5x_pins.h
View File

@ -20,8 +20,8 @@
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
#define __ASM_ARCH_MXC_MX51_PINS_H__
#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
#define __ASM_ARCH_MX5_MX5X_PINS_H__
#ifndef __ASSEMBLY__
@ -415,4 +415,4 @@ enum iomux_pins {
};
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */

0
arch/arm/include/asm/arch-mx51/sys_proto.h → arch/arm/include/asm/arch-mx5/sys_proto.h
View File

61
arch/arm/include/asm/arch-pxa/hardware.h
View File

@ -21,6 +21,19 @@
#include <linux/config.h>
#include <asm/mach-types.h>
/*
* Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
* PXA300/310/320 all have distinct register mappings in some cases, that's why
* the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
* drivers and compatibility glue with old source then.
*/
#ifndef CONFIG_CPU_MONAHANS
#if defined(CONFIG_CPU_PXA300) || \
defined(CONFIG_CPU_PXA310) || \
defined(CONFIG_CPU_PXA320)
#define CONFIG_CPU_MONAHANS
#endif
#endif
/*
* These are statically mapped PCMCIA IO space for designs using it as a
@ -51,54 +64,6 @@
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
/* FIXME: Only this does work for u-boot... find out why... [RS] */
#define UBOOT_REG_FIX 1
#ifndef UBOOT_REG_FIX
#ifndef __ASSEMBLY__
#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
/*
* This __REG() version gives the same results as the one above, except
* that we are fooling gcc somehow so it generates far better and smaller
* assembly code for access to contigous registers. It's a shame that gcc
* doesn't guess this by itself.
*/
#include <asm/types.h>
typedef struct { volatile u32 offset[4096]; } __regbase;
# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
# define __REG(x) __REGP(io_p2v(x))
#endif
/* Let's kick gcc's ass again... */
# define __REG2(x,y) \
( __builtin_constant_p(y) ? (__REG((x) + (y))) \
: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
# define __PREG(x) (io_v2p((u32)&(x)))
#else
# define __REG(x) io_p2v(x)
# define __PREG(x) io_v2p(x)
# undef io_p2v
# undef __REG
# ifndef __ASSEMBLY__
# define io_p2v(PhAdd) (PhAdd)
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
# define __REG(x) (x)
# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
# define __REG_2(x) (x)
# define __REG_3(x) (x)
# endif
# endif
#endif /* UBOOT_REG_FIX */
#include "pxa-regs.h"
#ifndef __ASSEMBLY__

20
arch/arm/include/asm/arch-pxa/macro.h
View File

@ -102,7 +102,11 @@
/*
* This macro sets up the Memory controller of the PXA2xx CPU
*
* Clobbered regs: r3, r4, r5
* WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
* and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
* use this regs for other purpose inside this macro.
*
* Clobbered regs: r3, r4, r5, r6, r7
*/
.macro pxa_mem_setup
/* This comes handy when setting MDREFR */
@ -157,7 +161,7 @@
bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
ldr r4, =CONFIG_SYS_MDREFR_VAL
mov r6, r4
mov r7, r4
lsl r4, #20
lsr r4, #20 /* Get a valid DRI field */
@ -187,12 +191,12 @@
* 6) Initialize SDRAM
*/
bic r6, #MDREFR_SLFRSH
str r6, [r3, #MDREFR_OFFSET]
bic r7, #MDREFR_SLFRSH
str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
orr r6, #MDREFR_E1PIN
str r6, [r3, #MDREFR_OFFSET]
orr r7, #MDREFR_E1PIN
str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
/*
@ -250,8 +254,8 @@
*/
ldr r4, [r3, #MDREFR_OFFSET]
and r6, r6, #MDREFR_APD
orr r4, r4, r6
and r7, r7, #MDREFR_APD
orr r4, r4, r7
str r4, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
.endm

2614
arch/arm/include/asm/arch-pxa/pxa-regs.h
View File

File diff suppressed because it is too large Load Diff

3
arch/arm/include/asm/config.h
View File

@ -21,10 +21,9 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* Relocation to SDRAM works on all ARM boards */
#define CONFIG_RELOC_FIXUP_WORKS
#endif
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

14
arch/arm/include/asm/global_data.h
View File

@ -47,6 +47,20 @@ typedef struct global_data {
#ifdef CONFIG_FSL_ESDHC
unsigned long sdhc_clk;
#endif
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
unsigned long main_clk_rate_hz;
unsigned long mck_rate_hz;
unsigned long plla_rate_hz;
unsigned long pllb_rate_hz;
unsigned long at91_pllb_usb_init;
/* "static data" needed by at91's timer.c */
unsigned long timer_rate_hz;
unsigned long tbl;
unsigned long tbu;
unsigned long long timer_reset_value;
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */

14
arch/arm/include/asm/u-boot-arm.h
View File

@ -30,18 +30,18 @@
#define _U_BOOT_ARM_H_ 1
/* for the following variables, see start.S */
extern ulong _bss_start; /* code + data end == BSS start */
extern ulong _bss_end; /* BSS end */
extern ulong _bss_start_ofs; /* BSS start relative to _start */
extern ulong _bss_end_ofs; /* BSS end relative to _start */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
extern ulong _armboot_start; /* code start */
extern ulong _armboot_start_ofs; /* code start */
#else
extern ulong _TEXT_BASE; /* code start */
extern ulong _datarel_start;
extern ulong _datarelrolocal_start;
extern ulong _datarellocal_start;
extern ulong _datarelro_start;
extern ulong _datarel_start_ofs;
extern ulong _datarelrolocal_start_ofs;
extern ulong _datarellocal_start_ofs;
extern ulong _datarelro_start_ofs;
extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
#endif

8
arch/arm/lib/board.c
View File

@ -147,7 +147,7 @@ static int display_banner (void)
#else
_armboot_start,
#endif
_bss_start, _bss_end);
_bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
#ifdef CONFIG_MODEM_SUPPORT
debug ("Modem Support enabled\n");
#endif
@ -508,7 +508,7 @@ void board_init_f (ulong bootflag)
memset ((void*)gd, 0, sizeof (gd_t));
gd->mon_len = _bss_end - _TEXT_BASE;
gd->mon_len = _bss_end_ofs;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
@ -670,6 +670,7 @@ static char *failed = "*** failed ***\n";
*
************************************************************************
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
char *s;
@ -693,7 +694,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
monitor_flash_len = _bss_start - _TEXT_BASE;
monitor_flash_len = _bss_start_ofs;
debug ("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
@ -895,6 +896,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
/* NOTREACHED - no way out of command loop except booting */
}
#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
void hang (void)

2
arch/arm/lib/cache.c
View File

@ -38,7 +38,7 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2)
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
#endif
#ifdef CONFIG_ARMCORTEXA8
#ifdef CONFIG_ARMV7
void v7_flush_cache_all(void);
v7_flush_cache_all();

1
arch/avr32/lib/board.c
View File

@ -257,7 +257,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
extern char * env_name_spec;
#endif
char *s;
cmd_tbl_t *cmdtp;
bd_t *bd;
gd = new_gd;

1
arch/m68k/lib/board.c
View File

@ -393,7 +393,6 @@ board_init_f (ulong bootflag)
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
cmd_tbl_t *cmdtp;
char *s;
bd_t *bd;
extern void malloc_bin_reloc (void);

1
arch/mips/lib/board.c
View File

@ -276,7 +276,6 @@ void board_init_f(ulong bootflag)
void board_init_r (gd_t *id, ulong dest_addr)
{
cmd_tbl_t *cmdtp;
#ifndef CONFIG_SYS_NO_FLASH
ulong size;
#endif

4
arch/powerpc/cpu/mpc85xx/config.mk
View File

@ -25,6 +25,10 @@ PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
# Enable gc-sections to enable generation of smaller images.
PLATFORM_LDFLAGS += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
# see "[PATCH,rs6000] make -mno-spe work as expected" on
# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html

219
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -34,6 +34,9 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@ -282,3 +285,219 @@ void mpc85xx_reginfo(void)
print_laws();
print_lbc_regs();
}
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num);
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn);
unsigned int
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
static void dump_spd_ddr_reg(void)
{
int i, j, k, m;
u8 *p_8;
u32 *p_32;
ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
generic_spd_eeprom_t
spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
fsl_ddr_get_spd(spd[i], i);
puts("SPD data of all dimms (zero vaule is omitted)...\n");
puts("Byte (hex) ");
k = 1;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
printf("Dimm%d ", k++);
}
puts("\n");
for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
m = 0;
printf("%3d (0x%02x) ", k, k);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
p_8 = (u8 *) &spd[i][j];
if (p_8[k]) {
printf("0x%02x ", p_8[k]);
m++;
} else
puts(" ");
}
}
if (m)
puts("\n");
else
puts("\r");
}
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
break;
#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
case 1:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
break;
#endif
default:
printf("%s unexpected controller number = %u\n",
__func__, i);
return;
}
}
printf("DDR registers dump for all controllers "
"(zero vaule is omitted)...\n");
puts("Offset (hex) ");
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
puts("\n");
for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
m = 0;
printf("%6d (0x%04x)", k * 4, k * 4);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
p_32 = (u32 *) ddr[i];
if (p_32[k]) {
printf(" 0x%08x", p_32[k]);
m++;
} else
puts(" ");
}
if (m)
puts("\n");
else
puts("\r");
}
puts("\n");
}
/* invalid the TLBs for DDR and setup new ones to cover p_addr */
static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
{
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
phys_addr_t rpn = 0;
int ddr_esel;
ptr = vstart;
while (ptr < (vstart + size)) {
ddr_esel = find_tlb_idx((void *)ptr, 1);
if (ddr_esel != -1) {
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
disable_tlb(ddr_esel);
}
ptr += TSIZE_TO_BYTES(tsize);
}
/* Setup new tlb to cover the physical address */
setup_ddr_tlbs_phys(p_addr, size>>20);
ptr = vstart;
ddr_esel = find_tlb_idx((void *)ptr, 1);
if (ddr_esel != -1) {
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
} else {
printf("TLB error in function %s\n", __func__);
return -1;
}
return 0;
}
/*
* slide the testing window up to test another area
* for 32_bit system, the maximum testable memory is limited to
* CONFIG_MAX_MEM_MAPPED
*/
int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
phys_addr_t test_cap, p_addr;
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
#if !defined(CONFIG_PHYS_64BIT) || \
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
test_cap = p_size;
#else
test_cap = gd->ram_size;
#endif
p_addr = (*vstart) + (*size) + (*phys_offset);
if (p_addr < test_cap - 1) {
p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
if (reset_tlb(p_addr, p_size, phys_offset) == -1)
return -1;
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
*size = (u32) p_size;
printf("Testing 0x%08llx - 0x%08llx\n",
(u64)(*vstart) + (*phys_offset),
(u64)(*vstart) + (*phys_offset) + (*size) - 1);
} else
return 1;
return 0;
}
/* initialization for testing area */
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
*size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
*phys_offset = 0;
#if !defined(CONFIG_PHYS_64BIT) || \
!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
puts("Cannot test more than ");
print_size(CONFIG_MAX_MEM_MAPPED,
" without proper 36BIT support.\n");
}
#endif
printf("Testing 0x%08llx - 0x%08llx\n",
(u64)(*vstart) + (*phys_offset),
(u64)(*vstart) + (*phys_offset) + (*size) - 1);
return 0;
}
/* invalid TLBs for DDR and remap as normal after testing */
int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
unsigned long epn;
u32 tsize, valid, ptr;
phys_addr_t rpn = 0;
int ddr_esel;
/* disable the TLBs for this testing */
ptr = *vstart;
while (ptr < (*vstart) + (*size)) {
ddr_esel = find_tlb_idx((void *)ptr, 1);
if (ddr_esel != -1) {
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
disable_tlb(ddr_esel);
}
ptr += TSIZE_TO_BYTES(tsize);
}
puts("Remap DDR ");
setup_ddr_tlbs(gd->ram_size>>20);
puts("\n");
return 0;
}
void arch_memory_failure_handle(void)
{
dump_spd_ddr_reg();
}
#endif

22
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -48,6 +48,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
ulong spin_tbl_addr = get_spin_phys_addr();
u32 bootpg = determine_mp_bootpg();
u32 id = get_my_id();
const char *enable_method;
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
@ -63,10 +64,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
fdt_setprop_string(blob, off, "status",
"disabled");
}
if (hold_cores_in_reset(0)) {
#ifdef CONFIG_FSL_CORENET
/* Cores held in reset, use BRR to release */
enable_method = "fsl,brr-holdoff";
#else
/* Cores held in reset, use EEBPCR to release */
enable_method = "fsl,eebpcr-holdoff";
#endif
} else {
/* Cores out of reset and in a spin-loop */
enable_method = "spin-table";
fdt_setprop(blob, off, "cpu-release-addr",
&val, sizeof(val));
}
fdt_setprop_string(blob, off, "enable-method",
"spin-table");
fdt_setprop(blob, off, "cpu-release-addr",
&val, sizeof(val));
enable_method);
} else {
printf ("cpu NULL\n");
}

31
arch/powerpc/cpu/mpc85xx/mp.c
View File

@ -36,6 +36,27 @@ u32 get_my_id()
return mfspr(SPRN_PIR);
}
/*
* Determine if U-Boot should keep secondary cores in reset, or let them out
* of reset and hold them in a spinloop
*/
int hold_cores_in_reset(int verbose)
{
const char *s = getenv("mp_holdoff");
/* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
if (verbose) {
puts("Secondary cores are being held in reset.\n");
puts("See 'mp_holdoff' environment variable\n");
}
return 1;
}
return 0;
}
int cpu_reset(int nr)
{
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
@ -51,6 +72,9 @@ int cpu_status(int nr)
{
u32 *table, id = get_my_id();
if (hold_cores_in_reset(1))
return 0;
if (nr == id) {
table = (u32 *)get_spin_virt_addr();
printf("table base @ 0x%p\n", table);
@ -133,6 +157,9 @@ int cpu_release(int nr, int argc, char * const argv[])
u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
if (hold_cores_in_reset(1))
return 0;
if (nr == get_my_id()) {
printf("Invalid to release the boot core.\n\n");
return 1;
@ -353,6 +380,10 @@ void setup_mp(void)
ulong fixup = (ulong)&__secondary_start_page;
u32 bootpg = determine_mp_bootpg();
/* Some OSes expect secondary cores to be held in reset */
if (hold_cores_in_reset(0))
return;
/* Store the bootpg's SDRAM address for use by secondary CPU cores */
__bootpg_addr = bootpg;

1
arch/powerpc/cpu/mpc85xx/mp.h
View File

@ -6,6 +6,7 @@
ulong get_spin_phys_addr(void);
ulong get_spin_virt_addr(void);
u32 get_my_id(void);
int hold_cores_in_reset(int verbose);
#define BOOT_ENTRY_ADDR_UPPER 0
#define BOOT_ENTRY_ADDR_LOWER 1

16
arch/powerpc/cpu/mpc85xx/tlb.c
View File

@ -245,7 +245,8 @@ void init_addr_map(void)
}
#endif
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
unsigned int
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
int i;
unsigned int tlb_size;
@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
tlb_size = (camsize - 10) / 2;
set_tlb(1, ram_tlb_address, ram_tlb_address,
set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
memsize -= 1ULL << camsize;
ram_tlb_address += 1UL << camsize;
p_addr += 1UL << camsize;
}
if (memsize)
print_size(memsize, " left unmapped\n");
/*
* Confirm that the requested amount of memory was mapped.
*/
return memsize_in_meg;
}
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
return
setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
#endif /* !CONFIG_NAND_SPL */

52
arch/powerpc/cpu/mpc85xx/u-boot.lds
View File

@ -25,8 +25,7 @@
#endif
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
@ -38,42 +37,16 @@ SECTIONS
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
*(.text)
*(.got1)
*(.text*)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@ -81,23 +54,19 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
*(.got)
KEEP(*(.got))
_GOT2_TABLE_ = .;
*(.got2)
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
*(.fixup)
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
@ -126,7 +95,7 @@ SECTIONS
.resetvec RESET_VECTOR_ADDRESS :
{
*(.resetvec)
KEEP(*(.resetvec))
} :text = 0xffff
. = RESET_VECTOR_ADDRESS + 0x4;
@ -145,9 +114,8 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(.sbss*)
*(.bss*)
*(COMMON)
} :bss

7
arch/powerpc/cpu/mpc86xx/config.mk
View File

@ -25,3 +25,10 @@ PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -ffixed-r2 -mstring
PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
# Enable gc-sections to enable generation of smaller images.
PLATFORM_LDFLAGS += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
# Use default linker script. Board port can override in board/*/config.mk
LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc86xx/u-boot.lds

26
board/xes/xpedite5170/u-boot.lds → arch/powerpc/cpu/mpc86xx/u-boot.lds
View File

@ -60,19 +60,14 @@ SECTIONS
lib/crc32.o (.text)
arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
*(.text)
*(.got1)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@ -80,23 +75,19 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
*(.got)
KEEP(*(.got))
_GOT2_TABLE_ = .;
*(.got2)
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
*(.fixup)
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
@ -121,9 +112,8 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(.sbss*)
*(.bss*)
*(COMMON)
. = ALIGN(4);
}

17
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -1184,6 +1184,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
unsigned int sr_it;
unsigned int zq_en;
unsigned int wrlvl_en;
int cs_en = 1;
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@ -1250,16 +1251,23 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
* and each controller uses rank interleaving within
* itself. Therefore the starting and ending address
* on each controller is twice the amount present on
* each controller.
* each controller. If any CS is not included in the
* interleaving, the memory on that CS is not accssible
* and the total memory size is reduced. The CS is also
* disabled.
*/
unsigned long long ctlr_density = 0;
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1:
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
ctlr_density = dimm_params[0].rank_density * 2;
if (i > 1)
cs_en = 0;
break;
case FSL_DDR_CS2_CS3:
ctlr_density = dimm_params[0].rank_density;
if (i > 0)
cs_en = 0;
break;
case FSL_DDR_CS0_CS1_CS2_CS3:
/*
@ -1379,8 +1387,11 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
);
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
set_csn_config(dimm_number, i, ddr, popts, dimm_params);
set_csn_config_2(i, ddr);
if (cs_en) {
set_csn_config(dimm_number, i, ddr, popts, dimm_params);
set_csn_config_2(i, ddr);
} else
printf("CS%d is disabled.\n", i);
}
set_ddr_eor(ddr, popts);

24
arch/powerpc/cpu/mpc8xxx/fdt.c
View File

@ -27,6 +27,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/mp.h>
#include <asm/fsl_enet.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@ -215,3 +216,26 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
fdt_del_node_and_alias(blob, "crypto");
}
#endif
int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
{
static const char *fsl_phy_enet_if_str[] = {
[MII] = "mii",
[RMII] = "rmii",
[GMII] = "gmii",
[RGMII] = "rgmii",
[RGMII_ID] = "rgmii-id",
[RGMII_RXID] = "rgmii-rxid",
[SGMII] = "sgmii",
[TBI] = "tbi",
[RTBI] = "rtbi",
[XAUI] = "xgmii",
[FSL_ETH_IF_NONE] = "",
};
if (phyc > ARRAY_SIZE(fsl_phy_enet_if_str))
return fdt_setprop_string(blob, offset, "phy-connection-type", "");
return fdt_setprop_string(blob, offset, "phy-connection-type",
fsl_phy_enet_if_str[phyc]);
}

5
arch/powerpc/cpu/mpc8xxx/pci_cfg.c
View File

@ -138,7 +138,10 @@ static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
(1 << 7) | (1 << 0xe) | (1 << 0xf),
(1 << 7) | (1 << 0xf),
},
[LAW_TRGT_IF_PCIE_2] = {
.cfg = (1 << 3) | (1 << 0xe) | (1 << 0xf),
},
};
#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \

8
arch/powerpc/cpu/ppc4xx/cpu_init.c
View File

@ -342,7 +342,7 @@ cpu_init_f (void)
#endif
#if defined(CONFIG_WATCHDOG)
val = mfspr(tcr);
val = mfspr(SPRN_TCR);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
@ -354,11 +354,11 @@ cpu_init_f (void)
val &= ~0x30000000; /* clear WRC bits */
val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
#endif
mtspr(tcr, val);
mtspr(SPRN_TCR, val);
val = mfspr(tsr);
val = mfspr(SPRN_TSR);
val |= 0x80000000; /* enable watchdog timer */
mtspr(tsr, val);
mtspr(SPRN_TSR, val);
reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */

7
arch/powerpc/cpu/ppc4xx/interrupts.c
View File

@ -67,13 +67,6 @@ static __inline__ void set_pit(unsigned long val)
asm volatile("mtpit %0" : : "r" (val));
}
static __inline__ void set_tcr(unsigned long val)
{
asm volatile("mttcr %0" : : "r" (val));
}
static __inline__ void set_evpr(unsigned long val)
{
asm volatile("mtevpr %0" : : "r" (val));

11
arch/powerpc/cpu/ppc4xx/traps.c
View File

@ -46,15 +46,6 @@ extern unsigned long search_exception_table(unsigned long);
*/
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
static __inline__ void set_tsr(unsigned long val)
{
#if defined(CONFIG_440)
asm volatile("mtspr 0x150, %0" : : "r" (val));
#else
asm volatile("mttsr %0" : : "r" (val));
#endif
}
static __inline__ unsigned long get_esr(void)
{
unsigned long val;
@ -364,7 +355,7 @@ DecrementerPITException(struct pt_regs *regs)
/*
* Reset PIT interrupt
*/
set_tsr(0x08000000);
mtspr(SPRN_TSR, 0x08000000);
/*
* Call timer_interrupt routine in interrupts.c

6
arch/powerpc/include/asm/fsl_ddr_sdram.h
View File

@ -213,4 +213,10 @@ typedef struct memctl_options_s {
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
typedef struct fixed_ddr_parm{
int min_freq;
int max_freq;
fsl_ddr_cfg_regs_t *ddr_settings;
} fixed_ddr_parm_t;
#endif

33
arch/powerpc/include/asm/fsl_enet.h Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __ASM_PPC_FSL_ENET_H
#define __ASM_PPC_FSL_ENET_H
enum fsl_phy_enet_if {
MII,
RMII,
GMII,
RGMII,
RGMII_ID,
RGMII_RXID,
RGMII_TXID,
SGMII,
TBI,
RTBI,
XAUI,
FSL_ETH_IF_NONE,
};
int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc);
#endif /* __ASM_PPC_FSL_ENET_H */

1
board/BuS/eb_cpux9k2/config.mk
View File

@ -1 +0,0 @@
CONFIG_SYS_TEXT_BASE = 0x23f00000

7
board/BuS/eb_cpux9k2/cpux9k2.c
View File

@ -66,7 +66,7 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
@ -134,9 +134,8 @@ void reset_phy(void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size =
get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}

3
board/LaCie/edminiv2/config.mk
View File

@ -24,4 +24,5 @@
# MA 02110-1301 USA
#
CONFIG_SYS_TEXT_BASE = 0x00100000
# TEXT_BASE must equal the intended FLASH location of u-boot.
CONFIG_SYS_TEXT_BASE = 0xfff90000

6
board/amcc/sequoia/sequoia.c
View File

@ -155,7 +155,8 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
@ -163,7 +164,8 @@ int misc_init_r(void)
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);

5
board/atmel/at91rm9200ek/Makefile
View File

@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += led.o
COBJS-y += misc.o
ifdef CONFIG_HAS_DATAFLASH
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
COBJS-y += partition.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))

60
board/atmel/at91rm9200ek/at91rm9200ek.c
View File

@ -1,4 +1,8 @@
/*
* (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
*
* derived from previous work
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
@ -23,78 +27,44 @@
*/
#include <common.h>
#include <exports.h>
#include <netdev.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_pmc.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
int board_init(void)
{
/* Enable Ctrlc */
console_init_f ();
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
/*
* memory and cpu-speed are setup before relocation
* so we do _nothing_ here
*/
writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
/* arch number of AT91RM9200EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
return at91emac_register(bis, (u32) AT91_EMAC_BASE);
}
#endif

3
board/atmel/at91rm9200ek/config.mk
View File

@ -1 +1,2 @@
CONFIG_SYS_TEXT_BASE = 0x21f00000
# currently only NOR flash booting is supported
CONFIG_SYS_TEXT_BASE = 0x10000000

58
board/atmel/at91rm9200ek/led.c
View File

@ -3,6 +3,9 @@
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
*
* (C) Copyright 2010
* Andreas Bießmann <andreas.devel@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -23,67 +26,62 @@
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pmc.h>
#define GREEN_LED AT91C_PIO_PB0
#define YELLOW_LED AT91C_PIO_PB1
#define RED_LED AT91C_PIO_PB2
/* bit mask in PIO port B */
#define GREEN_LED (1<<0)
#define YELLOW_LED (1<<1)
#define RED_LED (1<<2)
void green_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(GREEN_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(GREEN_LED, &pio->piob.codr);
}
void yellow_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(YELLOW_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(YELLOW_LED, &pio->piob.codr);
}
void red_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(RED_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(RED_LED, &pio->piob.codr);
}
void green_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(GREEN_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(GREEN_LED, &pio->piob.sodr);
}
void yellow_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(YELLOW_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(YELLOW_LED, &pio->piob.sodr);
}
void red_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(RED_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(RED_LED, &pio->piob.sodr);
}
void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;
at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/* Enable PIOB clock */
writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
writel(1 << AT91_ID_PIOB, &pmc->pcer);
/* Disable peripherals on LEDs */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
/* Enable pins as outputs */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
/* Turn all LEDs OFF */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
}

38
board/atmel/at91rm9200ek/mux.c
View File

@ -1,38 +0,0 @@
#include <config.h>
#include <common.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <dataflash.h>
int AT91F_GetMuxStatus(void)
{
/* Set in PIO mode */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
/* Configure in output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
return 1;
return 0;
}
void AT91F_SelectMMC(void)
{
/* Set in PIO mode */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
/* Configure in output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
/* Set Output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
}
void AT91F_SelectSPI(void)
{
/* Set in PIO mode */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
/* Configure in output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
/* Clear Output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
}

42
board/a4m072/config.mk → board/balloon3/Makefile
View File

@ -1,9 +1,7 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Balloon3 Support
#
# See file CREDITS for list of people who contributed to this
# project.
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@ -21,19 +19,29 @@
# MA 02111-1307 USA
#
#
# a4m072 board:
#
# Valid values for TEXT_BASE is:
#
# 0xFE000000 boot low
#
include $(TOPDIR)/config.mk
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
LIB = $(obj)lib$(BOARD).a
ifndef TEXT_BASE
## Standard: boot low
TEXT_BASE = 0xFE000000
endif
COBJS := balloon3.o
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

238
board/balloon3/balloon3.c Normal file
View File

@ -0,0 +1,238 @@
/*
* Balloon3 Support
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <serial.h>
#include <asm/io.h>
#include <spartan3.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
void balloon3_init_fpga(void);
/*
* Miscelaneous platform dependent initialisations
*/
int board_init(void)
{
/* We have RAM, disable cache */
dcache_disable();
icache_disable();
/* arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0xa0000100;
/* Init the FPGA */
balloon3_init_fpga();
return 0;
}
struct serial_device *default_serial_console(void)
{
return &serial_stuart_device;
}
extern void pxa_dram_init(void);
int dram_init(void)
{
pxa_dram_init();
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
}
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
UHCHR);
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (readl(UHCHR) & UHCHR_FSBIR)
;
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
if (readl(PSSR) & PSSR_OTGPH)
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
void usb_board_init_fail(void)
{
return;
}
void usb_board_stop(void)
{
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
#endif
#if defined(CONFIG_FPGA)
/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
int fpga_pgm_fn(int nassert, int nflush, int cookie)
{
if (nassert)
writel(0x80, GPCR3);
else
writel(0x80, GPSR3);
if (nflush)
writel(0x100, GPCR3);
else
writel(0x100, GPSR3);
return nassert;
}
/* Check GPIO83 -- INITB */
int fpga_init_fn(int cookie)
{
return !(readl(GPLR2) & 0x80000);
}
/* Check GPIO84 -- BUSY */
int fpga_busy_fn(int cookie)
{
return !(readl(GPLR2) & 0x100000);
}
/* Check GPIO111 -- DONE */
int fpga_done_fn(int cookie)
{
return readl(GPLR3) & 0x8000;
}
/* Configure GPIO104 as GPIO and deassert it */
int fpga_pre_config_fn(int cookie)
{
writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
writel(0x100, GPCR3);
return 0;
}
/* Configure GPIO104 as nSKTSEL */
int fpga_post_config_fn(int cookie)
{
writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
return 0;
}
/* Toggle RDnWR */
int fpga_wr_fn(int nassert_write, int flush, int cookie)
{
udelay(1000);
if (nassert_write)
writel(0x100, GPCR3);
else
writel(0x100, GPSR3);
return nassert_write;
}
/* Write program to the FPGA */
int fpga_wdata_fn(uchar data, int flush, int cookie)
{
writeb(data, 0x10f00000);
return 0;
}
/* Toggle Clock pin -- NO-OP */
int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
return assert_clk;
}
/* Toggle ChipSelect pin -- NO-OP */
int fpga_cs_fn(int assert_clk, int flush, int cookie)
{
return assert_clk;
}
Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_init_fn,
NULL, /* err */
fpga_done_fn,
fpga_clk_fn,
fpga_cs_fn,
fpga_wr_fn,
NULL, /* rdata */
fpga_wdata_fn,
fpga_busy_fn,
NULL, /* abort */
fpga_post_config_fn,
};
Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
(void *)&balloon3_fpga_fns, 0);
/* Initialize the FPGA */
void balloon3_init_fpga(void)
{
fpga_init();
fpga_add(fpga_xilinx, &fpga);
}
#else
void balloon3_init_fpga(void) {}
#endif /* CONFIG_FPGA */

33
board/colibri_pxa270/colibri_pxa270.c
View File

@ -22,6 +22,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -65,28 +66,30 @@ int dram_init (void)
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
UHCHR);
UHCHR |= UHCHR_FSBIR;
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (UHCHR & UHCHR_FSBIR);
UHCHR &= ~UHCHR_SSE;
UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
if (PSSR & PSSR_OTGPH)
PSSR |= PSSR_OTGPH;
if (readl(PSSR) & PSSR_OTGPH)
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
UHCRHDA &= ~(0x200);
UHCRHDA |= 0x100;
writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
UHCRHDB |= (0x7<<17);
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
@ -98,14 +101,14 @@ void usb_board_init_fail(void)
void usb_board_stop(void)
{
UHCHR |= UHCHR_FHR;
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
UHCHR &= ~UHCHR_FHR;
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
UHCCOMS |= 1;
writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
CKEN &= ~CKEN10_USBHOST;
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}

5
board/cradle/cradle.c
View File

@ -28,6 +28,7 @@
#include <asm/arch/pxa-regs.h>
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -92,8 +93,8 @@ set_led (int led, int color)
int shift = led * 2;
unsigned long mask = 0x3 << shift;
CRADLE_LED_CLR_REG = mask; /* clear bits */
CRADLE_LED_SET_REG = (color << shift); /* set bits */
writel(mask, GPCR2); /* clear bits */
writel((color << shift), GPSR2); /* set bits */
udelay (5000);
}

4
board/cradle/lowlevel_init.S
View File

@ -34,10 +34,10 @@ DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
.endm
.macro SET_LED val
ldr r6, =CRADLE_LED_CLR_REG
ldr r6, =GPCR2
ldr r7, =0
str r7, [r6]
ldr r6, =CRADLE_LED_SET_REG
ldr r6, =GPSR2
ldr r7, =\val
str r7, [r6]
.endm

13
board/csb226/csb226.c
View File

@ -26,6 +26,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -108,23 +109,23 @@ void csb226_set_led(int led, int state)
switch(led) {
case 0: if (state==1) {
GPCR0 |= CSB226_USER_LED0;
writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
} else if (state==0) {
GPSR0 |= CSB226_USER_LED0;
writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
}
break;
case 1: if (state==1) {
GPCR0 |= CSB226_USER_LED1;
writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
} else if (state==0) {
GPSR0 |= CSB226_USER_LED1;
writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
}
break;
case 2: if (state==1) {
GPCR0 |= CSB226_USER_LED2;
writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
} else if (state==0) {
GPSR0 |= CSB226_USER_LED2;
writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
}
break;
}

37
board/delta/delta.c
View File

@ -28,6 +28,7 @@
#include <malloc.h>
#include <command.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -110,7 +111,7 @@ static uchar kbd_command_prefix[] = "key_cmd";
static void get_pressed_keys(uchar *s)
{
unsigned long val;
val = GPLR3;
val = readl(GPLR3);
if(val & (1<<31))
*s++ = KEYBD_KP_DKIN0;
@ -124,18 +125,18 @@ static void get_pressed_keys(uchar *s)
static void keys_init()
{
CKENB |= CKENB_7_GPIO;
writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Configure GPIOs */
GPIO127 = 0xa840; /* KP_DKIN0 */
GPIO114 = 0xa840; /* KP_DKIN1 */
GPIO125 = 0xa840; /* KP_DKIN2 */
GPIO118 = 0xa840; /* KP_DKIN5 */
writel(0xa840, GPIO127); /* KP_DKIN0 */
writel(0xa840, GPIO114); /* KP_DKIN1 */
writel(0xa840, GPIO125); /* KP_DKIN2 */
writel(0xa840, GPIO118); /* KP_DKIN5 */
/* Configure GPIOs as inputs */
GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
udelay(100);
}
@ -283,11 +284,11 @@ int dram_init (void)
void i2c_init_board()
{
CKENB |= (CKENB_4_I2C);
writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
/* setup I2C GPIO's */
GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */
writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */
}
/* initialize the DA9030 Power Controller */
@ -295,20 +296,20 @@ static void init_DA9030()
{
uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
CKENB |= CKENB_7_GPIO;
writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Rising Edge on EXTON to reset DA9030 */
GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */
GPDR0 |= (1<<17); /* GPIO17 is output */
GSDR0 = (1<<17);
GPCR0 = (1<<17); /* drive GPIO17 low */
GPSR0 = (1<<17); /* drive GPIO17 high */
writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */
writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */
writel((1<<17), GSDR0);
writel((1<<17), GPCR0); /* drive GPIO17 low */
writel((1<<17), GPSR0); /* drive GPIO17 high */
#if CONFIG_SYS_DA9030_EXTON_DELAY
udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
#endif
GPCR0 = (1<<17); /* drive GPIO17 low */
writel((1<<17), GPCR0); /* drive GPIO17 low */
/* reset the watchdog and go active (0xec) */
val = (SYS_CONTROL_A_HWRES_ENABLE |

106
board/delta/nand.c
View File

@ -26,6 +26,7 @@
#include <nand.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#ifdef CONFIG_SYS_DFC_DEBUG1
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
NDDB = *long_buf;
writel(*long_buf, NDDB);
}
}
if(rest) {
@ -120,7 +121,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
*long_buf = NDDB;
*long_buf = readl(NDDB);
}
}
@ -166,8 +167,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
unsigned long dummy;
if(bytes_read < 0) {
read_buf = NDDB;
dummy = NDDB;
read_buf = readl(NDDB);
dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@ -181,7 +182,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
unsigned long cur = OSCR;
unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
@ -192,7 +193,7 @@ static unsigned long get_delta(unsigned long start)
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
unsigned long start = OSCR;
unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
@ -202,14 +203,14 @@ static void wait_us(unsigned long us)
static void dfc_clear_nddb(void)
{
NDCR &= ~NDCR_ND_RUN;
writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
unsigned long ndsr, timeout, start = OSCR;
unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
@ -221,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event)
* OSCR_CLK_FREQ, 1000);
while(1) {
ndsr = NDSR;
ndsr = readl(NDSR);
if(ndsr & event) {
NDSR |= event;
writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
@ -243,11 +244,11 @@ static void dfc_new_cmd(void)
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
NDSR = 0xFFF;
writel(0xfff, NDSR);
/* set NDCR[NDRUN] */
if(!(NDCR & NDCR_ND_RUN))
NDCR |= NDCR_ND_RUN;
if (!(readl(NDCR) & NDCR_ND_RUN))
writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
@ -357,9 +358,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
}
write_cmd:
NDCB0 = ndcb0;
NDCB0 = ndcb1;
NDCB0 = ndcb2;
writel(ndcb0, NDCB0);
writel(ndcb1, NDCB0);
writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
@ -372,36 +373,36 @@ static void dfc_gpio_init(void)
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
GPIO4 = 0x1;
writel(0x1, GPIO4);
DF_ALE_WE1 = 0x00000001;
DF_ALE_WE2 = 0x00000001;
DF_nCS0 = 0x00000001;
DF_nCS1 = 0x00000001;
DF_nWE = 0x00000001;
DF_nRE = 0x00000001;
DF_IO0 = 0x00000001;
DF_IO8 = 0x00000001;
DF_IO1 = 0x00000001;
DF_IO9 = 0x00000001;
DF_IO2 = 0x00000001;
DF_IO10 = 0x00000001;
DF_IO3 = 0x00000001;
DF_IO11 = 0x00000001;
DF_IO4 = 0x00000001;
DF_IO12 = 0x00000001;
DF_IO5 = 0x00000001;
DF_IO13 = 0x00000001;
DF_IO6 = 0x00000001;
DF_IO14 = 0x00000001;
DF_IO7 = 0x00000001;
DF_IO15 = 0x00000001;
writel(0x00000001, DF_ALE_nWE1);
writel(0x00000001, DF_ALE_nWE2);
writel(0x00000001, DF_nCS0);
writel(0x00000001, DF_nCS1);
writel(0x00000001, DF_nWE);
writel(0x00000001, DF_nRE);
writel(0x00000001, DF_IO0);
writel(0x00000001, DF_IO8);
writel(0x00000001, DF_IO1);
writel(0x00000001, DF_IO9);
writel(0x00000001, DF_IO2);
writel(0x00000001, DF_IO10);
writel(0x00000001, DF_IO3);
writel(0x00000001, DF_IO11);
writel(0x00000001, DF_IO4);
writel(0x00000001, DF_IO12);
writel(0x00000001, DF_IO5);
writel(0x00000001, DF_IO13);
writel(0x00000001, DF_IO6);
writel(0x00000001, DF_IO14);
writel(0x00000001, DF_IO7);
writel(0x00000001, DF_IO15);
DF_nWE = 0x1901;
DF_nRE = 0x1901;
DF_CLE_NOE = 0x1900;
DF_ALE_WE1 = 0x1901;
DF_INT_RnB = 0x1900;
writel(0x1901, DF_nWE);
writel(0x1901, DF_nRE);
writel(0x1900, DF_CLE_nOE);
writel(0x1901, DF_ALE_nWE1);
writel(0x1900, DF_INT_RnB);
}
/*
@ -430,7 +431,7 @@ int board_nand_init(struct nand_chip *nand)
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
@ -485,17 +486,19 @@ int board_nand_init(struct nand_chip *nand)
tRP_high = 0;
}
NDTR0CS0 = (tCH << 19) |
writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
(tRP << 0);
(tRP << 0),
NDTR0CS0);
NDTR1CS0 = (tR << 16) |
writel((tR << 16) |
(tWHR << 4) |
(tAR << 0);
(tAR << 0),
NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
@ -512,7 +515,7 @@ int board_nand_init(struct nand_chip *nand)
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
NDCR = (NDCR_SPARE_EN | /* use the spare area */
writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
@ -528,7 +531,8 @@ int board_nand_init(struct nand_chip *nand)
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
NDCR_WRCMDREQM); /* write command request ir masked */
NDCR_WRCMDREQM, /* write command request ir masked */
NDCR);
/* wait 10 us due to cmd buffer clear reset */

8
board/eNET/u-boot.lds
View File

@ -27,7 +27,7 @@ ENTRY(_start)
SECTIONS
{
. = TEXT_BASE; /* Location of bootcode in flash */
. = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
.text : { *(.text*); }
@ -94,11 +94,11 @@ SECTIONS
* The fff0 offset of resetvec is important, however.
*/
. = 0xfffffe00;
.start32 : AT (TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
.start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
. = 0xf800;
.start16 : AT (TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
.start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
. = 0xfff0;
.resetvec : AT (TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
.resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
}

3
board/freescale/corenet_ds/Makefile
View File

@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-$(CONFIG_DDR_SPD) += ddr.o
COBJS-y += ddr.o
COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += law.o
COBJS-y += tlb.o

15
board/freescale/corenet_ds/corenet_ds.c
View File

@ -29,7 +29,6 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
@ -196,20 +195,6 @@ int misc_init_r(void)
return 0;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
puts("Initializing....\n");
dram_size = fsl_ddr_sdram();
setup_ddr_tlbs(dram_size / 0x100000);
puts(" DDR: ");
return dram_size;
}
#ifdef CONFIG_MP
void board_lmb_reserve(struct lmb *lmb)
{

131
board/freescale/corenet_ds/ddr.c
View File

@ -8,9 +8,103 @@
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
extern fixed_ddr_parm_t fixed_ddr_parm_0[];
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
extern fixed_ddr_parm_t fixed_ddr_parm_1[];
#endif
phys_size_t fixed_sdram(void)
{
int i;
sys_info_t sysinfo;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
unsigned int lawbar1_target_id;
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
(sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0)
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_1[i].ddr_settings,
sizeof(ddr_cfg_regs));
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
#endif
/*
* setup laws for DDR. If not interleaving, presuming half memory on
* DDR1 and the other half on DDR2
*/
if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
LAW_TRGT_IF_DDR_INTRLV) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
} else {
#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
/* We require both controllers have identical DIMMs */
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size / 2,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
lawbar1_target_id = LAW_TRGT_IF_DDR_2;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
ddr_size / 2,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
#else
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
#endif
}
return ddr_size;
}
static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
{
@ -190,3 +284,38 @@ void fsl_ddr_board_options(memctl_options_t *popts,
/* Enable ZQ calibration */
popts->zq_en = 1;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
int use_spd = 0;
puts("Initializing....");
#ifdef CONFIG_DDR_SPD
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
if (hwconfig_sub("fsl_ddr", "sdram")) {
if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
use_spd = 1;
else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
use_spd = 0;
else
use_spd = 1;
} else
use_spd = 1;
#endif
if (use_spd) {
puts("using SPD\n");
dram_size = fsl_ddr_sdram();
} else {
puts("using fixed parameters\n");
dram_size = fixed_sdram();
}
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}

356
board/freescale/corenet_ds/p4080ds_ddr.c Normal file
View File

@ -0,0 +1,356 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#define DATARATE_800MHZ 800000000
#define DATARATE_900MHZ 900000000
#define DATARATE_1000MHZ 1000000000
#define DATARATE_1200MHZ 1200000000
#define DATARATE_1300MHZ 1300000000
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
#define CONFIG_SYS_DDR_RCW_1 0x00000000
#define CONFIG_SYS_DDR_RCW_2 0x00000000
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
{DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
{DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
{DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
{0, 0, NULL}
};

15
board/freescale/mpc8360emds/mpc8360emds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@ -22,6 +22,7 @@
#include <spd_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@ -396,10 +397,8 @@ void ft_board_setup(void *blob, bd_t *bd)
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_setprop(blob, path,
"phy-connection-type",
"rgmii-rxid",
sizeof("rgmii-rxid"));
fdt_fixup_phy_connection(blob, path,
RGMII_RXID);
}
#endif
#if defined(CONFIG_HAS_ETH1)
@ -410,10 +409,8 @@ void ft_board_setup(void *blob, bd_t *bd)
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_setprop(blob, path,
"phy-connection-type",
"rgmii-rxid",
sizeof("rgmii-rxid"));
fdt_fixup_phy_connection(blob, path,
RGMII_RXID);
}
#endif
}

8
board/freescale/mpc837xemds/mpc837xemds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* CREDITS: Kim Phillips contribute to LIBFDT code
@ -15,6 +15,7 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <asm/fsl_enet.h>
#include <spd_sdram.h>
#include <tsec.h>
#include <libfdt.h>
@ -136,7 +137,6 @@ int board_eth_init(bd_t *bd)
static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
int phy_addr)
{
const char *phy_type = "sgmii";
const u32 *ph;
int off;
int err;
@ -148,8 +148,8 @@ static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
return;
}
err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
strlen(phy_type) + 1);
err = fdt_fixup_phy_connection(blob, off, SGMII);
if (err) {
printf("WARNING: could not set phy-connection-type for %s: "
"%s.\n", alias, fdt_strerror(err));

4
board/freescale/mpc8569mds/mpc8569mds.c
View File

@ -622,8 +622,8 @@ void ft_board_setup(void *blob, bd_t *bd)
break;
}
err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
"rmii");
err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
if (err < 0) {
printf("WARNING: could not set phy-connection-type "
"%s.\n", fdt_strerror(err));

132
board/freescale/mpc8610hpcd/u-boot.lds
View File

@ -1,132 +0,0 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
arch/powerpc/cpu/mpc86xx/start.o (.text)
arch/powerpc/cpu/mpc86xx/traps.o (.text)
arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
arch/powerpc/cpu/mpc86xx/cpu.o (.text)
arch/powerpc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

97
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View File

@ -142,56 +142,26 @@ int first_free_busno = 0;
void pci_init_board(void)
{
struct fsl_pci_info pci_info[2];
int pcie_ep;
int num = 0;
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
struct pci_region *r = hose->regions;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint devdisr = gur->devdisr;
uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
#endif
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
debug("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
hose->first_busno,hose->last_busno);
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf(" PCIE1 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
@ -201,45 +171,22 @@ void pci_init_board(void)
+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
} else {
puts("PCI-EXPRESS 1: Disabled\n");
puts(" PCIE1: disabled\n");
}
}
#else
puts("PCI-EXPRESS1: Disabled\n");
puts(" PCIE1: disabled\n");
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
struct pci_region *r = hose->regions;
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
hose->first_busno,hose->last_busno);
}
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf(" PCIE2 connected as %s (base addr %lx)\n",
pcie_ep ? "Endpoint" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
#else
puts("PCI-EXPRESS 2: Disabled\n");
puts(" PCIE2: disabled\n");
#endif /* CONFIG_PCIE2 */
}

133
board/freescale/mpc8641hpcn/u-boot.lds
View File

@ -1,133 +0,0 @@
/*
* Copyright 2006, 2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
arch/powerpc/cpu/mpc86xx/start.o (.text)
arch/powerpc/cpu/mpc86xx/traps.o (.text)
arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
arch/powerpc/cpu/mpc86xx/cpu.o (.text)
arch/powerpc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
drivers/bios_emulator/atibios.o (.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
}

2
board/freescale/mx51evk/mx51evk.c
View File

@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx51_pins.h>
#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>

14
board/innokom/innokom.c
View File

@ -27,6 +27,7 @@
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -48,20 +49,21 @@ int i2c_init_board(void)
/* disable I2C controller first, otherwhise it thinks we want to */
/* talk to the slave port... */
icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
icr = readl(ICR);
writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
/* set gpio pin low _before_ we change direction to output */
GPCR(70) = GPIO_bit(70);
writel(GPIO_bit(70), GPCR(70));
/* now toggle between output=low and high-impedance */
for (i = 0; i < 20; i++) {
GPDR(70) |= GPIO_bit(70); /* output */
writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
udelay(10);
GPDR(70) &= ~GPIO_bit(70); /* input */
writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
udelay(10);
}
ICR = icr;
writel(icr, ICR);
return 0;
}
@ -76,7 +78,7 @@ int misc_init_r(void)
char *str;
/* determine if the software update key is pressed during startup */
if (GPLR0 & 0x00000800) {
if (readl(GPLR0) & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {

18
board/nc650/Makefile → board/jornada/Makefile
View File

@ -1,8 +1,9 @@
#
# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
# (C) Copyright 2004-2006
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# 2004 (c) MontaVista Software, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
@ -26,14 +27,21 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o nand.o flash.o
COBJS := jornada.o
SOBJS := setup.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################

42
board/atmel/at91rm9200ek/misc.c → board/jornada/jornada.c
View File

@ -3,6 +3,8 @@
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* 2004 (c) MontaVista Software, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -23,28 +25,36 @@
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
#include <net.h>
#include <SA-1100.h>
int board_late_init(void)
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
gd->bd->bi_boot_params = 0xc0000100;
/*
* Turn on flashing.
* Would be nice to have some protection but
* that would have to be implemented in the
* flash init function, which isnt possible yet.
*/
PPSR |= (1 << 7);
PPDR |= (1 << 7);
/* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
eth_init(gd->bd);
return 0;
}
/* checks if addr is in RAM */
int addr2ram(ulong addr)
int dram_init(void)
{
int result = 0;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
result = 1;
return result;
return (0);
}

210
board/jornada/setup.S Normal file
View File

@ -0,0 +1,210 @@
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
* 2004 (c) MontaVista Software, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "config.h"
#include "version.h"
/*-----------------------------------------------------------------------
* Board defines:
*/
#define MDCNFG 0x00
#define MDCAS00 0x04
#define MDCAS01 0x08
#define MDCAS02 0x0C
#define MSC0 0x10
#define MSC1 0x14
#define MECR 0x18
#define MDREFR 0x1C
#define MDCAS20 0x20
#define MDCAS21 0x24
#define MDCAS22 0x28
#define MSC2 0x2C
#define SMCNFG 0x30
#define GPDR 0x04
#define GPSR 0x08
#define GPCR 0x0C
#define GAFR 0x1C
#define PPDR 0x00
#define PPSR 0x04
#define PPAR 0x08
#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
#define MDREFR_K0DB2 (1 << 18)
#define MDREFR_K1DB2 (1 << 22)
#define MDREFR_K2DB2 (1 << 26)
#define MDREFR_K0RUN (1 << 17)
#define MDREFR_K1RUN (1 << 21)
#define MDREFR_K2RUN (1 << 25)
#define MDREFR_SLFRSH (1 << 31)
#define MDREFR_E1PIN (1 << 20)
#define PSSR 0x04
#define PSSR_DH 0x00000008
#define POSR 0x08
#define RCSR 0x04
/*-----------------------------------------------------------------------
* Setup parameters for the board:
*/
MEM_BASE: .long 0xa0000000
MEM_START: .long 0xc0000000
PWR_BASE: .word 0x90020000
RST_BASE: .long 0x90030000
PPC_BASE: .long 0x90060000
GPIO_BASE: .long 0x90040000
IC_BASE: .word 0x90050000
cpuspeed: .word 0xa0
/* calculated from old blob bootloader */
mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
msc2: .long 0x201d2959 /* msc2 0x201d2959 */
smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
pin_set_out: .long 0x37ff70
pin_set_dir: .long 0x11480
gpdr_set: .long 0x0B3A0900
gpsr_set: .long 0x02100800
gpcr_set: .long 0x092A0100
gafr_set: .long 0x08600000
.globl lowlevel_init
lowlevel_init:
/* set output and direction of pins */
ldr r0, PPC_BASE
ldr r1, pin_set_out
str r1, [r0, #PPSR]
ldr r1, pin_set_dir
str r1, [r0, #PPDR]
/* Setting up the memory and stuff */
/***********************************/
ldr r0, MEM_BASE
ldr r1, mdcnfg
str r1, [r0, #MDCNFG]
ldr r1, mdcas00
str r1, [r0, #MDCAS00]
ldr r1, mdcas01
str r1, [r0, #MDCAS01]
ldr r1, mdcas02
str r1, [r0, #MDCAS02]
ldr r1, mdcas20
str r1, [r0, #MDCAS20]
ldr r1, mdcas21
str r1, [r0, #MDCAS21]
ldr r1, mdcas22
str r1, [r0, #MDCAS22]
/* clear kxDB2 */
ldr r2, [r0, #MDREFR]
bic r2, r2, #MDREFR_K0DB2
bic r2, r2, #MDREFR_K1DB2
bic r2, r2, #MDREFR_K2DB2
str r2, [r0, #MDREFR]
ldr r2, [r0, #MDREFR]
orr r2, r2, #MDREFR_TRASR(7)
mov r4, #0x2000
spin: subs r4, r4, #1
bne spin
ldr r1, PWR_BASE
mov r2, #PSSR_DH
str r2, [r1, #PSSR]
ldr r2, [r0, #MDREFR]
bic r2, r2, #MDREFR_K0DB2
bic r2, r2, #MDREFR_K1DB2
bic r2, r2, #MDREFR_K2DB2
str r2, [r0, #MDREFR]
ldr r2, [r0, #MDREFR]
orr r2, r2, #MDREFR_TRASR(7)
orr r2, r2, #MDREFR_DRI(12)
orr r2, r2, #MDREFR_K0DB2
orr r2, r2, #MDREFR_K1DB2
orr r2, r2, #MDREFR_K2DB2
str r2, [r0, #MDREFR]
ldr r2, [r0, #MDREFR]
orr r2, r2, #MDREFR_K0RUN
orr r2, r2, #MDREFR_K1RUN
orr r2, r2, #MDREFR_K2RUN
str r2, [r0, #MDREFR]
ldr r2, [r0, #MDREFR]
bic r2, r2, #MDREFR_SLFRSH
str r2, [r0, #MDREFR]
ldr r2, [r0, #MDREFR]
orr r2, r2, #MDREFR_E1PIN
str r2, [r0, #MDREFR]
ldr r2, MEM_START
.rept 8
ldr r3, [r2]
.endr
ldr r1, msc0
str r1, [r0, #MSC0]
ldr r1, msc1
str r1, [r0, #MSC1]
ldr r1, msc2
str r1, [r0, #MSC2]
ldr r1, smcnfg
str r1, [r0, #SMCNFG]
ldr r1, mdcnfg
str r1, [r0, #MDCNFG]
ldr r1, mecr
str r1, [r0, #MECR]
/* enable SDRAM */
orr r1, r1, #0x00000001
str r1, [r0, #MDCNFG]
mov pc, lr

58
board/jornada/u-boot.lds Normal file
View File

@ -0,0 +1,58 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* 2004 (c) MontaVista Software, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/sa1100/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}

2
board/karo/tx25/config.mk
View File

@ -1,5 +1,5 @@
ifdef CONFIG_NAND_SPL
CONFIG_SYS_TEXT_BASE = 0x810c0000
else
CONFIG_SYS_TEXT_BASE = 0x81fc0000
CONFIG_SYS_TEXT_BASE = 0x81200000
endif

4
board/logicpd/imx27lite/config.mk
View File

@ -1 +1,5 @@
# with relocation CONFIG_SYS_TEXT_BASE can be anything, and making it 0
# makes relative and absolute relocation fixups interchangeable.
#CONFIG_SYS_TEXT_BASE = 0
CONFIG_SYS_TEXT_BASE = 0xc0000000

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