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Tom Rini 2022-07-11 10:18:13 -04:00
commit 36b661dc91
2646 changed files with 37618 additions and 39288 deletions
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9
.azure-pipelines.yml
View File

@ -261,6 +261,9 @@ stages:
evb_ast2500:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
evb_ast2600:
TEST_PY_BD: "evb-ast2600"
TEST_PY_ID: "--id qemu"
vexpress_ca9x4:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
@ -473,6 +476,12 @@ stages:
BUILDMAN: "imx8"
keystone2_keystone3:
BUILDMAN: "k2 k3"
sandbox_asan:
BUILDMAN: "sandbox"
OVERRIDE: "-a ASAN"
sandbox_clang_asan:
BUILDMAN: "sandbox"
OVERRIDE: "-O clang-13 -a ASAN"
samsung_socfpga:
BUILDMAN: "samsung socfpga"
sun4i:

6
.gitlab-ci.yml
View File

@ -272,6 +272,12 @@ evb-ast2500 test.py:
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
evb-ast2600 test.py:
variables:
TEST_PY_BD: "evb-ast2600"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
sandbox_flattree test.py:
variables:
TEST_PY_BD: "sandbox_flattree"

42
Kconfig
View File

@ -154,6 +154,22 @@ config CC_COVERAGE
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
config ASAN
bool "Enable AddressSanitizer"
depends on SANDBOX
help
Enables AddressSanitizer to discover out-of-bounds accesses,
use-after-free, double-free and memory leaks.
config FUZZ
bool "Enable fuzzing"
depends on CC_IS_CLANG
depends on DM_FUZZING_ENGINE
select ASAN
help
Enables the fuzzing infrastructure to generate fuzzing data and run
fuzz tests.
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
@ -228,12 +244,38 @@ config SYS_BOOT_GET_CMDLINE
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
config SYS_BARGSIZE
int "Size of kernel command line buffer in bytes"
depends on SYS_BOOT_GET_CMDLINE
default 512
help
Buffer size for Boot Arguments which are passed to the application
(usually a Linux kernel) when it is booted
config SYS_BOOT_GET_KBD
bool "Enable kernel board information setup"
help
Enables allocating and saving a kernel copy of the bd_info in
space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
config HAS_CUSTOM_SYS_INIT_SP_ADDR
bool "Use a custom location for the initial stack pointer address"
depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
default y if TFABOOT
help
Typically, we use an initial stack pointer address that is calculated
by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different
but statica calculation is performed. However, some platforms will
take a different approach. Say Y here to define the address statically
instead.
config CUSTOM_SYS_INIT_SP_ADDR
hex "Static location for the initial stack pointer"
depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
default SYS_TEXT_BASE if TFABOOT
config SYS_MALLOC_F
bool "Enable malloc() pool before relocation"
default y if DM

52
MAINTAINERS
View File

@ -207,6 +207,17 @@ F: drivers/pinctrl/broadcom/
F: configs/rpi_*
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
ARM BROADCOM BCMBCA
M: Anand Gore <anand.gore@broadcom.com>
M: William Zhang <william.zhang@broadcom.com>
M: Kursad Oney <kursad.oney@broadcom.com>
M: Joel Peshkin <joel.peshkin@broadcom.com>
S: Maintained
F: arch/arm/mach-bcmbca/
F: board/broadcom/bcmbca/
F: configs/bcm947622_defconfig
F: include/configs/bcm947622.h
ARM BROADCOM BCMSTB
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
S: Maintained
@ -269,6 +280,19 @@ F: arch/arm/cpu/armv8/hisilicon
F: arch/arm/include/asm/arch-hi6220/
F: arch/arm/include/asm/arch-hi3660/
ARM HPE GXP ARCHITECTURE
M: Jean-Marie Verdun <verdun@hpe.com>
M: Nick Hawkins <nick.hawkins@hpe.com>
S: Maintained
F: arch/arm/dts/hpe-bmc*
F: arch/arm/dts/hpe-gxp*
F: arch/arm/mach-hpe/
F: board/hpe/
F: configs/gxp_defconfig
F: doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
F: drivers/timer/gxp-timer.c
F: drivers/spi/gxp_spi.c
ARM IPQ40XX
M: Robert Marko <robert.marko@sartura.hr>
M: Luka Kovacic <luka.kovacic@sartura.hr>
@ -283,6 +307,11 @@ F: drivers/spi/spi-qup.c
F: drivers/net/mdio-ipq4019.c
F: drivers/rng/msm_rng.c
ARM LAYERSCAPE SFP
M: Sean Anderson <sean.anderson@seco.com>
S: Maintained
F: drivers/misc/ls2_sfp.c
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
S: Maintained
@ -320,13 +349,6 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: drivers/serial/serial_mvebu_a3700.c
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-pxa.git
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
@ -481,7 +503,7 @@ S: Maintained
F: arch/arm/mach-stm32mp/
F: doc/board/st/
F: drivers/adc/stm32-adc*
F: drivers/clk/clk_stm32mp1.c
F: drivers/clk/stm32/
F: drivers/gpio/stm32_gpio.c
F: drivers/hwspinlock/stm32_hwspinlock.c
F: drivers/i2c/stm32f7_i2c.c
@ -612,6 +634,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
F: drivers/net/xilinx_axi_mrmac.*
F: drivers/soc/soc_xilinx_versal.c
F: drivers/spi/cadence_ospi_versal.c
F: drivers/watchdog/xilinx_wwdt.c
N: (?<!uni)versal
@ -976,6 +999,7 @@ F: drivers/net/xilinx_emaclite.c
F: drivers/serial/serial_xuartlite.c
F: drivers/spi/xilinx_spi.c
F: drivers/sysreset/sysreset_gpio.c
F: drivers/timer/xilinx-timer.c
F: drivers/watchdog/xilinx_tb_wdt.c
N: xilinx
@ -1093,6 +1117,13 @@ F: cmd/nvme.c
F: include/nvme.h
F: doc/develop/driver-model/nvme.rst
NVMEM
M: Sean Anderson <seanga2@gmail.com>
S: Maintained
F: doc/api/nvmem.rst
F: drivers/misc/nvmem.c
F: include/nvmem.h
NXP C45 TJA11XX PHY DRIVER
M: Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
S: Maintained
@ -1244,6 +1275,11 @@ F: drivers/gpio/sl28cpld-gpio.c
F: drivers/misc/sl28cpld.c
F: drivers/watchdog/sl28cpld-wdt.c
SMCCC TRNG
M: Etienne Carriere <etienne.carriere@linaro.org>
S: Maintained
F: drivers/rng/smccc_trng.c
SPI
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

14
Makefile
View File

@ -673,6 +673,12 @@ else
include/config/auto.conf: ;
endif # $(dot-config)
ifdef CONFIG_CC_OPTIMIZE_FOR_DEBUG
KBUILD_HOSTCFLAGS := -Wall -Wstrict-prototypes -Og -g -fomit-frame-pointer \
$(HOST_LFS_CFLAGS) $(HOSTCFLAGS)
KBUILD_HOSTCXXFLAGS := -Og -g $(HOST_LFS_CFLAGS) $(HOSTCXXFLAGS)
endif
#
# Xtensa linker script cannot be preprocessed with -ansi because of
# preprocessor operations on strings that don't make C identifiers.
@ -922,12 +928,10 @@ endif
# the raw binary, but certain simulators only accept an ELF file (but don't
# do the relocation).
ifneq ($(CONFIG_STATIC_RELA),)
# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
# $(2) is u-boot ELF, $(3) is u-boot bin, $(4) is text base
quiet_cmd_static_rela = RELOC $@
cmd_static_rela = \
start=$$($(NM) $(2) | grep __rel_dyn_start | cut -f 1 -d ' '); \
end=$$($(NM) $(2) | grep __rel_dyn_end | cut -f 1 -d ' '); \
tools/relocate-rela $(3) $(4) $$start $$end
tools/relocate-rela $(3) $(2)
else
quiet_cmd_static_rela =
cmd_static_rela =
@ -2209,7 +2213,7 @@ CLEAN_DIRS += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
include/generated/env.in drivers/video/u_boot_logo.S \
include/generated/env.* drivers/video/u_boot_logo.S \
tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \

253
README
View File

@ -293,33 +293,6 @@ board_init_r():
SPL-specific notes:
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
CONFIG_SPL_STACK_R_ADDR points into SDRAM
- preloader_console_init() can be called here - typically this is
done by selecting CONFIG_SPL_BOARD_INIT and then supplying a
spl_board_init() function containing this call
- loads U-Boot or (in falcon mode) Linux
Configuration Options:
----------------------
Configuration depends on the combination of board and CPU type; all
such information is kept in a configuration file
"include/configs/<board_name>.h".
Example: For a TQM823L module, all configuration settings are in
"include/configs/TQM823L.h".
Many of the options are named exactly as the corresponding Linux
kernel configuration options. The intention is to make it easier to
build a config tool - later.
- ARM Platform Bus Type(CCI):
CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
provides full cache coherency between two clusters of multi-core
CPUs and I/O coherency for devices and I/O masters
CONFIG_SYS_FSL_HAS_CCI400
Defined For SoC that has cache coherent interconnect
@ -398,10 +371,6 @@ The following options need to be configured:
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
CONFIG_SYS_CPC_REINIT_F
This CONFIG is defined when the CPC is configured as SRAM at the
time of U-Boot entry and is required to be re-initialized.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
@ -415,10 +384,6 @@ The following options need to be configured:
CONFIG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_DDR_EMU
Specify emulator support for DDR. Some DDR features such as
deskew training are not available.
CONFIG_SYS_FSL_DDRC_GEN1
Freescale DDR1 controller.
@ -493,12 +458,6 @@ The following options need to be configured:
Defines the SEC controller register space as Little Endian
- MIPS CPU options:
CONFIG_SYS_INIT_SP_OFFSET
Offset relative to CONFIG_SYS_SDRAM_BASE for initial stack
pointer. This is needed for the temporary stack before
relocation.
CONFIG_XWAY_SWAP_BYTES
Enable compilation of tools/xway-swap-bytes needed for Lantiq
@ -697,18 +656,6 @@ The following options need to be configured:
CONFIG_SCSI) you must configure support for at
least one non-MTD partition type as well.
- LBA48 Support
CONFIG_LBA48
Set this to enable support for disks larger than 137GB
Also look at CONFIG_SYS_64BIT_LBA.
Whithout these , LBA48 support uses 32bit variables and will 'only'
support disks up to 2.1TB.
CONFIG_SYS_64BIT_LBA:
When enabled, makes the IDE subsystem use 64bit sector addresses.
Default is 32bit.
- NETWORK Support (PCI):
CONFIG_E1000_SPI
Utility code for direct access to the SPI bus on Intel 8257x.
@ -826,9 +773,6 @@ The following options need to be configured:
Supported are USB Keyboards and USB Floppy drives
(TEAC FD-05PUB).
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
CONFIG_USB_DWC2_REG_ADDR the physical CPU address of the DWC2
HW module registers.
@ -902,13 +846,6 @@ The following options need to be configured:
the appropriate value in Hz.
- MMC Support:
The MMC controller on the Intel PXA is supported. To
enable this define CONFIG_MMC. The MMC can be
accessed from the boot prompt by mapping the device
to physical memory similar to flash. Command line is
enabled with CONFIG_CMD_MMC. The MMC driver also works with
the FAT fs. This is enabled with CONFIG_CMD_FAT.
CONFIG_SH_MMCIF
Support for Renesas on-chip MMCIF controller
@ -1354,11 +1291,6 @@ The following options need to be configured:
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
CONFIG_SYS_SPD_BUS_NUM
If defined, then this indicates the I2C bus number for DDR SPD.
If not defined, then U-Boot assumes that SPD is on I2C bus 0.
CONFIG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC.
@ -1398,10 +1330,6 @@ The following options need to be configured:
Enables support for FPGA family.
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
CONFIG_FPGA_COUNT
Specify the number of FPGA devices to support.
CONFIG_SYS_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration.
@ -1570,20 +1498,6 @@ The following options need to be configured:
overwriting the architecture dependent default
settings.
- Frame Buffer Address:
CONFIG_FB_ADDR
Define CONFIG_FB_ADDR if you want to use specific
address for frame buffer. This is typically the case
when using a graphics controller has separate video
memory. U-Boot will then place the frame buffer at
the given address instead of dynamically reserving it
in system RAM by calling lcd_setmem(), which grabs
the memory for the frame buffer depending on the
configured panel size.
Please see board_init_f function.
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
@ -1658,36 +1572,6 @@ The following options need to be configured:
CONFIG_SPL
Enable building of SPL globally.
CONFIG_SPL_MAX_FOOTPRINT
Maximum size in memory allocated to the SPL, BSS included.
When defined, the linker checks that the actual memory
used by SPL from _start to __bss_end does not exceed it.
CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
must not be both defined at the same time.
CONFIG_SPL_MAX_SIZE
Maximum size of the SPL image (text, data, rodata, and
linker lists sections), BSS excluded.
When defined, the linker checks that the actual size does
not exceed it.
CONFIG_SPL_RELOC_TEXT_BASE
Address to relocate to. If unspecified, this is equal to
CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
CONFIG_SPL_BSS_START_ADDR
Link address for the BSS within the SPL binary.
CONFIG_SPL_BSS_MAX_SIZE
Maximum size in memory allocated to the SPL BSS.
When defined, the linker checks that the actual memory used
by SPL from __bss_start to __bss_end does not exceed it.
CONFIG_SPL_MAX_FOOTPRINT and CONFIG_SPL_BSS_MAX_SIZE
must not be both defined at the same time.
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
CONFIG_SPL_PANIC_ON_RAW_IMAGE
When defined, SPL will panic() if the image it has
loaded does not have a signature.
@ -1698,65 +1582,20 @@ The following options need to be configured:
consider that a completely unreadable NAND block is bad,
and thus should be skipped silently.
CONFIG_SPL_RELOC_STACK
Adress of the start of the stack SPL will use after
relocation. If unspecified, this is equal to
CONFIG_SPL_STACK.
CONFIG_SYS_SPL_MALLOC_START
Starting address of the malloc pool used in SPL.
When this option is set the full malloc is used in SPL and
it is set up by spl_init() and before that, the simple malloc()
can be used if CONFIG_SYS_MALLOC_F is defined.
CONFIG_SYS_SPL_MALLOC_SIZE
The size of the malloc pool used in SPL.
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
CONFIG_SPL_INIT_MINIMAL
Arch init code should be built for a very small image
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
Sector and number of sectors to load kernel argument
parameters from when MMC is being used in raw mode
(for falcon mode)
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
Filename to read to load U-Boot when reading from filesystem
CONFIG_SPL_FS_LOAD_KERNEL_NAME
Filename to read to load kernel uImage when reading
from filesystem (for Falcon mode)
CONFIG_SPL_FS_LOAD_ARGS_NAME
Filename to read to load kernel argument parameters
when reading from filesystem (for Falcon mode)
CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
Set this for NAND SPL on PPC mpc83xx targets, so that
start.S waits for the rest of the SPL to load before
continuing (the hardware starts execution after just
loading the first page rather than the full 4K).
CONFIG_SPL_SKIP_RELOCATE
Avoid SPL relocation
CONFIG_SPL_UBI
Support for a lightweight UBI (fastmap) scanner and
loader
CONFIG_SPL_NAND_RAW_ONLY
Support to boot only raw u-boot.bin images. Use this only
if you need to save space.
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
SPL binary.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@ -1781,35 +1620,12 @@ The following options need to be configured:
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary
CONFIG_SPL_PAD_TO
Image offset to which the SPL should be padded before appending
the SPL payload. By default, this is defined as
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
use an arch-specific makefile fragment instead, for
example if more than one image needs to be produced.
CONFIG_SPL_FIT_PRINT
Printing information about a FIT image adds quite a bit of
code to SPL. So this is normally disabled in SPL. Use this
option to re-enable it. This will affect the output of the
bootm command when booting a FIT image.
- TPL framework
CONFIG_TPL
Enable building of TPL globally.
CONFIG_TPL_PAD_TO
Image offset to which the TPL should be padded before appending
the TPL payload. By default, this is defined as
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
- Interrupt support (PPC):
There are common interrupt_init() and timer_interrupt()
@ -1853,16 +1669,6 @@ Configuration Settings:
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
- CONFIG_SYS_CBSIZE: Buffer size for input from the Console
- CONFIG_SYS_PBSIZE: Buffer size for Console output
- CONFIG_SYS_MAXARGS: max. Number of arguments accepted for monitor commands
- CONFIG_SYS_BARGSIZE: Buffer size for Boot Arguments which are passed to
the application (usually a Linux kernel) when it is
booted
- CONFIG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
@ -1909,7 +1715,7 @@ Configuration Settings:
- CONFIG_SYS_MALLOC_SIMPLE
Provides a simple and small malloc() and calloc() for those
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC_START).
enabled with CONFIG_SYS_SPL_MALLOC).
- CONFIG_SYS_NONCACHED_MEMORY:
Size of non-cached memory area. This area of memory will be
@ -1930,12 +1736,6 @@ Configuration Settings:
Non-cached memory is only supported on 32-bit ARM at present.
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
you can define CONFIG_SYS_BOOTM_LEN in your board config file
to adjust this setting to your needs.
- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
@ -1948,11 +1748,6 @@ Configuration Settings:
CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_RAMDISK_HIGH:
Enable initrd_high functionality. If defined then the
initrd_high feature is enabled and the bootm ramdisk subcommand
is enabled.
- CONFIG_SYS_BOOT_GET_CMDLINE:
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
@ -2033,14 +1828,6 @@ Configuration Settings:
while unprotecting/erasing/programming. Please only enable
this option if you really know what you are doing.
- CONFIG_ENV_MAX_ENTRIES
Maximum number of entries in the hash table that is used
internally to store the environment settings. The default
setting is supposed to be generous and should work in most
cases. This setting can be used to tune behaviour; see
lib/hashtable.c for details.
- CONFIG_ENV_FLAGS_LIST_DEFAULT
- CONFIG_ENV_FLAGS_LIST_STATIC
Enable validation of the values given to environment variables when
@ -2186,10 +1973,6 @@ Low Level (hardware related) configuration options:
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
- CONFIG_SYS_CCSR_DO_NOT_RELOCATE:
If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
forced to a value that ensures that CCSR is not relocated.
- CONFIG_SYS_IMMR: Physical address of the Internal Memory.
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
@ -2207,24 +1990,6 @@ Low Level (hardware related) configuration options:
U-Boot uses the following memory types:
- MPC8xx: IMMR (internal memory of the CPU)
- CONFIG_SYS_GBL_DATA_OFFSET:
Offset of the initial data structure in the memory
area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
GENERATED_GBL_DATA_SIZE), and the initial stack is just
below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET) downward.
Note:
On the MPC824X (or other systems that use the data
cache for initial memory) the address chosen for
CONFIG_SYS_INIT_RAM_ADDR is basically arbitrary - it must
point to an otherwise UNUSED address space between
the top of RAM and the start of the PCI space.
- CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM:
@ -2278,12 +2043,6 @@ Low Level (hardware related) configuration options:
one, specify here. Note that the value must resolve
to something your driver can deal with.
- CONFIG_SYS_DDR_RAW_TIMING
Get DDR timing information from other than SPD. Common with
soldered DDR chips onboard without SPD. DDR raw timing
parameters are extracted from datasheet and hard-coded into
header files or board specific files.
- CONFIG_FSL_DDR_INTERACTIVE
Enable interactive DDR debugging. See doc/README.fsl-ddr.
@ -2293,10 +2052,6 @@ Low Level (hardware related) configuration options:
- CONFIG_FSL_DDR_BIST
Enable built-in memory test for Freescale DDR controllers.
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
- CONFIG_RMII
Enable RMII mode for all FECs.
Note that this is a global option, we can't
@ -2342,11 +2097,6 @@ Low Level (hardware related) configuration options:
proper). Code that needs stage-specific behavior should check
this.
- CONFIG_SYS_MPC85XX_NO_RESETVEC
Only for 85xx systems. If this variable is specified, the section
.resetvec is not kept and the section .bootpg is placed in the
previous 4k of the .text section.
- CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
effective address. It is therefore not necessary to regard
@ -2578,6 +2328,7 @@ rarpboot- boot image via network using RARP/TFTP protocol
diskboot- boot from IDE devicebootd - boot default, i.e., run 'bootcmd'
loads - load S-Record file over serial line
loadb - load binary file over serial line (kermit mode)
loadm - load binary blob from source address to destination address
md - memory display
mm - memory modify (auto-incrementing)
nm - memory modify (constant address)

43
arch/Kconfig
View File

@ -8,9 +8,6 @@ config CREATE_ARCH_SYMLINK
config HAVE_ARCH_IOREMAP
bool
config NEEDS_MANUAL_RELOC
bool
config SYS_CACHE_SHIFT_4
bool
@ -76,9 +73,12 @@ config M68K
config MICROBLAZE
bool "MicroBlaze architecture"
select NEEDS_MANUAL_RELOC
select SUPPORT_OF_CONTROL
imply CMD_IRQ
imply CMD_TIMER
imply SPL_REGMAP if SPL
imply SPL_TIMER if SPL
imply TIMER
imply XILINX_TIMER
config MIPS
bool "MIPS architecture"
@ -135,6 +135,7 @@ config SANDBOX
select BZIP2
select CMD_POWEROFF
select DM
select DM_FUZZING_ENGINE
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
@ -170,6 +171,7 @@ config SANDBOX
imply CRC32_VERIFY
imply FAT_WRITE
imply FIRMWARE
imply FUZZING_ENGINE_SANDBOX
imply HASH_VERIFY
imply LZMA
imply TEE
@ -371,6 +373,9 @@ config SYS_IMMR
default 0xF0000000 if ARCH_MPC8313
default 0xE0000000 if MPC83xx && !ARCH_MPC8313
default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
ARCH_P2020
default SYS_CCSRBAR_DEFAULT
help
Address for the Internal Memory-Mapped Registers (IMMR) window used
@ -446,4 +451,32 @@ source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig"
source "arch/riscv/Kconfig"
if ARM || M68K || PPC
source "arch/Kconfig.nxp"
endif
source "board/keymile/Kconfig"
if MIPS || MICROBLAZE
choice
prompt "Endianness selection"
help
Some MIPS boards can be configured for either little or big endian
byte order. These modes require different U-Boot images. In general there
is one preferred byteorder for a particular system but some systems are
just as commonly used in the one or the other endianness.
config SYS_BIG_ENDIAN
bool "Big endian"
depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
config SYS_LITTLE_ENDIAN
bool "Little endian"
depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
endchoice
endif

241
arch/Kconfig.nxp Normal file
View File

@ -0,0 +1,241 @@
config NXP_ESBC
bool "NXP ESBC (secure boot) functionality"
help
Enable Freescale Secure Boot feature. Normally selected by defconfig.
If unsure, do not change.
menu "Chain of trust / secure boot options"
depends on !FIT_SIGNATURE && NXP_ESBC
config CHAIN_OF_TRUST
select FSL_CAAM
select ARCH_MISC_INIT
select FSL_SEC_MON
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
imply CMD_BLOB
imply CMD_HASH if ARM
def_bool y
config CMD_ESBC_VALIDATE
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
default y
help
This option enables two commands used for secure booting:
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
config ESBC_HDR_LS
bool
config ESBC_ADDR_64BIT
def_bool y
depends on ESBC_HDR_LS && FSL_LAYERSCAPE
help
For Layerscape based platforms, ESBC image Address in Header is 64bit.
config SYS_FSL_SFP_BE
def_bool y
depends on PPC || FSL_LSCH2 || ARCH_LS1021A
config SYS_FSL_SFP_LE
def_bool y
depends on !SYS_FSL_SFP_BE
choice
prompt "SFP IP revision"
default SYS_FSL_SFP_VER_3_0 if PPC
default SYS_FSL_SFP_VER_3_4
config SYS_FSL_SFP_VER_3_0
bool "SFP version 3.0"
config SYS_FSL_SFP_VER_3_2
bool "SFP version 3.2"
config SYS_FSL_SFP_VER_3_4
bool "SFP version 3.4"
endchoice
config SPL_UBOOT_KEY_HASH
string "Non-SRK key hash for U-Boot public/private key pair"
depends on SPL
default ""
help
Set the key hash for U-Boot here if public/private key pair used to
sign U-boot are different from the SRK hash put in the fuse. Example
of a key hash is
41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
Otherwise leave this empty.
if PPC
config BOOTSCRIPT_COPY_RAM
bool "Secure boot copies boot script to RAM"
help
On systems that support chain of trust booting, a number of addresses
are required to set variables that are used in the copying and then
verification of different parts of the system. If enabled, the subsequent
options are for what location to use in each step.
config BS_ADDR_DEVICE
hex "Address in RAM for bs_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_SIZE
hex "The size of bs_size which is the amount read from bs_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_ADDR_RAM
hex "Address in RAM for bs_ram"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_ADDR_DEVICE
hex "Address in RAM for bs_hdr_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_SIZE
hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
depends on BOOTSCRIPT_COPY_RAM
config BS_HDR_ADDR_RAM
hex "Address in RAM for bs_hdr_ram"
depends on BOOTSCRIPT_COPY_RAM
config BOOTSCRIPT_HDR_ADDR
hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
endif
config SYS_FSL_SRK_LE
def_bool y
depends on ARM
config KEY_REVOCATION
def_bool y
endmenu
comment "Other functionality shared between NXP SoCs"
config DEEP_SLEEP
bool "Enable SoC deep sleep feature"
depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
default y
help
Indicates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
config LAYERSCAPE_NS_ACCESS
bool "Layerscape non-secure access support"
depends on ARCH_LS1021A || FSL_LSCH2
config PCIE1
bool "PCIe controller #1"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE2
bool "PCIe controller #2"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE3
bool "PCIe controller #3"
depends on LAYERSCAPE_NS_ACCESS || PPC
config PCIE4
bool "PCIe controller #4"
depends on LAYERSCAPE_NS_ACCESS || PPC
config FSL_USE_PCA9547_MUX
bool "Enable PCA9547 I2C Mux on Freescale boards"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
help
This option enables the PCA9547 I2C mux on Freescale boards.
config VID
bool "Enable Freescale VID"
depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
help
This option enables setting core voltage based on individual
values saved in SoC fuses.
config SPL_VID
bool "Enable Freescale VID in SPL"
depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
help
This option enables setting core voltage based on individual
values saved in SoC fuses, in SPL.
if VID || SPL_VID
config VID_FLS_ENV
string "Environment variable for overriding VDD"
help
This option allows for specifying the environment variable
to check to override VDD information.
config VOL_MONITOR_INA220
bool "Enable the INA220 voltage monitor read"
help
This option enables INA220 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_READ
bool "Enable the IR36021 voltage monitor read"
help
This option enables IR36021 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_IR36021_SET
bool "Enable the IR36021 voltage monitor set"
help
This option enables IR36021 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_READ
bool "Enable the LTC3882 voltage monitor read"
help
This option enables LTC3882 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
bool "Enable the LTC3882 voltage monitor set"
help
This option enables LTC3882 voltage monitor set
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_READ
bool "Enable the ISL68233 voltage monitor read"
help
This option enables ISL68233 voltage monitor read
functionality. It is used by the common VID driver.
config VOL_MONITOR_ISL68233_SET
bool "Enable the ISL68233 voltage monitor set"
help
This option enables ISL68233 voltage monitor set
functionality. It is used by the common VID driver.
endif
config FSL_QIXIS
bool "Enable QIXIS support"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
config QIXIS_I2C_ACCESS
bool "Access to QIXIS is over i2c"
depends on FSL_QIXIS
default y
config HAS_FSL_DR_USB
def_bool y
depends on USB_EHCI_HCD && PPC

4
arch/arc/cpu/u-boot.lds
View File

@ -39,8 +39,8 @@ SECTIONS
}
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);

2
arch/arc/include/asm/config.h
View File

@ -6,6 +6,4 @@
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif /*__ASM_ARC_CONFIG_H_ */

3
arch/arc/lib/start.S
View File

@ -7,6 +7,7 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/arcregs.h>
#include <system-constants.h>
ENTRY(_start)
/* Setup interrupt vector base that matches "__text_start" */
@ -86,7 +87,7 @@ ENTRY(_start)
#endif
/* Establish C runtime stack and frame */
mov %sp, CONFIG_SYS_INIT_SP_ADDR
mov %sp, SYS_INIT_SP_ADDR
mov %fp, %sp
/* Allocate reserved area from current top of stack */

62
arch/arm/Kconfig
View File

@ -330,20 +330,6 @@ config CPU_V7R
select SYS_ARM_MPU
select SYS_CACHE_SHIFT_6
config CPU_PXA
bool
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
config CPU_PXA27X
bool
select CPU_PXA
config CPU_SA1100
bool
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
config SYS_CPU
default "arm720t" if CPU_ARM720T
default "arm920t" if CPU_ARM920T
@ -354,8 +340,6 @@ config SYS_CPU
default "armv7" if CPU_V7A
default "armv7" if CPU_V7R
default "armv7m" if CPU_V7M
default "pxa" if CPU_PXA
default "sa1100" if CPU_SA1100
default "armv8" if ARM64
config SYS_ARM_ARCH
@ -369,14 +353,11 @@ config SYS_ARM_ARCH
default 7 if CPU_V7A
default 7 if CPU_V7M
default 7 if CPU_V7R
default 5 if CPU_PXA
default 4 if CPU_SA1100
default 8 if ARM64
choice
prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
CPU_PXA || RZA1
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
default SYS_ARM_CACHE_WRITEBACK
config SYS_ARM_CACHE_WRITEBACK
@ -609,6 +590,9 @@ config ARM64_SUPPORT_AARCH32
help
This ARM64 system supports AArch32 execution state.
config S5P
def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
choice
prompt "Target select"
default TARGET_HIKEY
@ -718,6 +702,11 @@ config ARCH_BCMSTB
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
config ARCH_BCMBCA
bool "Broadcom broadband chip family"
select DM
select OF_CONTROL
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
@ -991,11 +980,6 @@ config ARCH_MX6
imply SYS_THUMB_BUILD
imply SPL_SEPARATE_BSS
if ARCH_MX6
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
endif
config ARCH_MX5
bool "Freescale MX5"
select BOARD_EARLY_INIT_F
@ -1116,7 +1100,6 @@ config ARCH_SOCFPGA
select SPL_DM_SERIAL
select SPL_LIBCOMMON_SUPPORT
select SPL_LIBGENERIC_SUPPORT
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_SERIAL
@ -1347,6 +1330,12 @@ config ARCH_VEXPRESS64
select ENV_IS_IN_FLASH if MTD
imply DISTRO_DEFAULTS
config TARGET_CORSTONE1000
bool "Support Corstone1000 Platform"
select ARM64
select PL01X_SERIAL
select DM
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
select ARM64
@ -1923,7 +1912,7 @@ config ARCH_STM32
imply CMD_DM
config ARCH_STI
bool "Support STMicrolectronics SoCs"
bool "Support STMicroelectronics SoCs"
select BLK
select CPU_V7A
select DM
@ -1951,7 +1940,6 @@ config ARCH_STM32MP
select OF_SYSTEM_SETUP
select PINCTRL
select REGMAP
select SUPPORT_SPL
select SYSCON
select SYSRESET
select SYS_THUMB_BUILD
@ -2085,6 +2073,12 @@ config TARGET_XENGUEST_ARM64
select SSCANF
imply OF_HAS_PRIOR_STAGE
config ARCH_GXP
bool "Support HPE GXP SoCs"
select DM
select OF_CONTROL
imply CMD_DM
endchoice
config SUPPORT_PASSING_ATAGS
@ -2187,12 +2181,16 @@ source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcm283x/Kconfig"
source "arch/arm/mach-bcmbca/Kconfig"
source "arch/arm/mach-bcmstb/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
source "arch/arm/mach-exynos/Kconfig"
source "arch/arm/mach-hpe/gxp/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
@ -2294,7 +2292,7 @@ source "arch/arm/mach-nexell/Kconfig"
source "arch/arm/mach-npcm/Kconfig"
source "board/armltd/total_compute/Kconfig"
source "board/armltd/corstone1000/Kconfig"
source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/Marvell/octeontx/Kconfig"
@ -2334,6 +2332,7 @@ source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/kontron/sl28/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/siemens/common/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig"
source "board/st/stv0991/Kconfig"
@ -2348,8 +2347,3 @@ source "board/xen/xenguest_arm64/Kconfig"
source "arch/arm/Kconfig.debug"
endmenu
config SPL_LDSCRIPT
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64

10
arch/arm/Makefile
View File

@ -10,8 +10,6 @@ arch-$(CONFIG_CPU_ARM720T) =-march=armv4
arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5t
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
@ -40,8 +38,6 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM920T) =
tune-$(CONFIG_CPU_ARM926EJS) =
tune-$(CONFIG_CPU_ARM946ES) =
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
tune-$(CONFIG_CPU_ARM1136) =
tune-$(CONFIG_CPU_ARM1176) =
tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a
@ -59,9 +55,11 @@ machine-$(CONFIG_ARCH_APPLE) += apple
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
machine-$(CONFIG_ARCH_BCMBCA) += bcmbca
machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GXP) += hpe
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx
machine-$(CONFIG_ARCH_K3) += k3
@ -103,8 +101,8 @@ libs-y += $(machdirs)
head-y := arch/arm/cpu/$(CPU)/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
ifneq ($(CONFIG_SPL_START_S_PATH),)
head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
head-y := arch/arm/cpu/arm926ejs/mxs/start.o
endif
endif

4
arch/arm/config.mk
View File

@ -141,11 +141,11 @@ endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j __u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j .binman_sym_table -j .text_rest
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
-j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \
-j .binman_sym_table -j .text_rest
endif

3
arch/arm/cpu/arm926ejs/mxs/start.S
View File

@ -21,6 +21,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <system-constants.h>
/*
*************************************************************************
@ -44,7 +45,7 @@ reset:
* it point to the end of OCRAM if the SP is zero.
*/
cmp sp, #0x00000000
ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
ldreq sp, =SYS_INIT_SP_ADDR
/*
* Store all registers on old stack pointer, this will allow us later to

4
arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
View File

@ -29,8 +29,8 @@ SECTIONS
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
} > .sram
. = ALIGN(4);

3
arch/arm/cpu/armv7/lowlevel_init.S
View File

@ -13,6 +13,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <system-constants.h>
.pushsection .text.s_init, "ax"
WEAK(s_init)
@ -28,7 +29,7 @@ WEAK(lowlevel_init)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =CONFIG_SPL_STACK
#else
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
ldr sp, =SYS_INIT_SP_ADDR
#endif
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_SPL_DM

6
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -41,12 +41,6 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config NXP_ESBC
bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400

3
arch/arm/cpu/armv7/s5p-common/Makefile
View File

@ -3,14 +3,13 @@
# Copyright (C) 2009 Samsung Electronics
# Minkyu Kang <mk7.kang@samsung.com>
obj-$(CONFIG_PWM_S5P) += pwm.o
ifdef CONFIG_ARCH_NEXELL
obj-$(CONFIG_PWM_NX) += pwm.o
obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o
else
obj-y += cpu_info.o
ifndef CONFIG_SPL_BUILD
obj-y += timer.o
obj-y += sromc.o
obj-$(CONFIG_PWM) += pwm.o
endif
endif

3
arch/arm/cpu/armv7/start.S
View File

@ -17,6 +17,7 @@
#include <asm/system.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <system-constants.h>
/*************************************************************************
*
@ -254,7 +255,7 @@ ENTRY(cpu_init_cp15)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
ldr r0, =(SYS_INIT_SP_ADDR)
#endif
bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
mov sp, r0

2
arch/arm/cpu/armv7/stv0991/lowlevel.S
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014 stmicroelectronics
* (C) Copyright 2014 STMicroelectronics
*/
#include <config.h>

4
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
View File

@ -38,8 +38,8 @@ SECTIONS
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
} > .sram
. = ALIGN(4);

17
arch/arm/cpu/armv8/Kconfig
View File

@ -76,6 +76,7 @@ config ARMV8_SEC_FIRMWARE_SUPPORT
config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support for SPL"
depends on SPL
select SPL_FIT
select SPL_OF_LIBFDT
help
@ -83,6 +84,7 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
config SPL_RECOVER_DATA_SECTION
bool "save/restore SPL data section"
depends on SPL
help
Say Y here to save SPL data section for cold boot, and restore
at warm boot in SPL phase.
@ -185,4 +187,19 @@ config ARMV8_EA_EL3_FIRST
Exception handling at all exception levels for External Abort and
SError interrupt exception are taken in EL3.
menuconfig ARMV8_CRYPTO
bool "ARM64 Accelerated Cryptographic Algorithms"
if ARMV8_CRYPTO
config ARMV8_CE_SHA1
bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
default y if SHA1
config ARMV8_CE_SHA256
bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"
default y if SHA256
endif
endif

2
arch/arm/cpu/armv8/Makefile
View File

@ -44,3 +44,5 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
obj-$(CONFIG_XEN) += xen/
obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o

18
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -26,6 +26,7 @@ config ARCH_LS1012A
config ARCH_LS1028A
bool
select ARMV8_SET_SMPEN
select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
@ -138,6 +139,7 @@ config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
@ -187,6 +189,7 @@ config ARCH_LS2080A
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
@ -239,6 +242,7 @@ config ARCH_LS2080A
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
@ -277,6 +281,7 @@ config ARCH_LX2162A
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE
select FSL_LAYERSCAPE
@ -456,11 +461,6 @@ config EMC2305
Enable the EMC2305 fan controller for configuration of fan
speed.
config NXP_ESBC
bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature
config QSPI_AHB_INIT
bool "Init the QSPI AHB bus"
help
@ -511,6 +511,11 @@ config DP_DDR_CTRL
depends on SYS_FSL_HAS_DP_DDR
default 2 if ARCH_LS2080A
config DP_DDR_DIMM_SLOTS_PER_CTLR
int
depends on SYS_FSL_HAS_DP_DDR
default 1 if ARCH_LS2080A
config DP_DDR_NUM_CTRLS
int
depends on SYS_FSL_HAS_DP_DDR
@ -701,9 +706,6 @@ config SYS_FSL_HAS_RGMII
bool
depends on SYS_FSL_EC1 || SYS_FSL_EC2
config SPL_LDSCRIPT
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
config HAS_FSL_XHCI_USB
bool
help

10
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -29,8 +29,8 @@ void get_sys_info(struct sys_info *sys_info)
* mux 2 clock for LS1043A/LS1046A.
*/
#if defined(CONFIG_SYS_DPAA_FMAN) || \
defined(CONFIG_TARGET_LS1046ARDB) || \
defined(CONFIG_TARGET_LS1043ARDB)
defined(CONFIG_ARCH_LS1046A) || \
defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@ -129,13 +129,13 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
#if defined(CONFIG_ARCH_LS1046A) || defined(CONFIG_ARCH_LS1043A)
rcw_tmp = in_be32(&gur->rcwsr[15]);
switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
case 1:
sys_info->freq_cga_m2 = freq_c_pll[1];
break;
#if defined(CONFIG_TARGET_LS1046ARDB)
#if defined(CONFIG_ARCH_LS1046A)
case 2:
sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
break;
@ -143,7 +143,7 @@ void get_sys_info(struct sys_info *sys_info)
case 3:
sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
break;
#if defined(CONFIG_TARGET_LS1046ARDB)
#if defined(CONFIG_ARCH_LS1046A)
case 6:
sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
break;

132
arch/arm/cpu/armv8/sha1_ce_core.S Normal file
View File

@ -0,0 +1,132 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* sha1_ce_core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
*
* Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
* Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/macro.h>
.text
.arch armv8-a+crypto
k0 .req v0
k1 .req v1
k2 .req v2
k3 .req v3
t0 .req v4
t1 .req v5
dga .req q6
dgav .req v6
dgb .req s7
dgbv .req v7
dg0q .req q12
dg0s .req s12
dg0v .req v12
dg1s .req s13
dg1v .req v13
dg2s .req s14
.macro add_only, op, ev, rc, s0, dg1
.ifc \ev, ev
add t1.4s, v\s0\().4s, \rc\().4s
sha1h dg2s, dg0s
.ifnb \dg1
sha1\op dg0q, \dg1, t0.4s
.else
sha1\op dg0q, dg1s, t0.4s
.endif
.else
.ifnb \s0
add t0.4s, v\s0\().4s, \rc\().4s
.endif
sha1h dg1s, dg0s
sha1\op dg0q, dg2s, t1.4s
.endif
.endm
.macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
add_only \op, \ev, \rc, \s1, \dg1
sha1su1 v\s0\().4s, v\s3\().4s
.endm
.macro loadrc, k, val, tmp
movz \tmp, :abs_g0_nc:\val
movk \tmp, :abs_g1:\val
dup \k, \tmp
.endm
/*
* void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
* uint32_t blocks)
*/
ENTRY(sha1_armv8_ce_process)
/* load round constants */
loadrc k0.4s, 0x5a827999, w6
loadrc k1.4s, 0x6ed9eba1, w6
loadrc k2.4s, 0x8f1bbcdc, w6
loadrc k3.4s, 0xca62c1d6, w6
/* load state (4+1 digest states) */
ld1 {dgav.4s}, [x0]
ldr dgb, [x0, #16]
/* load input (64 bytes into v8->v11 16B vectors) */
0: ld1 {v8.4s-v11.4s}, [x1], #64
sub w2, w2, #1
#if __BYTE_ORDER == __LITTLE_ENDIAN
rev32 v8.16b, v8.16b
rev32 v9.16b, v9.16b
rev32 v10.16b, v10.16b
rev32 v11.16b, v11.16b
#endif
1: add t0.4s, v8.4s, k0.4s
mov dg0v.16b, dgav.16b
add_update c, ev, k0, 8, 9, 10, 11, dgb
add_update c, od, k0, 9, 10, 11, 8
add_update c, ev, k0, 10, 11, 8, 9
add_update c, od, k0, 11, 8, 9, 10
add_update c, ev, k1, 8, 9, 10, 11
add_update p, od, k1, 9, 10, 11, 8
add_update p, ev, k1, 10, 11, 8, 9
add_update p, od, k1, 11, 8, 9, 10
add_update p, ev, k1, 8, 9, 10, 11
add_update p, od, k2, 9, 10, 11, 8
add_update m, ev, k2, 10, 11, 8, 9
add_update m, od, k2, 11, 8, 9, 10
add_update m, ev, k2, 8, 9, 10, 11
add_update m, od, k2, 9, 10, 11, 8
add_update m, ev, k3, 10, 11, 8, 9
add_update p, od, k3, 11, 8, 9, 10
add_only p, ev, k3, 9
add_only p, od, k3, 10
add_only p, ev, k3, 11
add_only p, od
/* update state */
add dgbv.2s, dgbv.2s, dg1v.2s
add dgav.4s, dgav.4s, dg0v.4s
/* loop on next block? */
cbz w2, 2f
b 0b
/* store new state */
2: st1 {dgav.4s}, [x0]
str dgb, [x0, #16]
mov w0, w2
ret
ENDPROC(sha1_armv8_ce_process)

21
arch/arm/cpu/armv8/sha1_ce_glue.c Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* sha1_ce_glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions
*
* Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
*/
#include <common.h>
#include <u-boot/sha1.h>
extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
uint32_t blocks);
void sha1_process(sha1_context *ctx, const unsigned char *data,
unsigned int blocks)
{
if (!blocks)
return;
sha1_armv8_ce_process(ctx->state, data, blocks);
}

134
arch/arm/cpu/armv8/sha256_ce_core.S Normal file
View File

@ -0,0 +1,134 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* sha256-ce-core.S - core SHA-256 transform using v8 Crypto Extensions
*
* Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
* Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/macro.h>
.text
.arch armv8-a+crypto
dga .req q20
dgav .req v20
dgb .req q21
dgbv .req v21
t0 .req v22
t1 .req v23
dg0q .req q24
dg0v .req v24
dg1q .req q25
dg1v .req v25
dg2q .req q26
dg2v .req v26
.macro add_only, ev, rc, s0
mov dg2v.16b, dg0v.16b
.ifeq \ev
add t1.4s, v\s0\().4s, \rc\().4s
sha256h dg0q, dg1q, t0.4s
sha256h2 dg1q, dg2q, t0.4s
.else
.ifnb \s0
add t0.4s, v\s0\().4s, \rc\().4s
.endif
sha256h dg0q, dg1q, t1.4s
sha256h2 dg1q, dg2q, t1.4s
.endif
.endm
.macro add_update, ev, rc, s0, s1, s2, s3
sha256su0 v\s0\().4s, v\s1\().4s
add_only \ev, \rc, \s1
sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
.endm
/*
* The SHA-256 round constants
*/
.align 4
.Lsha2_rcon:
.word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
.word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
.word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
.word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
.word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
.word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
.word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
.word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
.word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
.word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
.word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
.word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
.word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
.word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
.word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
.word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
/*
* void sha256_armv8_ce_process(struct sha256_ce_state *sst,
* uint8_t const *src, uint32_t blocks)
*/
ENTRY(sha256_armv8_ce_process)
/* load round constants */
adr x8, .Lsha2_rcon
ld1 { v0.4s- v3.4s}, [x8], #64
ld1 { v4.4s- v7.4s}, [x8], #64
ld1 { v8.4s-v11.4s}, [x8], #64
ld1 {v12.4s-v15.4s}, [x8]
/* load state */
ldp dga, dgb, [x0]
/* load input */
0: ld1 {v16.4s-v19.4s}, [x1], #64
sub w2, w2, #1
#if __BYTE_ORDER == __LITTLE_ENDIAN
rev32 v16.16b, v16.16b
rev32 v17.16b, v17.16b
rev32 v18.16b, v18.16b
rev32 v19.16b, v19.16b
#endif
1: add t0.4s, v16.4s, v0.4s
mov dg0v.16b, dgav.16b
mov dg1v.16b, dgbv.16b
add_update 0, v1, 16, 17, 18, 19
add_update 1, v2, 17, 18, 19, 16
add_update 0, v3, 18, 19, 16, 17
add_update 1, v4, 19, 16, 17, 18
add_update 0, v5, 16, 17, 18, 19
add_update 1, v6, 17, 18, 19, 16
add_update 0, v7, 18, 19, 16, 17
add_update 1, v8, 19, 16, 17, 18
add_update 0, v9, 16, 17, 18, 19
add_update 1, v10, 17, 18, 19, 16
add_update 0, v11, 18, 19, 16, 17
add_update 1, v12, 19, 16, 17, 18
add_only 0, v13, 17
add_only 1, v14, 18
add_only 0, v15, 19
add_only 1
/* update state */
add dgav.4s, dgav.4s, dg0v.4s
add dgbv.4s, dgbv.4s, dg1v.4s
/* handled all input blocks? */
cbnz w2, 0b
/* store new state */
3: stp dga, dgb, [x0]
ret
ENDPROC(sha256_armv8_ce_process)

21
arch/arm/cpu/armv8/sha256_ce_glue.c Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* sha256_ce_glue.c - SHA-256 secure hash using ARMv8 Crypto Extensions
*
* Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
*/
#include <common.h>
#include <u-boot/sha256.h>
extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src,
uint32_t blocks);
void sha256_process(sha256_context *ctx, const unsigned char *data,
unsigned int blocks)
{
if (!blocks)
return;
sha256_armv8_ce_process(ctx->state, data, blocks);
}

6
arch/arm/cpu/armv8/u-boot-spl.lds
View File

@ -23,7 +23,7 @@ SECTIONS
{
.text : {
. = ALIGN(8);
*(.__image_copy_start)
__image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
@ -46,9 +46,9 @@ SECTIONS
} >.sram
#endif
.u_boot_list : {
__u_boot_list : {
. = ALIGN(8);
KEEP(*(SORT(.u_boot_list*)));
KEEP(*(SORT(__u_boot_list*)));
} >.sram
.image_copy_end : {

4
arch/arm/cpu/armv8/u-boot.lds
View File

@ -109,8 +109,8 @@ SECTIONS
. = .;
. = ALIGN(8);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(8);

15
arch/arm/cpu/pxa/Makefile
View File

@ -1,15 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
extra-y = start.o
obj-$(CONFIG_CPU_PXA25X) += pxa2xx.o
obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o
obj-y += cpuinfo.o
obj-y += timer.o
obj-y += usb.o
obj-y += relocate.o
obj-y += cache.o

58
arch/arm/cpu/pxa/cache.c
View File

@ -1,58 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/types.h>
#include <common.h>
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
/* Flush/Invalidate D cache */
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
}
void flush_dcache_all(void)
{
return invalidate_dcache_all();
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
while (start <= stop) {
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
return invalidate_dcache_range(start, stop);
}
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
*/
__weak void l2_cache_disable(void) {}
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
__weak void invalidate_l2_cache(void) {}
#endif

18
arch/arm/cpu/pxa/config.mk
View File

@ -1,18 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# !WARNING!
# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
# really small OneNAND memories where the mmap'd window is only 1KiB big. The
# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
# they are not discarded.
#
#ifdef CONFIG_SPL_BUILD
OBJCOPYFLAGS += -j .text.0 -j .text.1
#endif

145
arch/arm/cpu/pxa/cpuinfo.c
View File

@ -1,145 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PXA CPU information display
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <errno.h>
#include <linux/compiler.h>
#ifdef CONFIG_CPU_PXA25X
#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
#error "Init SP address must be set to 0xfffff800 for PXA250"
#endif
#endif
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f
#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
#define CPU_VALUE_PXA25X 0x100
#define CPU_VALUE_PXA27X 0x110
static uint32_t pxa_get_cpuid(void)
{
uint32_t cpuid;
asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
return cpuid;
}
int cpu_is_pxa25x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA25X;
}
int cpu_is_pxa27x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA27X;
}
int cpu_is_pxa27xm(void)
{
uint32_t id = pxa_get_cpuid();
return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) &&
((id & CPU_MASK_PXA_REVID) == 8);
}
uint32_t pxa_get_cpu_revision(void)
{
return pxa_get_cpuid() & CPU_MASK_PRODREV;
}
#ifdef CONFIG_DISPLAY_CPUINFO
static const char *pxa25x_get_revision(void)
{
static __maybe_unused const char * const revs_25x[] = { "A0" };
static __maybe_unused const char * const revs_26x[] = {
"A0", "B0", "B1"
};
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa25x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
#ifdef CONFIG_CPU_PXA26X
switch (id) {
case 3: return revs_26x[0];
case 5: return revs_26x[1];
case 6: return revs_26x[2];
}
#else
if (id == 6)
return revs_25x[0];
#endif
return unknown;
}
static const char *pxa27x_get_revision(void)
{
static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa27x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
if ((id == 5) || (id == 6) || (id > 8))
return unknown;
/* Cap the special PXA270 C5 case. */
if (id == 7)
id = 5;
/* Cap the special PXA270M A1 case. */
if (id == 8)
id = 1;
return rev[id];
}
static int print_cpuinfo_pxa2xx(void)
{
if (cpu_is_pxa25x()) {
puts("Marvell PXA25x rev. ");
puts(pxa25x_get_revision());
} else if (cpu_is_pxa27x()) {
puts("Marvell PXA27x");
if (cpu_is_pxa27xm()) puts("M");
puts(" rev. ");
puts(pxa27x_get_revision());
} else
return -EINVAL;
puts("\n");
return 0;
}
int print_cpuinfo(void)
{
int ret;
puts("CPU: ");
ret = print_cpuinfo_pxa2xx();
if (!ret)
return ret;
return ret;
}
#endif

295
arch/arm/cpu/pxa/pxa2xx.c
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@ -1,295 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <irq_func.h>
#include <asm/arch/pxa-regs.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <command.h>
/* Flush I/D-cache */
static void cache_flush(void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
}
int cleanup_before_linux(void)
{
/*
* This function is called just before we call Linux. It prepares
* the processor for Linux by just disabling everything that can
* disturb booting Linux.
*/
disable_interrupts();
icache_disable();
dcache_disable();
cache_flush();
return 0;
}
inline void writelrb(uint32_t val, uint32_t addr)
{
writel(val, addr);
asm volatile("" : : : "memory");
readl(addr);
asm volatile("" : : : "memory");
}
void pxa2xx_dram_init(void)
{
uint32_t tmp;
int i;
/*
* 1) Initialize Asynchronous static memory controller
*/
writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
/*
* 2) Initialize Card Interface
*/
/* MECR: Memory Expansion Card Register */
writelrb(CONFIG_SYS_MECR_VAL, MECR);
/* MCMEM0: Card Interface slot 0 timing */
writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
/* MCMEM1: Card Interface slot 1 timing */
writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
/*
* 3) Configure Fly-By DMA register
*/
writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
/*
* 4) Initialize Timing for Sync Memory (SDCLK0)
*/
/*
* Before accessing MDREFR we need a valid DRI field, so we set
* this to power on defaults + DRI field.
*/
/* Read current MDREFR config and zero out DRI */
tmp = readl(MDREFR) & ~0xfff;
/* Add user-specified DRI */
tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
/* Configure important bits */
tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
/* Write MDREFR back */
writelrb(tmp, MDREFR);
/*
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
*/
/* Initialize SXCNFG register. Assert the enable bits.
*
* Write SXMRS to cause an MRS command to all enabled banks of
* synchronous static memory. Note that SXLCR need not be written
* at this time.
*/
writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
/*
* 6) Initialize SDRAM
*/
writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
/*
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
* but not enable each SDRAM partition pair.
*/
writelrb(CONFIG_SYS_MDCNFG_VAL &
~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
writel(0, OSCR);
while (readl(OSCR) < 0x300)
asm volatile("" : : : "memory");
/*
* 8) Trigger a number (usually 8) refresh cycles by attempting
* non-burst read or write accesses to disabled SDRAM, as commonly
* specified in the power up sequence documented in SDRAM data
* sheets. The address(es) used for this purpose must not be
* cacheable.
*/
for (i = 9; i >= 0; i--) {
writel(i, 0xa0000000);
asm volatile("" : : : "memory");
}
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
*/
tmp = CONFIG_SYS_MDCNFG_VAL &
(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
tmp |= readl(MDCNFG);
writelrb(tmp, MDCNFG);
/*
* 10) Write MDMRS.
*/
writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
/*
* 11) Enable APD
*/
if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
tmp = readl(MDREFR);
tmp |= MDREFR_APD;
writelrb(tmp, MDREFR);
}
}
void pxa_gpio_setup(void)
{
writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
#endif
writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
#endif
writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
#endif
writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
#endif
writel(CONFIG_SYS_PSSR_VAL, PSSR);
}
void pxa_interrupt_setup(void)
{
writel(0, ICLR);
writel(0, ICMR);
#if defined(CONFIG_CPU_PXA27X)
writel(0, ICLR2);
writel(0, ICMR2);
#endif
}
void pxa_clock_setup(void)
{
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
while (!(readl(OSCC) & OSCC_OOK))
asm volatile("" : : : "memory");
}
void pxa_wakeup(void)
{
uint32_t rcsr;
rcsr = readl(RCSR);
writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
/* Wakeup */
if (rcsr & RCSR_SMR) {
writel(PSSR_PH, PSSR);
pxa2xx_dram_init();
icache_disable();
dcache_disable();
asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
}
}
int arch_cpu_init(void)
{
pxa_gpio_setup();
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();
return 0;
}
void i2c_clk_enable(void)
{
/* Set the global I2C clock on */
writel(readl(CKEN) | CKEN14_I2C, CKEN);
}
void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
void reset_cpu(void)
{
uint32_t tmp;
setbits_le32(OWER, OWER_WME);
tmp = readl(OSCR);
tmp += 0x1000;
writel(tmp, OSMR3);
writel(MDREFR_SLFRSH, MDREFR);
for (;;)
;
}
void enable_caches(void)
{
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

22
arch/arm/cpu/pxa/relocate.S
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - PXA270 vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The PXA SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

205
arch/arm/cpu/pxa/start.S
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@ -1,205 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for XScale CPU-core
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (C) 2003 Kshitij <kshitij@ti.com>
* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
#ifdef CONFIG_CPU_PXA25X
bl lock_cache_for_stack
#endif
#ifdef CONFIG_CPU_PXA27X
/*
* enable clock for SRAM
*/
ldr r0,=CKEN
ldr r1,[r0]
orr r1,r1,#(1 << 20)
str r1,[r0]
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
#ifdef CONFIG_CPU_PXA25X
/*
* Unlock (actually, disable) the cache now that board_init_f
* is done. We could do this earlier but we would need to add
* a new C runtime hook, whereas c_runtime_cpu_setup already
* exists.
* As this routine is just a call to cpu_init_crit, let us
* tail-optimize and do a simple branch here.
*/
b cpu_init_crit
#else
bx lr
#endif
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
/*
* Enable MMU to use DCache as DRAM.
*
* This is useful on PXA25x and PXA26x in early bootstages, where there is no
* other possible memory available to hold stack.
*/
#ifdef CONFIG_CPU_PXA25X
.macro CPWAIT reg
mrc p15, 0, \reg, c2, c0, 0
mov \reg, \reg
sub pc, pc, #4
.endm
lock_cache_for_stack:
/* Domain access -- enable for all CPs */
ldr r0, =0x0000ffff
mcr p15, 0, r0, c3, c0, 0
/* Point TTBR to MMU table */
ldr r0, =mmutable
mcr p15, 0, r0, c2, c0, 0
/* Kick in MMU, ICache, DCache, BTB */
mrc p15, 0, r0, c1, c0, 0
bic r0, #0x1b00
bic r0, #0x0087
orr r0, #0x1800
orr r0, #0x0005
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
/* Unlock Icache, Dcache */
mcr p15, 0, r0, c9, c1, 1
mcr p15, 0, r0, c9, c2, 1
/* Flush Icache, Dcache, BTB */
mcr p15, 0, r0, c7, c7, 0
/* Unlock I-TLB, D-TLB */
mcr p15, 0, r0, c10, c4, 1
mcr p15, 0, r0, c10, c8, 1
/* Flush TLB */
mcr p15, 0, r0, c8, c7, 0
/* Allocate 4096 bytes of Dcache as RAM */
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r4, #0x00
mov r5, #0x00
mov r2, #0x01
mcr p15, 0, r0, c9, c2, 0
CPWAIT r0
/* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
mov r0, #128
ldr r1, =0xfffff000
alloc:
mcr p15, 0, r1, c7, c2, 5
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
strd r4, [r1], #8
subs r0, #0x01
bne alloc
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
mov r2, #0x00
mcr p15, 0, r2, c9, c2, 0
CPWAIT r0
mov pc, lr
.section .mmutable, "a"
mmutable:
.align 14
/* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
.set __base, 0
.rept 0xfff
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
/* 0xfff00000 : 1:1, cached mapping */
.word (0xfff << 20) | 0x1c1e
#endif /* CONFIG_CPU_PXA25X */

16
arch/arm/cpu/pxa/timer.c
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@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Marvell PXA2xx/3xx timer driver
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
int timer_init(void)
{
writel(0, CONFIG_SYS_TIMER_COUNTER);
return 0;
}

89
arch/arm/cpu/pxa/usb.c
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@ -1,89 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2006
* Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
*/
#include <common.h>
#include <linux/delay.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <usb.h>
int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
#if defined(CONFIG_CPU_PXA27X)
/* Enable USB host clock. */
writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
#if defined(CONFIG_CPU_MONAHANS)
/* Configure Port 2 for Host (USB Client Registers) */
writel(0x3000c, UP2OCR);
#endif
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
mdelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (readl(UHCHR) & UHCHR_FSBIR)
udelay(1);
#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
return 0;
}
int usb_cpu_stop(void)
{
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
udelay(10);
#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
#if defined(CONFIG_CPU_MONAHANS)
/* Disable USB host clock. */
writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
udelay(100);
#endif
#if defined(CONFIG_CPU_PXA27X)
/* Disable USB host clock. */
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
return 0;
}
int usb_cpu_init_fail(void)
{
return usb_cpu_stop();
}
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

9
arch/arm/cpu/sa1100/Makefile
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@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
extra-y = start.o
obj-y += cpu.o
obj-y += timer.o

65
arch/arm/cpu/sa1100/cpu.c
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@ -1,65 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*/
/*
* CPU specific code
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/system.h>
#include <asm/io.h>
static void cache_flush(void);
int cleanup_before_linux (void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* just disable everything that can disturb booting linux
*/
disable_interrupts();
/* turn off I-cache */
icache_disable();
dcache_disable();
/* flush I-cache */
cache_flush();
return (0);
}
/* flush I/D-cache */
static void cache_flush (void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
#define RST_BASE 0x90030000
#define RSRR 0x00
#define RCSR 0x04
__attribute__((noreturn)) void reset_cpu(void)
{
/* repeat endlessly */
while (1) {
writel(0, RST_BASE + RCSR);
writel(1, RST_BASE + RSRR);
}
}

126
arch/arm/cpu/sa1100/start.S
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for SA1100 CPU
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
/* Interrupt-Controller base address */
IC_BASE: .word 0x90050000
#define ICMR 0x04
/* Reset-Controller */
RST_BASE: .word 0x90030000
#define RSRR 0x00
#define RCSR 0x04
/* PWR */
PWR_BASE: .word 0x90020000
#define PSPR 0x08
#define PPCR 0x14
cpuspeed: .word CONFIG_SYS_CPUSPEED
cpu_init_crit:
/*
* mask all IRQs
*/
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
/* set clock speed */
ldr r0, PWR_BASE
ldr r1, cpuspeed
str r1, [r0, #PPCR]
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
bl lowlevel_init
mov lr, ip
#endif
/*
* disable MMU stuff and enable I-cache
*/
mrc p15,0,r0,c1,c0
bic r0, r0, #0x00002000 @ clear bit 13 (X)
bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
mcr p15,0,r0,c1,c0
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov pc, lr

66
arch/arm/cpu/sa1100/timer.c
View File

@ -1,66 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*/
#include <common.h>
#include <SA-1100.h>
#include <time.h>
#include <linux/delay.h>
static ulong get_timer_masked (void)
{
return OSCR;
}
ulong get_timer (ulong base)
{
return get_timer_masked ();
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
endtime = get_timer_masked () + tmo;
do {
ulong now = get_timer_masked ();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

4
arch/arm/cpu/u-boot-spl.lds
View File

@ -32,8 +32,8 @@ SECTIONS
}
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);

6
arch/arm/cpu/u-boot.lds
View File

@ -15,7 +15,7 @@ ENTRY(_start)
SECTIONS
{
#ifndef CONFIG_CMDLINE
/DISCARD/ : { *(.u_boot_list_2_cmd_*) }
/DISCARD/ : { *(__u_boot_list_2_cmd_*) }
#endif
#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC)
/*
@ -149,8 +149,8 @@ SECTIONS
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);

28
arch/arm/dts/Makefile
View File

@ -5,9 +5,9 @@ dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb
dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-universal_c210.dtb \
exynos4210-trats.dtb \
@ -19,7 +19,7 @@ dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-spring.dtb \
exynos5250-smdk5250.dtb \
@ -342,6 +342,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-qspi.dtb \
zynqmp-sm-k26-revA.dtb \
zynqmp-smk-k26-revA.dtb \
zynqmp-sck-kr-g-revA.dtbo \
zynqmp-sck-kr-g-revB.dtbo \
zynqmp-sck-kv-g-revA.dtbo \
zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
@ -412,7 +414,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am437x-cm-t43.dtb
dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
@ -1072,6 +1074,8 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
omap3-beagle-xm.dtb \
omap3-beagle.dtb
dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
omap3-igep0020.dtb
@ -1157,11 +1161,17 @@ dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
dtb-$(CONFIG_BCM47622) += \
bcm947622.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13x) += \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15x) += \
stm32mp157a-dk1.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
@ -1199,6 +1209,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-sk.dtb \
k3-am642-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
@ -1239,6 +1252,8 @@ dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_GXP) += hpe-bmc-dl360gen10.dts
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
imx8mm-cl-iot-gate-ied.dtbo \
imx8mm-cl-iot-gate-ied-adc0.dtbo \
@ -1265,6 +1280,9 @@ dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
corstone1000-fvp.dtb
include $(srctree)/scripts/Makefile.dts
targets += $(dtb-y)

23
arch/arm/dts/ast2500-evb.dts
View File

@ -60,6 +60,10 @@
pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
};
&sdmmc {
status = "okay";
};
&sdhci0 {
status = "okay";
@ -73,3 +77,22 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
};
&i2c3 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c7 {
status = "okay";
lm75@4d {
compatible = "national,lm75";
reg = <0x4d>;
};
};

25
arch/arm/dts/ast2500-u-boot.dtsi
View File

@ -28,31 +28,6 @@
clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst ASPEED_RESET_SDRAM>;
};
ahb {
u-boot,dm-pre-reloc;
apb {
u-boot,dm-pre-reloc;
sdhci0: sdhci@1e740100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst ASPEED_RESET_SDIO>;
};
sdhci1: sdhci@1e740200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst ASPEED_RESET_SDIO>;
};
};
};
};
&uart1 {

28
arch/arm/dts/ast2500.dtsi
View File

@ -207,6 +207,34 @@
reg = <0x1e720000 0x9000>; // 36K
};
sdmmc: sd-controller@1e740000 {
compatible = "aspeed,ast2500-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x100 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
sdhci1: sdhci@200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x200 0x100>;
interrupts = <26>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
gpio: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;

49
arch/arm/dts/ast2600-evb.dts
View File

@ -15,9 +15,9 @@
};
aliases {
mmc0 = &emmc_slot0;
mmc1 = &sdhci_slot0;
mmc2 = &sdhci_slot1;
mmc0 = &emmc;
mmc1 = &sdhci0;
mmc2 = &sdhci1;
spi0 = &fmc;
spi1 = &spi1;
spi2 = &spi2;
@ -134,53 +134,52 @@
};
};
&emmc {
u-boot,dm-pre-reloc;
timing-phase = <0x700ff>;
&emmc_controller {
status = "okay";
};
&emmc_slot0 {
u-boot,dm-pre-reloc;
status = "okay";
&emmc {
non-removable;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_default>;
sdhci-drive-type = <1>;
max-frequency = <100000000>;
clk-phase-mmc-hs200 = <9>, <225>;
};
&i2c4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
temp@2e {
compatible = "adi,adt7490";
reg = <0x2e>;
};
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c8 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
lm75@4d {
compatible = "national,lm75";
reg = <0x4d>;
};
};
&mdio0 {

123
arch/arm/dts/ast2600.dtsi
View File

@ -416,60 +416,51 @@
status = "disabled";
};
sdhci: sdhci@1e740000 {
#interrupt-cells = <1>;
compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
reg = <0x1e740000 0x1000>;
sdc: sdc@1e740000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e740000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e740000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
status = "disabled";
sdhci0: sdhci@1e740100 {
compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x100 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
<&scu ASPEED_CLK_GATE_SDEXTCLK>;
clock-names = "ctrlclk", "extclk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e740000 0x1000>;
sdhci_slot0: sdhci_slot0@100 {
compatible = "aspeed,sdhci-ast2600";
reg = <0x100 0x100>;
interrupts = <0>;
interrupt-parent = <&sdhci>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
sdhci_slot1: sdhci_slot1@200 {
compatible = "aspeed,sdhci-ast2600";
sdhci1: sdhci@1e740200 {
compatible = "aspeed,ast2600-sdhci", "sdhci";
reg = <0x200 0x100>;
interrupts = <1>;
interrupt-parent = <&sdhci>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
sdhci,auto-cmd12;
clocks = <&scu ASPEED_CLK_SDIO>;
status = "disabled";
};
};
emmc: emmc@1e750000 {
#interrupt-cells = <1>;
compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
reg = <0x1e750000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
<&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
clock-names = "ctrlclk", "extclk";
emmc_controller: sdc@1e750000 {
compatible = "aspeed,ast2600-sd-controller";
reg = <0x1e750000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e750000 0x1000>;
emmc_slot0: emmc_slot0@100 {
compatible = "aspeed,emmc-ast2600";
reg = <0x100 0x100>;
interrupts = <0>;
interrupt-parent = <&emmc>;
clocks = <&scu ASPEED_CLK_EMMC>;
ranges = <0 0x1e750000 0x10000>;
clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>;
status = "disabled";
emmc: sdhci@1e750100 {
compatible = "aspeed,ast2600-sdhci";
reg = <0x100 0x100>;
sdhci,auto-cmd12;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_EMMC>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc_default>;
};
};
@ -832,7 +823,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "disabled";
};
@ -845,7 +839,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_default>;
status = "disabled";
};
@ -858,7 +855,11 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_default>;
status = "disabled";
};
i2c3: i2c@200 {
@ -870,7 +871,11 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_default>;
status = "disabled";
};
i2c4: i2c@280 {
@ -882,7 +887,11 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c5_default>;
status = "disabled";
};
i2c5: i2c@300 {
@ -894,7 +903,11 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6_default>;
status = "disabled";
};
i2c6: i2c@380 {
@ -906,7 +919,11 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_default>;
status = "disabled";
};
i2c7: i2c@400 {
@ -918,7 +935,11 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c8_default>;
status = "disabled";
};
i2c8: i2c@480 {
@ -930,7 +951,11 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c9_default>;
status = "disabled";
};
i2c9: i2c@500 {
@ -942,7 +967,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c10_default>;
status = "disabled";
};
@ -955,7 +983,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c11_default>;
status = "disabled";
};
@ -968,7 +999,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c12_default>;
status = "disabled";
};
@ -981,7 +1015,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c13_default>;
status = "disabled";
};
@ -994,7 +1031,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c14_default>;
status = "disabled";
};
@ -1007,7 +1047,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c15_default>;
status = "disabled";
};
@ -1020,7 +1063,10 @@
compatible = "aspeed,ast2600-i2c-bus";
bus-frequency = <100000>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst ASPEED_RESET_I2C>;
clocks = <&scu ASPEED_CLK_APB2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c16_default>;
status = "disabled";
};
@ -1246,6 +1292,7 @@
function = "I2C1";
groups = "I2C1";
};
pinctrl_i2c2_default: i2c2_default {
function = "I2C2";
groups = "I2C2";

6
arch/arm/dts/at91-sama5d2_icp.dts
View File

@ -68,19 +68,19 @@
status = "okay";
eeprom@50 {
compatible = "microchip,24aa02e48";
compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
reg = <0x50>;
pagesize = <16>;
};
eeprom@52 {
compatible = "microchip,24aa02e48";
compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "microchip,24aa02e48";
compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
reg = <0x53>;
pagesize = <16>;
};

25
arch/arm/dts/at91-sama7g5ek.dts
View File

@ -14,6 +14,7 @@
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/sound/microchip,pdmc.h>
/ {
model = "Microchip SAMA7G5-EK";
@ -404,13 +405,13 @@
status = "okay";
eeprom@52 {
compatible = "microchip,24aa02e48";
compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "microchip,24aa02e48";
compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
reg = <0x53>;
pagesize = <16>;
};
@ -468,7 +469,7 @@
&pinctrl_gmac1_mdio_default
&pinctrl_gmac1_phy_irq>;
phy-mode = "rmii";
status = "okay";
status = "okay"; /* Conflict with pdmc0. */
ethernet-phy@0 {
reg = <0x0>;
@ -482,6 +483,17 @@
pinctrl-0 = <&pinctrl_i2s0_default>;
};
&pdmc0 {
#sound-dai-cells = <0>;
microchip,mic-pos = <MCHP_PDMC_DS0 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 1 */
<MCHP_PDMC_DS1 MCHP_PDMC_CLK_NEGATIVE>, /* MIC 2 */
<MCHP_PDMC_DS0 MCHP_PDMC_CLK_POSITIVE>, /* MIC 3 */
<MCHP_PDMC_DS1 MCHP_PDMC_CLK_POSITIVE>; /* MIC 4 */
status = "disabled"; /* Conflict with gmac1. */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdmc0_default>;
};
&pioA {
pinctrl_can0_default: can0_default {
@ -651,6 +663,13 @@
bias-disable;
};
pinctrl_pdmc0_default: pdmc0_default {
pinmux = <PIN_PD23__PDMC0_DS0>,
<PIN_PD24__PDMC0_DS1>,
<PIN_PD22__PDMC0_CLK>;
bias_disable;
};
pinctrl_qspi: qspi {
pinmux = <PIN_PB12__QSPI0_IO0>,
<PIN_PB11__QSPI0_IO1>,

126
arch/arm/dts/bcm47622.dtsi Normal file
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@ -0,0 +1,126 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm47622", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>, <&CA7_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
cpu_off = <1>;
cpu_on = <2>;
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x818000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

30
arch/arm/dts/bcm947622.dts Normal file
View File

@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm47622.dtsi"
/ {
model = "Broadcom BCM947622 Reference Board";
compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

51
arch/arm/dts/corstone1000-fvp.dts Normal file
View File

@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0 or MIT
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
* Copyright (c) 2022, Linaro Limited. All rights reserved.
*
*/
/dts-v1/;
#include "corstone1000.dtsi"
/ {
model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
compatible = "arm,corstone1000-fvp";
smsc: ethernet@4010000 {
compatible = "smsc,lan91c111";
reg = <0x40100000 0x10000>;
phy-mode = "mii";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <2>;
};
vmmc_v3_3d: fixed_v3_3d {
compatible = "regulator-fixed";
regulator-name = "vmmc_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sdmmc0: mmc@40300000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x40300000 0x1000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <12000000>;
vmmc-supply = <&vmmc_v3_3d>;
clocks = <&smbclk>, <&refclk100mhz>;
clock-names = "smclk", "apb_pclk";
};
sdmmc1: mmc@50000000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x50000000 0x10000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
max-frequency = <12000000>;
vmmc-supply = <&vmmc_v3_3d>;
clocks = <&smbclk>, <&refclk100mhz>;
clock-names = "smclk", "apb_pclk";
};
};

32
arch/arm/dts/corstone1000-mps3.dts Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0 or MIT
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
* Copyright (c) 2022, Linaro Limited. All rights reserved.
*
*/
/dts-v1/;
#include "corstone1000.dtsi"
/ {
model = "ARM Corstone1000 FPGA MPS3 board";
compatible = "arm,corstone1000-mps3";
smsc: ethernet@4010000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x40100000 0x10000>;
phy-mode = "mii";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <2>;
smsc,irq-push-pull;
};
usb_host: usb@40200000 {
compatible = "nxp,usb-isp1763";
reg = <0x40200000 0x100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <16>;
dr_mode = "host";
};
};

164
arch/arm/dts/corstone1000.dtsi Normal file
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@ -0,0 +1,164 @@
// SPDX-License-Identifier: GPL-2.0 or MIT
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
* Copyright (c) 2022, Linaro Limited. All rights reserved.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0>;
next-level-cache = <&L2_0>;
};
};
memory@88200000 {
device_type = "memory";
reg = <0x88200000 0x77e00000>;
};
gic: interrupt-controller@1c000000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1c010000 0x1000>,
<0x1c02f000 0x2000>,
<0x1c04f000 0x1000>,
<0x1c06f000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>;
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>;
};
refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
smbclk: refclk24mhzx2 {
/* Reference 24MHz clock x 2 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "smclk";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>;
};
uartclk: uartclk {
/* UART clock - 50MHz */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "uartclk";
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges;
timer@1a220000 {
compatible = "arm,armv7-timer-mem";
reg = <0x1a220000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
clock-frequency = <50000000>;
ranges;
frame@1a230000 {
frame-number = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1a230000 0x1000>;
};
};
uart0: serial@1a510000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a510000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart1: serial@1a520000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1a520000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
mhu_hse1: mailbox@1b820000 {
compatible = "arm,mhuv2-tx", "arm,primecell";
reg = <0x1b820000 0x1000>;
clocks = <&refclk100mhz>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
arm,mhuv2-protocols = <0 0>;
secure-status = "okay"; /* secure-world-only */
status = "disabled";
};
mhu_seh1: mailbox@1b830000 {
compatible = "arm,mhuv2-rx", "arm,primecell";
reg = <0x1b830000 0x1000>;
clocks = <&refclk100mhz>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
arm,mhuv2-protocols = <0 0>;
secure-status = "okay"; /* secure-world-only */
status = "disabled";
};
};
};

7
arch/arm/dts/fsl-ls1012a.dtsi
View File

@ -34,6 +34,13 @@
#size-cells = <2>;
ranges;
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x1000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1012a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;

7
arch/arm/dts/fsl-ls1043a.dtsi
View File

@ -38,6 +38,13 @@
#size-cells = <2>;
ranges;
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x1000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;

7
arch/arm/dts/fsl-ls1046a.dtsi
View File

@ -38,6 +38,13 @@
#size-cells = <2>;
ranges;
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x1000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1046a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;

26
arch/arm/dts/hpe-bmc-dl360gen10.dts Normal file
View File

@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for HPE DL360Gen10
*/
/include/ "hpe-gxp-u-boot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";
aliases {
serial0 = &uartc;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
};

25
arch/arm/dts/hpe-gxp-u-boot.dtsi Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for HPE GXP
*/
/include/ "hpe-gxp.dtsi"
/ {
axi {
u-boot,dm-pre-reloc;
ahb@c0000000 {
u-boot,dm-pre-reloc;
spi0: spi@200 {
compatible = "hpe,gxp-spi";
reg = <0x200 0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
};
};
};

127
arch/arm/dts/hpe-gxp.dtsi Normal file
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@ -0,0 +1,127 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree file for HPE GXP
*/
/dts-v1/;
/ {
model = "Hewlett Packard Enterprise GXP BMC";
compatible = "hpe,gxp";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L2>;
};
};
clocks {
pll: clock-0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1600000000>;
};
iopclk: clock-1 {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clocks = <&pll>;
};
};
axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges;
L2: cache-controller@b0040000 {
compatible = "arm,pl310-cache";
reg = <0xb0040000 0x1000>;
cache-unified;
cache-level = <2>;
};
ahb@c0000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc0000000 0x30000000>;
dma-ranges;
vic0: interrupt-controller@eff0000 {
compatible = "arm,pl192-vic";
reg = <0xeff0000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@80f00000 {
compatible = "arm,pl192-vic";
reg = <0x80f00000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};
uarta: serial@e0 {
compatible = "ns16550a";
reg = <0xe0 0x8>;
interrupts = <17>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};
uartb: serial@e8 {
compatible = "ns16550a";
reg = <0xe8 0x8>;
interrupts = <18>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};
uartc: serial@f0 {
compatible = "ns16550a";
reg = <0xf0 0x8>;
interrupts = <19>;
interrupt-parent = <&vic0>;
clock-frequency = <1846153>;
reg-shift = <0>;
};
usb0: usb@efe0000 {
compatible = "hpe,gxp-ehci", "generic-ehci";
reg = <0xefe0000 0x100>;
interrupts = <7>;
interrupt-parent = <&vic0>;
};
st: timer@80 {
compatible = "hpe,gxp-timer";
reg = <0x80 0x16>;
interrupts = <0>;
interrupt-parent = <&vic0>;
clocks = <&iopclk>;
clock-names = "iop";
};
usb1: usb@efe0100 {
compatible = "hpe,gxp-ohci", "generic-ohci";
reg = <0xefe0100 0x110>;
interrupts = <6>;
interrupt-parent = <&vic0>;
};
};
};
};

4
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
View File

@ -73,6 +73,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
View File

@ -84,6 +84,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi
View File

@ -139,3 +139,7 @@
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mm-venice-u-boot.dtsi
View File

@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
View File

@ -132,6 +132,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";

4
arch/arm/dts/imx8mn-venice-u-boot.dtsi
View File

@ -110,6 +110,10 @@
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;

8
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
View File

@ -89,6 +89,14 @@
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};

4
arch/arm/dts/imx8mp-venice-u-boot.dtsi
View File

@ -72,3 +72,7 @@
&wdog1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};

11
arch/arm/dts/k3-am62-ddr.dtsi Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am64-ddr.dtsi"
&memorycontroller {
power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
<&k3_pds 55 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 170 0>, <&k3_clks 16 4>;
};

533
arch/arm/dts/k3-am62-main.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM625 SoC Family Main Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x00 0x70000000 0x00 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x70000000 0x10000>;
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_conf: syscon@100000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x00100000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x00100000 0x20000>;
phy_gmii_sel: phy@4044 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4044 0x8>;
#phy-cells = <1>;
};
};
dmss: bus@48000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x4d000000 0x00 0x80000>,
<0x00 0x4a600000 0x00 0x80000>,
<0x00 0x4a400000 0x00 0x80000>;
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
inta_main_dmss: interrupt-controller@48000000 {
compatible = "ti,sci-inta";
reg = <0x00 0x48000000 0x00 0x100000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupt-parent = <&gic500>;
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <28>;
ti,interrupt-ranges = <4 68 36>;
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
};
main_bcdma: dma-controller@485c0100 {
compatible = "ti,am64-dmss-bcdma";
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <26>;
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
};
main_pktdma: dma-controller@485c0000 {
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <30>;
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
<0x24>, /* CPSW_TX_CHAN */
<0x25>, /* SAUL_TX_0_CHAN */
<0x26>; /* SAUL_TX_1_CHAN */
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
<0x11>, /* RING_CPSW_TX_CHAN */
<0x12>, /* RING_SAUL_TX_0_CHAN */
<0x13>; /* RING_SAUL_TX_1_CHAN */
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
<0x2b>, /* CPSW_RX_CHAN */
<0x2d>, /* SAUL_RX_0_CHAN */
<0x2f>, /* SAUL_RX_1_CHAN */
<0x31>, /* SAUL_RX_2_CHAN */
<0x33>; /* SAUL_RX_3_CHAN */
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
<0x2c>, /* FLOW_CPSW_RX_CHAN */
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
<0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
};
};
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
};
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
};
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
};
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
};
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
};
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
};
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
};
main_i2c0: i2c@20000000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20000000 0x00 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 2>;
clock-names = "fck";
};
main_i2c1: i2c@20010000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20010000 0x00 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 103 2>;
clock-names = "fck";
};
main_i2c2: i2c@20020000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20020000 0x00 0x100>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 104 2>;
clock-names = "fck";
};
main_i2c3: i2c@20030000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20030000 0x00 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 2>;
clock-names = "fck";
};
main_spi0: spi@20100000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x20100000 0x00 0x400>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 172 0>;
};
main_spi1: spi@20110000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20110000 0x00 0x400>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 173 0>;
};
main_spi2: spi@20120000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20120000 0x00 0x400>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 174 0>;
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <3>;
ti,interrupt-ranges = <0 32 16>;
};
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <190>, <191>, <192>,
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <87>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
};
main_gpio1: gpio@601000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <88>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
clock-names = "gpio";
};
sdhci0: mmc@fa10000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 57 6>;
assigned-clock-parents = <&k3_clks 57 8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
ti,trm-icp = <0x2>;
bus-width = <8>;
ti,clkbuf-sel = <0x7>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x9>;
ti,otap-del-sel-hs200 = <0x6>;
};
sdhci1: mmc@fa00000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
ti,trm-icp = <0x2>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
bus-width = <4>;
};
sdhci2: mmc@fa20000 {
compatible = "ti,am62-sdhci";
reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
clock-names = "clk_ahb", "clk_xin";
ti,trm-icp = <0x2>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
};
fss: bus@fc00000 {
compatible = "simple-bus";
reg = <0x00 0x0fc00000 0x00 0x70000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ospi0: spi@fc40000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x05 0x00000000 0x01 0x00000000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
clocks = <&k3_clks 75 7>;
assigned-clocks = <&k3_clks 75 7>;
assigned-clock-parents = <&k3_clks 75 8>;
assigned-clock-rates = <166666666>;
power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x00 0x08000000 0x00 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
clocks = <&k3_clks 13 0>;
assigned-clocks = <&k3_clks 13 3>;
assigned-clock-parents = <&k3_clks 13 11>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_pktdma 0xc600 15>,
<&main_pktdma 0xc601 15>,
<&main_pktdma 0xc602 15>,
<&main_pktdma 0xc603 15>,
<&main_pktdma 0xc604 15>,
<&main_pktdma 0xc605 15>,
<&main_pktdma 0xc606 15>,
<&main_pktdma 0xc607 15>,
<&main_pktdma 0x4600 15>;
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
"tx7", "rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 00 00 00 00];
ti,syscon-efuse = <&wkup_conf 0x200>;
};
cpsw_port2: port@2 {
reg = <2>;
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 00 00 00 00 00];
};
};
cpsw3g_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x00 0xf00 0x00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 13 0>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,j721e-cpts";
reg = <0x00 0x3d000 0x00 0x400>;
clocks = <&k3_clks 13 1>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
hwspinlock: spinlock@2a000000 {
compatible = "ti,am64-hwspinlock";
reg = <0x00 0x2a000000 0x00 0x1000>;
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@29000000 {
compatible = "ti,am64-mailbox";
reg = <0x00 0x29000000 0x00 0x200>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM625 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
};
mcu_i2c0: i2c@4900000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04900000 0x00 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
};
mcu_spi0: spi@4b00000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x04b00000 0x00 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
};
mcu_spi1: spi@4b10000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x04b10000 0x00 0x400>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_wakeup {
wkup_conf: syscon@43000000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
wkup_uart0: serial@2b300000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x2b300000 0x00 0x100>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "fclk";
};
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x02b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 4>;
clock-names = "fck";
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM62 SoC Family
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM625 SoC";
compatible = "ti,am625";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a53_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@f0000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
<0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
/* MCU Domain Range */
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
/* Wakeup Domain Range */
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
cbass_mcu: bus@4000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
cbass_wakeup: bus@2b000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
};
};
};
/* Now include the peripherals for each bus segments */
#include "k3-am62-main.dtsi"
#include "k3-am62-mcu.dtsi"
#include "k3-am62-wakeup.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* AM625 SK dts file for R5 SPL
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am625-sk.dts"
#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
#include "k3-am62-ddr.dtsi"
#include "k3-am625-sk-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
u-boot,dm-spl;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
u-boot,dm-spl;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
u-boot,dm-spl;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "rt", "scfg", "target_data";
reg = <0x00 0x44880000 0x00 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x43600000 0x0 0x10000>;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
u-boot,dm-spl;
};
};
&mcu_pmx0 {
u-boot,dm-spl;
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
>;
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
u-boot,dm-spl;
};
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
u-boot,dm-spl;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
u-boot,dm-spl;
};

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@ -0,0 +1,104 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common AM625 SK dts file for SPLs
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
mmc1 = &sdhci1;
};
memory@80000000 {
u-boot,dm-spl;
};
};
&cbass_main{
u-boot,dm-spl;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x00 0x2400000 0x00 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
u-boot,dm-spl;
};
};
&dmss {
u-boot,dm-spl;
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&wkup_conf {
u-boot,dm-spl;
};
&chipid {
u-boot,dm-spl;
};
&main_pmx0 {
u-boot,dm-spl;
};
&main_uart0 {
u-boot,dm-spl;
};
&main_uart0_pins_default {
u-boot,dm-spl;
};
&main_uart1 {
u-boot,dm-spl;
};
&cbass_mcu {
u-boot,dm-spl;
};
&cbass_wakeup {
u-boot,dm-spl;
};
&mcu_pmx0 {
u-boot,dm-spl;
};
&wkup_uart0 {
u-boot,dm-spl;
};
&sdhci1 {
u-boot,dm-spl;
};
&main_mmc1_pins_default {
u-boot,dm-spl;
};

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@ -0,0 +1,150 @@
// SPDX-License-Identifier: GPL-2.0
/*
* AM625 SK: https://www.ti.com/lit/zip/sprr448
*
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am625.dtsi"
/ {
compatible = "ti,am625-sk", "ti,am625";
model = "Texas Instruments AM625 SK";
aliases {
serial2 = &main_uart0;
mmc1 = &sdhci1;
};
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
no-map;
};
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9db00000 0x00 0xc00000>;
no-map;
};
};
};
&main_pmx0 {
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
>;
};
};
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
status = "reserved";
};
&mcu_uart0 {
status = "disabled";
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
&main_uart1 {
/* Main UART1 is used by TIFS firmware */
status = "reserved";
};
&main_uart2 {
status = "disabled";
};
&main_uart3 {
status = "disabled";
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
status = "disabled";
};
&main_uart6 {
status = "disabled";
};
&mcu_i2c0 {
status = "disabled";
};
&wkup_i2c0 {
status = "disabled";
};
&main_i2c0 {
status = "disabled";
};
&main_i2c1 {
status = "disabled";
};
&main_i2c2 {
status = "disabled";
};
&main_i2c3 {
status = "disabled";
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM625 SoC family in Quad core configuration
*
* TRM: https://www.ti.com/lit/pdf/spruiv7
*
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am62.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x002>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x003>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};

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2
arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
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@ -198,7 +198,7 @@
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "host";
dr_mode = "peripheral";
u-boot,dm-spl;
};

1
arch/arm/dts/k3-am654-r5-base-board.dts
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@ -309,6 +309,7 @@
&dwc3_0 {
status = "okay";
u-boot,dm-spl;
/delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;

24
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
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@ -192,6 +192,22 @@
u-boot,dm-spl;
};
&hbmc {
u-boot,dm-spl;
flash@0,0 {
u-boot,dm-spl;
};
};
&hbmc_mux {
u-boot,dm-spl;
};
&wkup_gpio0 {
u-boot,dm-spl;
};
&ospi0 {
u-boot,dm-spl;
@ -208,6 +224,14 @@
};
};
&mcu_fss0_hpb0_pins_default {
u-boot,dm-spl;
};
&wkup_gpio_pins_default {
u-boot,dm-spl;
};
&mcu_fss0_ospi1_pins_default {
u-boot,dm-spl;
};

11
arch/arm/dts/k3-j721e-common-proc-board.dts
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@ -213,6 +213,12 @@
>;
};
wkup_gpio_pins_default: wkup-gpio-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
>;
};
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
@ -381,6 +387,11 @@
phy-names = "cdns3,usb3-phy";
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&usbss1 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss1_pins_default>;

20
arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
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@ -170,12 +170,30 @@
};
fss: fss@47000000 {
compatible = "simple-bus";
compatible = "syscon", "simple-mfd";
reg = <0x0 0x47000000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
hbmc_mux: hbmc-mux {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x2>; /* HBMC select */
};
hbmc: hyperbus@47034000 {
compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
reg = <0x0 0x47034000 0x0 0x100>,
<0x5 0x00000000 0x1 0x0000000>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <1>;
mux-controls = <&hbmc_mux 0>;
assigned-clocks = <&k3_clks 102 0>;
assigned-clock-rates = <250000000>;
};
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,

45
arch/arm/dts/k3-j721e-r5-common-proc-board.dts
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@ -129,6 +129,31 @@
>;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
wkup_gpio_pins_default: wkup-gpio-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@ -207,6 +232,11 @@
status = "okay";
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_gpio_pins_default>;
};
&mcu_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
@ -307,6 +337,21 @@
};
};
&hbmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
<0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x0 0x0 0x4000000>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;

32
arch/arm/dts/k3-j721e-som-p0.dtsi
View File

@ -150,6 +150,25 @@
>;
};
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@ -167,6 +186,19 @@
};
};
&hbmc {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
<0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
flash@0,0 {
compatible = "cypress,hyperflash", "cfi-flash";
reg = <0x0 0x0 0x4000000>;
};
};
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;

85
arch/arm/dts/ls1021a.dtsi
View File

@ -31,17 +31,24 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
clocks = <&cluster1_clk>;
clocks = <&clockgen 1 0>;
};
cpu@f01 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
clocks = <&cluster1_clk>;
clocks = <&clockgen 1 0>;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@ -82,6 +89,13 @@
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
};
sfp: efuse@1e80000 {
compatible = "fsl,ls1021a-sfp";
reg = <0x0 0x1e80000 0x0 0x10000>;
clocks = <&clockgen 4 3>;
clock-names = "sfp";
};
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg", "syscon";
reg = <0x1ee0000 0x10000>;
@ -185,41 +199,10 @@
};
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1ee1000 0x10000>;
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "sysclk";
};
cga_pll1: pll@800 {
compatible = "fsl,qoriq-core-pll-2.0";
#clock-cells = <1>;
reg = <0x800 0x10>;
compatible = "fsl,ls1021a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
clock-output-names = "cga-pll1", "cga-pll1-div2",
"cga-pll1-div4";
};
platform_clk: pll@c00 {
compatible = "fsl,qoriq-core-pll-2.0";
#clock-cells = <1>;
reg = <0xc00 0x10>;
clocks = <&sysclk>;
clock-output-names = "platform-clk", "platform-clk-div2";
};
cluster1_clk: clk0c0@0 {
compatible = "fsl,qoriq-core-mux-2.0";
#clock-cells = <0>;
reg = <0x0 0x10>;
clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
clock-output-names = "cluster1-clk";
};
};
dspi0: dspi@2100000 {
@ -229,7 +212,7 @@
reg = <0x2100000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@ -242,7 +225,7 @@
reg = <0x2110000 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@ -265,7 +248,7 @@
reg = <0x2180000 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
@ -276,7 +259,7 @@
reg = <0x2190000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
@ -287,7 +270,7 @@
reg = <0x21a0000 0x10000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
status = "disabled";
};
@ -336,7 +319,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2960000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -345,7 +328,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2970000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -354,7 +337,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2980000 0x1000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -363,7 +346,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x2990000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -372,7 +355,7 @@
compatible = "fsl,ls1021a-lpuart";
reg = <0x29a0000 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "ipg";
status = "disabled";
};
@ -381,7 +364,7 @@
compatible = "fsl,imx21-wdt";
reg = <0x2ad0000 0x10000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "wdog-en";
big-endian;
};
@ -390,7 +373,7 @@
compatible = "fsl,vf610-sai";
reg = <0x2b50000 0x10000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "sai";
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
@ -403,7 +386,7 @@
compatible = "fsl,vf610-sai";
reg = <0x2b60000 0x10000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&platform_clk 1>;
clocks = <&clockgen 4 1>;
clock-names = "sai";
dma-names = "tx", "rx";
dmas = <&edma0 1 45>,
@ -424,8 +407,8 @@
dma-channels = <32>;
big-endian;
clock-names = "dmamux0", "dmamux1";
clocks = <&platform_clk 1>,
<&platform_clk 1>;
clocks = <&clockgen 4 1>,
<&clockgen 4 1>;
};
enet0: ethernet@2d10000 {

20
arch/arm/dts/omap3-devkit8000-u-boot.dtsi Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
#include "omap3-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart3;
};
ethernet@2c000000 {
compatible = "davicom,dm9000";
reg = <0x2c000000 2 0x2c000400 2>;
bank-width = <2>;
};
};

349
arch/arm/dts/omap3-devkit8000.dts Normal file
View File

@ -0,0 +1,349 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Author: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
*/
/dts-v1/;
#include "omap34xx.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000";
compatible = "timll,omap3-devkit8000", "ti,omap3430", "ti,omap3";
aliases {
display1 = &dvi0;
display2 = &tv0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
leds {
compatible = "gpio-leds";
heartbeat {
label = "devkit8000::led1";
gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */
default-state = "on";
linux,default-trigger = "heartbeat";
};
mmc {
label = "devkit8000::led2";
gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */
default-state = "on";
linux,default-trigger = "none";
};
usr {
label = "devkit8000::led3";
gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */
default-state = "on";
linux,default-trigger = "usr";
};
pmu_stat {
label = "devkit8000::pmu_stat";
gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "devkit8000";
ti,mcbsp = <&mcbsp2>;
ti,audio-routing =
"Ext Spk", "PREDRIVEL",
"Ext Spk", "PREDRIVER",
"MAINMIC", "Main Mic",
"Main Mic", "Mic Bias 1";
};
tfp410: encoder0 {
compatible = "ti,tfp410";
powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&dpi_dvi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c2>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
tv0: connector1 {
compatible = "svideo-connector";
label = "tv";
port {
tv_connector_in: endpoint {
remote-endpoint = <&venc_out>;
};
};
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
status = "disabled";
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&mmc1 {
vmmc-supply = <&vmmc1>;
vqmmc-supply = <&vsim>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&twl_gpio {
ti,use-leds;
/*
* pulldowns:
* BIT(1), BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
* BIT(15), BIT(16), BIT(17)
*/
ti,pulldowns = <0x03a1c6>;
};
&wdt2 {
status = "disabled";
};
&mcbsp2 {
status = "okay";
};
&gpmc {
ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
6 0 0x2c000000 0x1000000>; /* CS6: 16MB for DM9000 */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
nand-bus-width = <16>;
gpmc,device-width = <2>;
ti,nand-ecc-opt = "sw";
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
x-loader@0 {
label = "X-Loader";
reg = <0 0x80000>;
};
bootloaders@80000 {
label = "U-Boot";
reg = <0x80000 0x1e0000>;
};
bootloaders_env@260000 {
label = "U-Boot Env";
reg = <0x260000 0x20000>;
};
kernel@280000 {
label = "Kernel";
reg = <0x280000 0x400000>;
};
filesystem@680000 {
label = "File System";
reg = <0x680000 0xf980000>;
};
};
ethernet@6,0 {
compatible = "davicom,dm9000";
reg = <6 0x000 2
6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */
bank-width = <2>;
interrupt-parent = <&gpio1>;
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
davicom,no-eeprom;
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <0>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <6>;
gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <180>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <90>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wr-access-ns = <0>;
};
};
&omap3_pmx_core {
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
};
&vpll1 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&dss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
vdds_dsi-supply = <&vpll1>;
vdda_dac-supply = <&vdac>;
port {
#address-cells = <1>;
#size-cells = <0>;
dpi_dvi_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
endpoint@1 {
reg = <1>;
};
};
};
&venc {
status = "okay";
vdda-supply = <&vdac>;
port {
venc_out: endpoint {
remote-endpoint = <&tv_connector_in>;
ti,channels = <2>;
};
};
};

1
arch/arm/dts/omap3-u-boot.dtsi
View File

@ -78,4 +78,5 @@
&i2c1 {
u-boot,dm-spl;
clock-frequency = <100000>;
};

4
arch/arm/dts/sam9x60ek.dts
View File

@ -49,7 +49,7 @@
status = "okay";
nor_flash: sst26vf064@0 {
compatible = "spi-flash";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
@ -72,7 +72,7 @@
status = "okay";
eeprom@53 {
compatible = "atmel,24c32";
compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa025e48, an at24c02 with page size of 16 */
reg = <0x53>;
pagesize = <16>;
};

2
arch/arm/dts/sama5d27_som1.dtsi
View File

@ -92,7 +92,7 @@
status = "okay";
i2c_eeprom: i2c_eeprom@50 {
compatible = "microchip,24aa02e48";
compatible = "atmel,24c02"; /* EEPROM is 2Kbits microchip 24aa02e48 */
reg = <0x50>;
};
};

46
arch/arm/dts/sama7g5.dtsi
View File

@ -33,6 +33,7 @@
reg = <0x0>;
clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
clock-names = "cpu", "master", "xtal";
operating-points-v2 = <&cpu_opp_table>;
};
};
@ -225,7 +226,7 @@
status = "disabled";
};
rtt: rtt@e001d020 {
rtt: rtc@e001d020 {
compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xe001d020 0x30>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@ -490,6 +491,30 @@
status = "disabled";
};
pdmc0: sound@e1608000 {
compatible = "microchip,sama7g5-pdmc";
reg = <0xe1608000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
#sound-dai-cells = <0>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>;
dma-names = "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>;
clock-names = "pclk", "gclk";
status = "disabled";
};
pdmc1: sound@e160c000 {
compatible = "microchip,sama7g5-pdmc";
reg = <0xe160c000 0x1000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#sound-dai-cells = <0>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>;
dma-names = "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>;
clock-names = "pclk", "gclk";
status = "disabled";
};
spdifrx: spdifrx@e1614000 {
#sound-dai-cells = <0>;
compatible = "microchip,sama7g5-spdifrx";
@ -628,9 +653,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
<&dma0 AT91_XDMAC_DT_PERID(8)>;
dma-names = "rx", "tx";
dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
<&dma0 AT91_XDMAC_DT_PERID(7)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
@ -814,9 +839,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
<&dma0 AT91_XDMAC_DT_PERID(22)>;
dma-names = "rx", "tx";
dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
<&dma0 AT91_XDMAC_DT_PERID(21)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
@ -838,9 +863,9 @@
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
atmel,fifo-size = <32>;
dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,
<&dma0 AT91_XDMAC_DT_PERID(24)>;
dma-names = "rx", "tx";
dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
<&dma0 AT91_XDMAC_DT_PERID(23)>;
dma-names = "tx", "rx";
status = "disabled";
};
};
@ -885,7 +910,6 @@
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupt-parent;
reg = <0xe8c11000 0x1000>,
<0xe8c12000 0x2000>;
};

123
arch/arm/dts/stm32mp13-pinctrl.dtsi Normal file
View File

@ -0,0 +1,123 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-open-drain;
bias-disable;
};
};
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
};
};
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
};
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
pins2 {
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
slew-rate = <1>;
drive-open-drain;
bias-pull-up;
};
};
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
};
};
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
bias-disable;
};
};
};

91
arch/arm/dts/stm32mp13-u-boot.dtsi Normal file
View File

@ -0,0 +1,91 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*/
/ {
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
pinctrl0 = &pinctrl;
};
/* need PSCI for sysreset during board_f */
psci {
u-boot,dm-pre-proper;
};
soc {
u-boot,dm-pre-reloc;
ddr: ddr@5a003000 {
u-boot,dm-pre-reloc;
compatible = "st,stm32mp13-ddr";
reg = <0x5A003000 0x550
0x5A004000 0x234>;
status = "okay";
};
};
};
&bsec {
u-boot,dm-pre-reloc;
};
&gpioa {
u-boot,dm-pre-reloc;
};
&gpiob {
u-boot,dm-pre-reloc;
};
&gpioc {
u-boot,dm-pre-reloc;
};
&gpiod {
u-boot,dm-pre-reloc;
};
&gpioe {
u-boot,dm-pre-reloc;
};
&gpiof {
u-boot,dm-pre-reloc;
};
&gpiog {
u-boot,dm-pre-reloc;
};
&gpioh {
u-boot,dm-pre-reloc;
};
&gpioi {
u-boot,dm-pre-reloc;
};
&iwdg2 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&syscfg {
u-boot,dm-pre-reloc;
};

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