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Merge branch '2022-07-08-Kconfig-migrations' into next

Browse Source 
- Another small round of CONFIG migrations to Kconfig
This commit is contained in:
Tom Rini 2022-07-08 17:57:39 -04:00
commit 05a4859637
75 changed files with 62 additions and 3403 deletions
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7
arch/arm/Kconfig
View File

@ -330,11 +330,6 @@ config CPU_V7R
select SYS_ARM_MPU
select SYS_CACHE_SHIFT_6
config CPU_SA1100
bool
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
config SYS_CPU
default "arm720t" if CPU_ARM720T
default "arm920t" if CPU_ARM920T
@ -345,7 +340,6 @@ config SYS_CPU
default "armv7" if CPU_V7A
default "armv7" if CPU_V7R
default "armv7m" if CPU_V7M
default "sa1100" if CPU_SA1100
default "armv8" if ARM64
config SYS_ARM_ARCH
@ -359,7 +353,6 @@ config SYS_ARM_ARCH
default 7 if CPU_V7A
default 7 if CPU_V7M
default 7 if CPU_V7R
default 4 if CPU_SA1100
default 8 if ARM64
choice

2
arch/arm/Makefile
View File

@ -10,7 +10,6 @@ arch-$(CONFIG_CPU_ARM720T) =-march=armv4
arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_ARM1136) =-march=armv5t
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
@ -39,7 +38,6 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM920T) =
tune-$(CONFIG_CPU_ARM926EJS) =
tune-$(CONFIG_CPU_ARM946ES) =
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
tune-$(CONFIG_CPU_ARM1136) =
tune-$(CONFIG_CPU_ARM1176) =
tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a

9
arch/arm/cpu/sa1100/Makefile
View File

@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
extra-y = start.o
obj-y += cpu.o
obj-y += timer.o

65
arch/arm/cpu/sa1100/cpu.c
View File

@ -1,65 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*/
/*
* CPU specific code
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/system.h>
#include <asm/io.h>
static void cache_flush(void);
int cleanup_before_linux (void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* just disable everything that can disturb booting linux
*/
disable_interrupts();
/* turn off I-cache */
icache_disable();
dcache_disable();
/* flush I-cache */
cache_flush();
return (0);
}
/* flush I/D-cache */
static void cache_flush (void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
#define RST_BASE 0x90030000
#define RSRR 0x00
#define RCSR 0x04
__attribute__((noreturn)) void reset_cpu(void)
{
/* repeat endlessly */
while (1) {
writel(0, RST_BASE + RCSR);
writel(1, RST_BASE + RSRR);
}
}

126
arch/arm/cpu/sa1100/start.S
View File

@ -1,126 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for SA1100 CPU
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
/* Interrupt-Controller base address */
IC_BASE: .word 0x90050000
#define ICMR 0x04
/* Reset-Controller */
RST_BASE: .word 0x90030000
#define RSRR 0x00
#define RCSR 0x04
/* PWR */
PWR_BASE: .word 0x90020000
#define PSPR 0x08
#define PPCR 0x14
cpuspeed: .word CONFIG_SYS_CPUSPEED
cpu_init_crit:
/*
* mask all IRQs
*/
ldr r0, IC_BASE
mov r1, #0x00
str r1, [r0, #ICMR]
/* set clock speed */
ldr r0, PWR_BASE
ldr r1, cpuspeed
str r1, [r0, #PPCR]
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
bl lowlevel_init
mov lr, ip
#endif
/*
* disable MMU stuff and enable I-cache
*/
mrc p15,0,r0,c1,c0
bic r0, r0, #0x00002000 @ clear bit 13 (X)
bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
mcr p15,0,r0,c1,c0
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
mov pc, lr

66
arch/arm/cpu/sa1100/timer.c
View File

@ -1,66 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*/
#include <common.h>
#include <SA-1100.h>
#include <time.h>
#include <linux/delay.h>
static ulong get_timer_masked (void)
{
return OSCR;
}
ulong get_timer (ulong base)
{
return get_timer_masked ();
}
void __udelay(unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
endtime = get_timer_masked () + tmo;
do {
ulong now = get_timer_masked ();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

112
arch/arm/include/asm/arch-sa1100/bitfield.h
View File

@ -1,112 +0,0 @@
/*
* FILE bitfield.h
*
* Version 1.1
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date April 1998 (April 1997)
* System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
* Purpose Definition of macros to operate on bit fields.
*/
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
/*
* MACRO: Fld
*
* Purpose
* The macro "Fld" encodes a bit field, given its size and its shift value
* with respect to bit 0.
*
* Note
* A more intuitive way to encode bit fields would have been to use their
* mask. However, extracting size and shift value information from a bit
* field's mask is cumbersome and might break the assembler (255-character
* line-size limit).
*
* Input
* Size Size of the bit field, in number of bits.
* Shft Shift value of the bit field with respect to bit 0.
*
* Output
* Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
/*
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
*
* Purpose
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
* the size, shift value, mask, aligned mask, and first bit of a
* bit field.
*
* Input
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FSize Size of the bit field, in number of bits.
* FShft Shift value of the bit field with respect to bit 0.
* FMsk Mask for the bit field.
* FAlnMsk Mask for the bit field, aligned on bit 0.
* F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
/*
* MACRO: FInsrt
*
* Purpose
* The macro "FInsrt" inserts a value into a bit field by shifting the
* former appropriately.
*
* Input
* Value Bit-field value.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
/*
* MACRO: FExtr
*
* Purpose
* The macro "FExtr" extracts the value of a bit field by masking and
* shifting it appropriately.
*
* Input
* Data Data containing the bit-field to be extracted.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* __BITFIELD_H */

3
arch/arm/include/asm/proc-armv/system.h
View File

@ -163,8 +163,7 @@
#endif /* CONFIG_ARM64 */
#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
defined(CONFIG_ARM64)
#if defined(CONFIG_ARM64)
/*
* On the StrongARM, "swp" is terminally broken since it bypasses the
* cache totally. This means that the cache becomes inconsistent, and,

13
arch/arm/mach-keystone/ddr3_spd.c
View File

@ -404,24 +404,11 @@ static void init_ddr3param(struct ddr3_spd_cb *spd_cb,
static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
{
int ret;
#if !CONFIG_IS_ENABLED(DM_I2C)
int old_bus;
i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
old_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256);
i2c_set_bus_num(old_bus);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(1, 0x53, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, 0, (unsigned char *)spd_params, 256);
#endif
if (ret) {
printf("Cannot read DIMM params\n");
return 1;

2
arch/arm/mach-omap2/omap3/emif4.c
View File

@ -41,7 +41,7 @@ static u32 get_sdr_cs_size(u32 cs)
/* TODO: Calculate the size based on EMIF4 configuration */
if (cs == CS0)
size = CONFIG_SYS_CS0_SIZE;
size = 256 * 1024 * 1024;
return size;
}

3
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -1230,6 +1230,9 @@ config SYS_CPC_REINIT_F
config SYS_FSL_CPC
bool "Corenet Platform Cache support"
config SYS_CACHE_STASHING
bool "Enable cache stashing"
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx

1
board/freescale/corenet_ds/p4080ds_ddr.c
View File

@ -62,7 +62,6 @@
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000

2
board/freescale/p1_p2_rdb_pc/ddr.c
View File

@ -227,7 +227,7 @@ phys_size_t fixed_sdram(void)
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
.ddr_data_init = 0xdeadbeef, /* Poison value */
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,

15
board/lego/ev3/legoev3.c
View File

@ -27,6 +27,7 @@
#include <hwconfig.h>
#include <asm/mach-types.h>
#include <asm/setup.h>
#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
@ -57,6 +58,8 @@ const int lpsc_size = ARRAY_SIZE(lpsc);
*/
static void setup_serial_number(void)
{
struct udevice *idev, *ibus;
int ret;
u32 offset;
char serial_number[13];
u8 buf[6];
@ -65,7 +68,15 @@ static void setup_serial_number(void)
if (env_get("serial#"))
return;
if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &ibus);
if (ret)
return;
ret = dm_i2c_probe(ibus, EEPROM_I2C_ADDR, 0, &idev);
if (ret)
return;
if (dm_i2c_read(idev, EEPROM_REV_OFFSET, buf, 2)) {
printf("\nEEPROM revision read failed!\n");
return;
}
@ -83,7 +94,7 @@ static void setup_serial_number(void)
/* EEPROM rev 3 has Bluetooth address where rev should be */
offset = (eeprom_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_BDADDR_OFFSET;
if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) {
if (dm_i2c_read(idev, offset, buf, 6)) {
printf("\nEEPROM serial read failed!\n");
return;
}

1
configs/P2041RDB_NAND_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_SDCARD_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_SPIFLASH_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P2041RDB_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_NAND_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_SDCARD_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_SPIFLASH_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P3041DS_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_SDCARD_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_SPIFLASH_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P4080DS_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_NAND_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_SDCARD_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_SPIFLASH_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/P5040DS_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T1024RDB_NAND_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T1024RDB_SDCARD_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1024RDB_SPIFLASH_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1024RDB_defconfig
View File

@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T1042D4RDB_NAND_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T1042D4RDB_SDCARD_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1042D4RDB_SPIFLASH_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T1042D4RDB_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080QDS_NAND_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T2080QDS_SDCARD_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T2080QDS_SECURE_BOOT_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_NXP_ESBC=y
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
CONFIG_PCIE1=y

1
configs/T2080QDS_SPIFLASH_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T2080QDS_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080RDB_NAND_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

1
configs/T2080RDB_SDCARD_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T2080RDB_SPIFLASH_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T2080RDB_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/T2080RDB_revD_NAND_defconfig
View File

@ -14,6 +14,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y

1
configs/T2080RDB_revD_SDCARD_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
CONFIG_PCIE1=y

1
configs/T2080RDB_revD_SPIFLASH_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
CONFIG_PCIE1=y

1
configs/T2080RDB_revD_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_T2080RDB_REV_D=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T4240RDB_SDCARD_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/T4240RDB_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

1
configs/kmcent2_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_CACHE_STASHING=y
# CONFIG_DEEP_SLEEP is not set
CONFIG_PCIE1=y
CONFIG_KM_DEF_NETDEV="eth2"

2
configs/legoev3_defconfig
View File

@ -46,7 +46,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_NET is not set
CONFIG_DM=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y

4
drivers/i2c/Kconfig
View File

@ -687,9 +687,9 @@ config SYS_I2C_SPEED
config SYS_I2C_BUS_MAX
int "Max I2C busses"
depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
default 2 if TI816X
default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
default 3 if OMAP34XX || AM33XX || AM43XX
default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
default 5 if OMAP54XX
help

97
drivers/i2c/davinci_i2c.c
View File

@ -21,14 +21,12 @@
#include <linux/delay.h>
#include "davinci_i2c.h"
#if CONFIG_IS_ENABLED(DM_I2C)
/* Information about i2c controller */
struct i2c_bus {
int id;
uint speed;
struct i2c_regs *regs;
};
#endif
#define CHECK_NACK() \
do {\
@ -340,99 +338,6 @@ static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
return rc;
}
#if !CONFIG_IS_ENABLED(DM_I2C)
static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 3
case 2:
return (struct i2c_regs *)I2C2_BASE;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
case 1:
return (struct i2c_regs *)I2C1_BASE;
#endif
case 0:
return (struct i2c_regs *)I2C_BASE;
default:
printf("wrong hwadapnr: %d\n", adap->hwadapnr);
}
return NULL;
}
static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
{
struct i2c_regs *i2c_base = davinci_get_base(adap);
uint ret;
adap->speed = speed;
ret = _davinci_i2c_setspeed(i2c_base, speed);
return ret;
}
static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
int slaveadd)
{
struct i2c_regs *i2c_base = davinci_get_base(adap);
adap->speed = speed;
_davinci_i2c_init(i2c_base, speed, slaveadd);
return;
}
static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
uint32_t addr, int alen, uint8_t *buf, int len)
{
struct i2c_regs *i2c_base = davinci_get_base(adap);
return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
}
static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
uint32_t addr, int alen, uint8_t *buf, int len)
{
struct i2c_regs *i2c_base = davinci_get_base(adap);
return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
}
static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
{
struct i2c_regs *i2c_base = davinci_get_base(adap);
return _davinci_i2c_probe_chip(i2c_base, chip);
}
U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED,
CONFIG_SYS_DAVINCI_I2C_SLAVE,
0)
#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED1,
CONFIG_SYS_DAVINCI_I2C_SLAVE1,
1)
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED2,
CONFIG_SYS_DAVINCI_I2C_SLAVE2,
2)
#endif
#else /* CONFIG_DM_I2C */
static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
int nmsgs)
{
@ -507,5 +412,3 @@ U_BOOT_DRIVER(i2c_davinci) = {
.priv_auto = sizeof(struct i2c_bus),
.ops = &davinci_i2c_ops,
};
#endif /* CONFIG_DM_I2C */

15
drivers/usb/gadget/ether.c
View File

@ -1048,13 +1048,6 @@ static int eth_set_config(struct eth_dev *dev, unsigned number,
int result = 0;
struct usb_gadget *gadget = dev->gadget;
if (gadget_is_sa1100(gadget)
&& dev->config
&& dev->tx_qlen != 0) {
/* tx fifo is full, but we can't clear it...*/
pr_err("can't change configurations");
return -ESPIPE;
}
eth_reset_config(dev);
switch (number) {
@ -2019,14 +2012,6 @@ static int eth_bind(struct usb_gadget *gadget)
/* sh doesn't support multiple interfaces or configs */
cdc = 0;
rndis = 0;
} else if (gadget_is_sa1100(gadget)) {
/* hardware can't write zlps */
zlp = 0;
/*
* sa1100 CAN do CDC, without status endpoint ... we use
* non-CDC to be compatible with ARM Linux-2.4 "usb-eth".
*/
cdc = 0;
}
gcnum = usb_gadget_controller_number(gadget);

9
drivers/usb/gadget/gadget_chips.h
View File

@ -45,13 +45,6 @@
#define gadget_is_sh(g) 0
#endif
/* not yet stable on 2.6 (would help "original Zaurus") */
#ifdef CONFIG_USB_GADGET_SA1100
#define gadget_is_sa1100(g) (!strcmp("sa1100_udc", (g)->name))
#else
#define gadget_is_sa1100(g) 0
#endif
/* handhelds.org tree (?) */
#ifdef CONFIG_USB_GADGET_MQ11XX
#define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name))
@ -183,8 +176,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
return 0x02;
else if (gadget_is_sh(gadget))
return 0x04;
else if (gadget_is_sa1100(gadget))
return 0x05;
else if (gadget_is_goku(gadget))
return 0x06;
else if (gadget_is_mq11xx(gadget))

2833
include/SA-1100.h
View File

File diff suppressed because it is too large Load Diff

1
include/configs/P1010RDB.h
View File

@ -118,7 +118,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000

1
include/configs/P2041RDB.h
View File

@ -45,7 +45,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */

1
include/configs/T102xRDB.h
View File

@ -95,7 +95,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef

1
include/configs/T104xRDB.h
View File

@ -63,7 +63,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef

1
include/configs/T208xQDS.h
View File

@ -68,7 +68,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/T208xRDB.h
View File

@ -63,7 +63,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

1
include/configs/T4240RDB.h
View File

@ -44,7 +44,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif

3
include/configs/am3517_evm.h
View File

@ -85,9 +85,6 @@
/* memtest works on */
/* Physical Memory Map */
#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
/* FLASH and environment organization */
/* **** PISMO SUPPORT *** */

1
include/configs/corenet_ds.h
View File

@ -38,7 +38,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef

1
include/configs/kmcent2.h
View File

@ -146,7 +146,6 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
/* POST memory regions test */

6
include/configs/legoev3.h
View File

@ -41,12 +41,6 @@
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
/*
* I2C Configuration
*/
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*
* U-Boot general configuration
*/

2
include/configs/omapl138_lcdk.h
View File

@ -99,8 +99,6 @@
/*
* I2C Configuration
*/
#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
/*

1
include/configs/p1_p2_rdb_pc.h
View File

@ -132,7 +132,6 @@
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000

8
include/configs/ti_armv7_keystone2.h
View File

@ -59,14 +59,6 @@
#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
/* I2C Configuration */
#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
/* EEPROM definitions */
/* NAND Configuration */

10
scripts/config_whitelist.txt
View File

@ -495,7 +495,6 @@ CONFIG_SYS_CACHE_ACR1
CONFIG_SYS_CACHE_ACR2
CONFIG_SYS_CACHE_DCACR
CONFIG_SYS_CACHE_ICACR
CONFIG_SYS_CACHE_STASHING
CONFIG_SYS_CCSRBAR
CONFIG_SYS_CCSRBAR_PHYS
CONFIG_SYS_CCSRBAR_PHYS_HIGH
@ -515,7 +514,6 @@ CONFIG_SYS_CPLD_FTIM1
CONFIG_SYS_CPLD_FTIM2
CONFIG_SYS_CPLD_FTIM3
CONFIG_SYS_CPLD_SIZE
CONFIG_SYS_CPUSPEED
CONFIG_SYS_CPU_CLK
CONFIG_SYS_CS0_BASE
CONFIG_SYS_CS0_CTRL
@ -524,7 +522,6 @@ CONFIG_SYS_CS0_FTIM1
CONFIG_SYS_CS0_FTIM2
CONFIG_SYS_CS0_FTIM3
CONFIG_SYS_CS0_MASK
CONFIG_SYS_CS0_SIZE
CONFIG_SYS_CS1_BASE
CONFIG_SYS_CS1_CTRL
CONFIG_SYS_CS1_FTIM0
@ -593,12 +590,6 @@ CONFIG_SYS_DA850_DDR2_SDTIMR2
CONFIG_SYS_DA850_PLL0_PLLM
CONFIG_SYS_DA850_PLL1_PLLM
CONFIG_SYS_DA850_SYSCFG_SUSPSRC
CONFIG_SYS_DAVINCI_I2C_SLAVE
CONFIG_SYS_DAVINCI_I2C_SLAVE1
CONFIG_SYS_DAVINCI_I2C_SLAVE2
CONFIG_SYS_DAVINCI_I2C_SPEED
CONFIG_SYS_DAVINCI_I2C_SPEED1
CONFIG_SYS_DAVINCI_I2C_SPEED2
CONFIG_SYS_DCACHE_INV
CONFIG_SYS_DCSRBAR
CONFIG_SYS_DCSRBAR_PHYS
@ -626,7 +617,6 @@ CONFIG_SYS_DDR_CS0_CONFIG_2
CONFIG_SYS_DDR_CS1_BNDS
CONFIG_SYS_DDR_CS1_CONFIG
CONFIG_SYS_DDR_CS1_CONFIG_2
CONFIG_SYS_DDR_DATA_INIT
CONFIG_SYS_DDR_INIT_ADDR
CONFIG_SYS_DDR_INIT_EXT_ADDR
CONFIG_SYS_DDR_INTERVAL