arm: socfpga: Add misc support for Arria 10
Add misc support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
caf36e1edb
commit
35b9800ff2
@ -12,6 +12,7 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
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pinmux_arria10.o \
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misc_arria10.o \
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reset_manager_arria10.o
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obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
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@ -22,4 +22,10 @@ void socfpga_fpga_add(void);
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static inline void socfpga_fpga_add(void) {}
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#endif
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#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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unsigned int dedicated_uart_com_port(const void *blob);
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unsigned int shared_uart_com_port(const void *blob);
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unsigned int uart_com_port(const void *blob);
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#endif
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#endif /* _MISC_H_ */
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259
arch/arm/mach-socfpga/misc_arria10.c
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259
arch/arm/mach-socfpga/misc_arria10.c
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@ -0,0 +1,259 @@
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <altera.h>
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <ns16550.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/sdram_arria10.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SPL_BUILD)
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
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(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
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#endif
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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/*
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* DesignWare Ethernet initialization
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*/
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#ifdef CONFIG_ETH_DESIGNWARE
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void dwmac_deassert_reset(const unsigned int of_reset_id,
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const u32 phymode)
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{
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u32 reset;
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if (of_reset_id == EMAC0_RESET) {
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reset = SOCFPGA_RESET(EMAC0);
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} else if (of_reset_id == EMAC1_RESET) {
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reset = SOCFPGA_RESET(EMAC1);
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} else if (of_reset_id == EMAC2_RESET) {
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reset = SOCFPGA_RESET(EMAC2);
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} else {
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printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
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return;
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}
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clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
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SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
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phymode);
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/* Release the EMAC controller from reset */
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socfpga_per_reset(reset, 0);
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}
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#endif
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#if defined(CONFIG_SPL_BUILD)
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/*
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+ * This function initializes security policies to be consistent across
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+ * all logic units in the Arria 10.
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+ *
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+ * The idea is to set all security policies to be normal, nonsecure
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+ * for all units.
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+ */
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static void initialize_security_policies(void)
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{
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/* Put OCRAM in non-secure */
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writel(0x003f0000, &noc_fw_ocram_base->region0);
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writel(0x1, &noc_fw_ocram_base->enable);
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}
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int arch_early_init_r(void)
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{
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initialize_security_policies();
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/* Configure the L2 controller to make SDRAM start at 0 */
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writel(0x1, &pl310->pl310_addr_filter_start);
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/* assert reset to all except L4WD0 and L4TIMER0 */
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socfpga_per_reset_all();
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/* configuring the clock based on handoff */
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/* TODO: Add call to cm_basic_init() */
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/* Add device descriptor to FPGA device table */
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socfpga_fpga_add();
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return 0;
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}
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#else
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int arch_early_init_r(void)
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{
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return 0;
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}
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#endif
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/*
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* This function looking the 1st encounter UART peripheral,
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* and then return its offset of the dedicated/shared IO pin
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* mux. offset value (zero and above).
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*/
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static int find_peripheral_uart(const void *blob,
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int child, const char *node_name)
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{
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int len;
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fdt_addr_t base_addr = 0;
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fdt_size_t size;
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const u32 *cell;
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u32 value, offset = 0;
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base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
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if (base_addr != FDT_ADDR_T_NONE) {
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cell = fdt_getprop(blob, child, "pinctrl-single,pins",
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&len);
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if (cell != NULL) {
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for (; len > 0; len -= (2 * sizeof(u32))) {
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offset = fdt32_to_cpu(*cell++);
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value = fdt32_to_cpu(*cell++);
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/* Found UART peripheral. */
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if (value == PINMUX_UART)
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return offset;
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}
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}
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}
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return -EINVAL;
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}
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/*
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* This function looks up the 1st encounter UART peripheral,
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* and then return its offset of the dedicated/shared IO pin
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* mux. UART peripheral is found if the offset is not in negative
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* value.
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*/
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static int is_peripheral_uart_true(const void *blob,
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int node, const char *child_name)
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{
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int child, len;
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const char *node_name;
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child = fdt_first_subnode(blob, node);
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if (child < 0)
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return -EINVAL;
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node_name = fdt_get_name(blob, child, &len);
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while (node_name) {
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if (!strcmp(child_name, node_name))
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return find_peripheral_uart(blob, child, node_name);
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child = fdt_next_subnode(blob, child);
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if (child < 0)
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break;
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node_name = fdt_get_name(blob, child, &len);
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}
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return -1;
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}
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/*
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* This function looking the 1st encounter UART dedicated IO peripheral,
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* and then return based address of the 1st encounter UART dedicated
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* IO peripheral.
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*/
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unsigned int dedicated_uart_com_port(const void *blob)
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{
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int node;
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node = fdtdec_next_compatible(blob, 0,
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COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
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if (node < 0)
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return 0;
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if (is_peripheral_uart_true(blob, node, "dedicated") >= 0)
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return SOCFPGA_UART1_ADDRESS;
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return 0;
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}
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/*
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* This function looking the 1st encounter UART shared IO peripheral, and then
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* return based address of the 1st encounter UART shared IO peripheral.
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*/
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unsigned int shared_uart_com_port(const void *blob)
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{
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int node, ret;
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node = fdtdec_next_compatible(blob, 0,
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COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
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if (node < 0)
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return 0;
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ret = is_peripheral_uart_true(blob, node, "shared");
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if (ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 ||
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ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 ||
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ret == PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3)
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return SOCFPGA_UART0_ADDRESS;
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else if (ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 ||
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ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 ||
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ret == PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3)
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return SOCFPGA_UART1_ADDRESS;
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return 0;
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}
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/*
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* This function looking the 1st encounter UART peripheral, and then return
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* base address of the 1st encounter UART peripheral.
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*/
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unsigned int uart_com_port(const void *blob)
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{
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unsigned int ret;
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ret = dedicated_uart_com_port(blob);
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if (ret)
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return ret;
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return shared_uart_com_port(blob);
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}
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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const u32 bsel =
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SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
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puts("CPU: Altera SoCFPGA Arria 10\n");
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printf("BOOT: %s\n", bsel_str[bsel].name);
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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return 0;
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}
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#endif
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