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Set ips dividor to 1/4 of csb clock.

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Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
This commit is contained in:
Grzegorz Bernacki 2008-01-16 15:12:47 +01:00 committed by Wolfgang Denk
parent 4c9e98ace7
commit 334e442e6f
1 changed files with 1 additions and 1 deletions
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2
include/mpc512x.h
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@ -185,7 +185,7 @@
/* SCFR1 System Clock Frequency Register 1 /* SCFR1 System Clock Frequency Register 1
*/ */
#define SCFR1_IPS_DIV 0x2 #define SCFR1_IPS_DIV 0x4
#define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_MASK 0x03800000
#define SCFR1_IPS_DIV_SHIFT 23 #define SCFR1_IPS_DIV_SHIFT 23