Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx
This commit is contained in:
Wolfgang Denk
commit
4c9e98ace7
@ -29,14 +29,13 @@ endif
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LIB = $(obj)lib$(VENDOR).a
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COBJS := sys_eeprom.o \
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pixis.o \
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pq-mds-pib.o \
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fsl_logo_bmp.o \
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fsl_diu_fb.o
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COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o
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COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o
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COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o
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COBJS-${CONFIG_FSL_PIXIS} += pixis.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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@ -27,8 +27,6 @@
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#include <i2c.h>
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#include <malloc.h>
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#ifdef CONFIG_FSL_DIU_FB
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#include "fsl_diu_fb.h"
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#ifdef DEBUG
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@ -615,4 +613,3 @@ void fsl_diu_clear_screen(void)
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memset(info->screen_base, 0, info->smem_len);
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}
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#endif /* CONFIG_FSL_DIU_FB */
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@ -25,9 +25,8 @@
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#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#ifdef CONFIG_FSL_PIXIS
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#include <asm/cache.h>
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#include "pixis.h"
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@ -184,7 +183,7 @@ int set_px_corepll(ulong corepll)
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void read_from_px_regs(int set)
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{
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u8 mask = 0x1C;
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u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
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if (set)
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@ -197,7 +196,7 @@ void read_from_px_regs(int set)
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void read_from_px_regs_altbank(int set)
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{
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u8 mask = 0x04;
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u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
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if (set)
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@ -208,15 +207,26 @@ void read_from_px_regs_altbank(int set)
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}
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#ifndef CFG_PIXIS_VBOOT_MASK
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#define CFG_PIXIS_VBOOT_MASK 0x40
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#define CFG_PIXIS_VBOOT_MASK (0x40)
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#endif
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void clear_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp &= ~CFG_PIXIS_VBOOT_MASK;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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void set_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp ^= CFG_PIXIS_VBOOT_MASK;
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tmp |= CFG_PIXIS_VBOOT_MASK;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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@ -227,11 +237,11 @@ void set_px_go(void)
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E;
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tmp = tmp & 0x1E; /* clear GO bit */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp | 0x01;
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tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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}
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@ -293,7 +303,7 @@ static ulong strfractoint(uchar *strptr)
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* simply create the intarr.
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*/
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i = 0;
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while (strptr[i] != 46) {
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while (strptr[i] != '.') {
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if (strptr[i] == 0) {
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no_dec = 1;
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break;
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@ -313,7 +323,7 @@ static ulong strfractoint(uchar *strptr)
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} else {
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j = 0;
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i++; /* Skipping the decimal point */
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while ((strptr[i] > 47) && (strptr[i] < 58)) {
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while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
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decarr[j] = strptr[i];
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i++;
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j++;
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@ -340,8 +350,14 @@ static ulong strfractoint(uchar *strptr)
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int
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pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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ulong val;
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ulong corepll;
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unsigned int i;
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char *p_cf = NULL;
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char *p_cf_sysclk = NULL;
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char *p_cf_corepll = NULL;
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char *p_cf_mpxpll = NULL;
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char *p_altbank = NULL;
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char *p_wd = NULL;
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unsigned int unknown_param = 0;
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/*
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* No args is a simple reset request.
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@ -351,116 +367,97 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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/* not reached */
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}
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if (strcmp(argv[1], "cf") == 0) {
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/*
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* Reset with frequency changed:
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* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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*/
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if (argc < 5) {
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puts(cmdtp->usage);
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return 1;
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}
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read_from_px_regs(0);
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val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
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corepll = strfractoint((uchar *)argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0 and VCTL\n");
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read_from_px_regs(1);
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puts("Resetting board with values from ");
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puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
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set_px_go();
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} else {
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puts(cmdtp->usage);
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return 1;
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}
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while (1) ; /* Not reached */
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} else if (strcmp(argv[1], "altbank") == 0) {
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/*
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* Reset using alternate flash bank:
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*/
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if (argv[2] == 0) {
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/*
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* Reset from alternate bank without changing
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* frequency and without watchdog timer enabled.
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* altbank
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if (argc > 2) {
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puts(cmdtp->usage);
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return 1;
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for (i = 1; i < argc; i++) {
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if (strcmp(argv[i], "cf") == 0) {
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p_cf = argv[i];
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if (i + 3 >= argc) {
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break;
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}
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puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Resetting board to boot from the other bank.\n");
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set_px_go();
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} else if (strcmp(argv[2], "cf") == 0) {
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/*
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* Reset with frequency changed
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* altbank cf <SYSCLK freq> <COREPLL ratio>
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* <MPXPLL ratio>
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
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corepll = strfractoint((uchar *)argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[5],
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NULL, 10));
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if (val == 3) {
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puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA\n");
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puts("Resetting board with values from ");
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puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
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puts("to boot from the other bank.\n");
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set_px_go_with_watchdog();
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} else {
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puts(cmdtp->usage);
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return 1;
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}
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while (1) ; /* Not reached */
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} else if (strcmp(argv[2], "wd") == 0) {
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/*
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* Reset from alternate bank without changing
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* frequencies but with watchdog timer enabled:
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* altbank wd
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*/
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs_altbank(1);
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puts("Enabling watchdog timer on the FPGA\n");
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puts("Resetting board to boot from the other bank.\n");
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set_px_go_with_watchdog();
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while (1) ; /* Not reached */
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} else {
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puts(cmdtp->usage);
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return 1;
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p_cf_sysclk = argv[i+1];
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p_cf_corepll = argv[i+2];
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p_cf_mpxpll = argv[i+3];
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i += 3;
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continue;
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}
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} else {
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puts(cmdtp->usage);
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if (strcmp(argv[i], "altbank") == 0) {
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p_altbank = argv[i];
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continue;
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}
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if (strcmp(argv[i], "wd") == 0) {
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p_wd = argv[i];
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continue;
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}
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unknown_param = 1;
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}
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/*
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* Check that cf has all required parms
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*/
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if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
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|| unknown_param) {
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puts(cmdtp->help);
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return 1;
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}
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/*
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* PIXIS seems to be sensitive to the ordering of
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* the registers that are touched.
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*/
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read_from_px_regs(0);
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if (p_altbank) {
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read_from_px_regs_altbank(0);
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}
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clear_altbank();
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/*
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* Clock configuration specified.
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*/
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if (p_cf) {
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unsigned long sysclk;
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unsigned long corepll;
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unsigned long mpxpll;
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sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
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corepll = strfractoint((uchar *) p_cf_corepll);
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mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
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if (!(set_px_sysclk(sysclk)
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&& set_px_corepll(corepll)
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&& set_px_mpxpll(mpxpll))) {
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puts(cmdtp->help);
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return 1;
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}
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read_from_px_regs(1);
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}
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/*
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* Altbank specified
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*
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* NOTE CHANGE IN BEHAVIOR: previous code would default
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* to enabling watchdog if altbank is specified.
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* Now the watchdog must be enabled explicitly using 'wd'.
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*/
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if (p_altbank) {
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set_altbank();
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read_from_px_regs_altbank(1);
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}
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/*
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* Reset with watchdog specified.
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*/
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if (p_wd) {
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set_px_go_with_watchdog();
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} else {
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set_px_go();
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}
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/*
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* Shouldn't be reached.
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*/
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return 0;
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}
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@ -474,4 +471,3 @@ U_BOOT_CMD(
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" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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);
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#endif /* CONFIG_FSL_PIXIS */
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@ -12,8 +12,6 @@
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#include <i2c.h>
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#include <asm/io.h>
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#ifdef CONFIG_PQ_MDS_PIB
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#include "pq-mds-pib.h"
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int pib_init(void)
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@ -102,4 +100,3 @@ int pib_init(void)
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i2c_set_bus_num(orig_i2c_bus);
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return 0;
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}
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#endif /* CONFIG_PQ_MDS_PIB */
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@ -27,7 +27,6 @@
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#include <i2c.h>
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#include <linux/ctype.h>
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#ifdef CFG_ID_EEPROM
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typedef struct {
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unsigned char id[4]; /* 0x0000 - 0x0003 */
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unsigned char sn[12]; /* 0x0004 - 0x000F */
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@ -253,4 +252,3 @@ int mac_read_from_eeprom(void)
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}
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return 0;
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}
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#endif /* CFG_ID_EEPROM */
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@ -27,14 +27,14 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o \
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../common/sys_eeprom.o \
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../common/pixis.o \
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mpc8610hpcd_diu.o \
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../common/fsl_diu_fb.o
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SOBJS := init.o
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COBJS := $(BOARD).o
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COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o
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COBJS += ${COBJS-y}
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -141,6 +141,9 @@
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#endif
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#define CFG_ID_EEPROM
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#ifdef CFG_ID_EEPROM
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#define CONFIG_ID_EEPROM
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#endif
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#define ID_EEPROM_ADDR 0x57
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@ -312,11 +315,8 @@
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#define CONFIG_CMD_NET
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_RTL8139
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#define CONFIG_SK98
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#define CONFIG_EEPRO100
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#define CONFIG_TULIP
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#ifdef CONFIG_TULIP
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#define CONFIG_ULI526X
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#ifdef CONFIG_ULI526X
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#define CONFIG_ETHADDR 00:E0:0C:00:00:01
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#endif
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@ -152,6 +152,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CFG_ID_EEPROM 1
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#ifdef CFG_ID_EEPROM
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#define CONFIG_ID_EEPROM
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#endif
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#define ID_EEPROM_ADDR 0x57
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/*
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