AX88180: new gigabit network driver
Signed-off-by: Louis Su <louis@asix.com.tw> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Louis Su
Ben Warren
parent
c9d6b69253
commit
30f5747172
@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libnet.a
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COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
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COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
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COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
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COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
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COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
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727
drivers/net/ax88180.c
Normal file
727
drivers/net/ax88180.c
Normal file
@ -0,0 +1,727 @@
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/*
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* ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
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*
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* This program is free software; you can distribute it and/or modify
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* it under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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* This program is distributed in the hope it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
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* USA.
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*/
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/*
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* ========================================================================
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* ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
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*
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* The AX88180 Ethernet controller is a high performance and highly
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* integrated local CPU bus Ethernet controller with embedded 40K bytes
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* SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
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* embedded systems.
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* The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
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* controller that supports both MII and RGMII interfaces and is
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* compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
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*
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* Please visit ASIX's web site (http://www.asix.com.tw) for more
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* details.
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*
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* Module Name : ax88180.c
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* Date : 2008-07-07
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* History
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* 09/06/2006 : New release for AX88180 US2 chip.
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* 07/07/2008 : Fix up the coding style and using inline functions
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* instead of macros
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* ========================================================================
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*/
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#include <common.h>
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#include <command.h>
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#include <net.h>
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#include <malloc.h>
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#include "ax88180.h"
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/*
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* ===========================================================================
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* Local SubProgram Declaration
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* ===========================================================================
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*/
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static void ax88180_rx_handler (struct eth_device *dev);
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static int ax88180_phy_initial (struct eth_device *dev);
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static void ax88180_meidia_config (struct eth_device *dev);
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static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev);
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static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev);
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static unsigned short ax88180_mdio_read (struct eth_device *dev,
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unsigned long regaddr);
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static void ax88180_mdio_write (struct eth_device *dev,
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unsigned long regaddr, unsigned short regdata);
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/*
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* ===========================================================================
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* Local SubProgram Bodies
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* ===========================================================================
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*/
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static int ax88180_mdio_check_complete (struct eth_device *dev)
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{
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int us_cnt = 10000;
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unsigned short tmpval;
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/* MDIO read/write should not take more than 10 ms */
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while (--us_cnt) {
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tmpval = INW (dev, MDIOCTRL);
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if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
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break;
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}
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return us_cnt;
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}
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static unsigned short
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ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
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{
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struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
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unsigned long tmpval = 0;
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OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
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if (ax88180_mdio_check_complete (dev))
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tmpval = INW (dev, MDIODP);
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else
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printf ("Failed to read PHY register!\n");
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return (unsigned short)(tmpval & 0xFFFF);
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}
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static void
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ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
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unsigned short regdata)
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{
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struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
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OUTW (dev, regdata, MDIODP);
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OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
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if (!ax88180_mdio_check_complete (dev))
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printf ("Failed to write PHY register!\n");
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}
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static int ax88180_phy_reset (struct eth_device *dev)
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{
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unsigned short delay_cnt = 500;
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ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN));
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/* Wait for the reset to complete, or time out (500 ms) */
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while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) {
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udelay (1000);
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if (--delay_cnt == 0) {
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printf ("Failed to reset PHY!\n");
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return -1;
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}
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}
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return 0;
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}
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static void ax88180_mac_reset (struct eth_device *dev)
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{
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unsigned long tmpval;
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unsigned char i;
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struct {
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unsigned short offset, value;
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} program_seq[] = {
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{
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MISC, MISC_NORMAL}, {
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RXINDICATOR, DEFAULT_RXINDICATOR}, {
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TXCMD, DEFAULT_TXCMD}, {
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TXBS, DEFAULT_TXBS}, {
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TXDES0, DEFAULT_TXDES0}, {
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TXDES1, DEFAULT_TXDES1}, {
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TXDES2, DEFAULT_TXDES2}, {
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TXDES3, DEFAULT_TXDES3}, {
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TXCFG, DEFAULT_TXCFG}, {
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MACCFG2, DEFAULT_MACCFG2}, {
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MACCFG3, DEFAULT_MACCFG3}, {
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TXLEN, DEFAULT_TXLEN}, {
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RXBTHD0, DEFAULT_RXBTHD0}, {
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RXBTHD1, DEFAULT_RXBTHD1}, {
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RXFULTHD, DEFAULT_RXFULTHD}, {
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DOGTHD0, DEFAULT_DOGTHD0}, {
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DOGTHD1, DEFAULT_DOGTHD1},};
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OUTW (dev, MISC_RESET_MAC, MISC);
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tmpval = INW (dev, MISC);
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for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++)
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OUTW (dev, program_seq[i].value, program_seq[i].offset);
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}
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static int ax88180_poll_tx_complete (struct eth_device *dev)
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{
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struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
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unsigned long tmpval, txbs_txdp;
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int TimeOutCnt = 10000;
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txbs_txdp = 1 << priv->NextTxDesc;
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while (TimeOutCnt--) {
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tmpval = INW (dev, TXBS);
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if ((tmpval & txbs_txdp) == 0)
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break;
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udelay (100);
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}
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if (TimeOutCnt)
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return 0;
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else
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return -TimeOutCnt;
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}
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static void ax88180_rx_handler (struct eth_device *dev)
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{
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struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
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unsigned long data_size;
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unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
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int i;
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#if defined (CONFIG_DRIVER_AX88180_16BIT)
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unsigned short *rxdata = (unsigned short *)NetRxPackets[0];
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#else
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unsigned long *rxdata = (unsigned long *)NetRxPackets[0];
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#endif
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unsigned short count;
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rxcurt_ptr = INW (dev, RXCURT);
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rxbound_ptr = INW (dev, RXBOUND);
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next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
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debug ("ax88180: RX original RXBOUND=0x%04x,"
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" RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
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while (next_ptr != rxcurt_ptr) {
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OUTW (dev, RX_START_READ, RXINDICATOR);
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data_size = READ_RXBUF (dev) & 0xFFFF;
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if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
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OUTW (dev, RX_STOP_READ, RXINDICATOR);
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ax88180_mac_reset (dev);
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printf ("ax88180: Invalid Rx packet length!"
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" (len=0x%04lx)\n", data_size);
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debug ("ax88180: RX RXBOUND=0x%04x,"
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"RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
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return;
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}
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rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
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rxbound_ptr &= RX_PAGE_NUM_MASK;
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/* Comput access times */
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count = (data_size + priv->PadSize) >> priv->BusWidth;
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for (i = 0; i < count; i++) {
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*(rxdata + i) = READ_RXBUF (dev);
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}
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OUTW (dev, RX_STOP_READ, RXINDICATOR);
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/* Pass the packet up to the protocol layers. */
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NetReceive (NetRxPackets[0], data_size);
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OUTW (dev, rxbound_ptr, RXBOUND);
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rxcurt_ptr = INW (dev, RXCURT);
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rxbound_ptr = INW (dev, RXBOUND);
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next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
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debug ("ax88180: RX updated RXBOUND=0x%04x,"
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"RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
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}
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return;
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}
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static int ax88180_phy_initial (struct eth_device *dev)
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{
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struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
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unsigned long tmp_regval;
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/* Check avaliable PHY chipset */
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priv->PhyAddr = MARVELL_88E1111_PHYADDR;
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priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
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if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
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debug ("ax88180: Found Marvell 88E1111 PHY."
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" (PHY Addr=0x%x)\n", priv->PhyAddr);
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tmp_regval = ax88180_mdio_read (dev, M88_EXT_SSR);
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if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) {
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ax88180_mdio_write (dev, M88_EXT_SCR, DEFAULT_EXT_SCR);
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if (ax88180_phy_reset (dev) < 0)
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return 0;
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ax88180_mdio_write (dev, M88_IER, LINK_CHANGE_INT);
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}
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} else {
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priv->PhyAddr = CICADA_CIS8201_PHYADDR;
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priv->PhyID0 = ax88180_mdio_read (dev, PHYIDR0);
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if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
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debug ("ax88180: Found CICADA CIS8201 PHY"
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" chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
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ax88180_mdio_write (dev, CIS_IMR,
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(CIS_INT_ENABLE | LINK_CHANGE_INT));
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/* Set CIS_SMI_PRIORITY bit before force the media mode */
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tmp_regval =
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ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
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tmp_regval &= ~CIS_SMI_PRIORITY;
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ax88180_mdio_write (dev, CIS_AUX_CTRL_STATUS,
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tmp_regval);
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} else {
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printf ("ax88180: Unknown PHY chipset!!\n");
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return 0;
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}
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}
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return 1;
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}
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static void ax88180_meidia_config (struct eth_device *dev)
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{
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struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
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unsigned long bmcr_val, bmsr_val;
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unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
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unsigned long RealMediaMode;
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int i;
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/* Waiting 2 seconds for PHY link stable */
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for (i = 0; i < 20000; i++) {
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bmsr_val = ax88180_mdio_read (dev, BMSR);
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if (bmsr_val & LINKOK) {
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break;
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}
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udelay (100);
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}
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bmsr_val = ax88180_mdio_read (dev, BMSR);
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debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
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if (bmsr_val & LINKOK) {
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bmcr_val = ax88180_mdio_read (dev, BMCR);
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if (bmcr_val & AUTONEG_EN) {
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/*
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* Waiting for Auto-negotiation completion, this may
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* take up to 5 seconds.
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*/
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debug ("ax88180: Auto-negotiation is "
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"enabled. Waiting for NWay completion..\n");
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for (i = 0; i < 50000; i++) {
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bmsr_val = ax88180_mdio_read (dev, BMSR);
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if (bmsr_val & AUTONEG_COMPLETE) {
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break;
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}
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udelay (100);
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}
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} else
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debug ("ax88180: Auto-negotiation is disabled.\n");
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debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
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(unsigned int)bmcr_val, (unsigned int)bmsr_val);
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/* Get real media mode here */
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if (priv->PhyID0 == MARVELL_88E1111_PHYIDR0) {
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RealMediaMode = get_MarvellPHY_meida_mode (dev);
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} else if (priv->PhyID0 == CICADA_CIS8201_PHYIDR0) {
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RealMediaMode = get_CicadaPHY_meida_mode (dev);
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} else {
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RealMediaMode = MEDIA_1000FULL;
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}
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priv->LinkState = INS_LINK_UP;
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switch (RealMediaMode) {
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case MEDIA_1000FULL:
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debug ("ax88180: 1000Mbps Full-duplex mode.\n");
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rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
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maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
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maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
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FULLDUPLEX | DEFAULT_MACCFG1;
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break;
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case MEDIA_1000HALF:
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debug ("ax88180: 1000Mbps Half-duplex mode.\n");
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rxcfg_val = DEFAULT_RXCFG;
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maccfg0_val = DEFAULT_MACCFG0;
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maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
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break;
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case MEDIA_100FULL:
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debug ("ax88180: 100Mbps Full-duplex mode.\n");
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rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
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maccfg0_val = SPEED100 | TXFLOW_ENABLE
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| DEFAULT_MACCFG0;
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maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
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break;
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case MEDIA_100HALF:
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debug ("ax88180: 100Mbps Half-duplex mode.\n");
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rxcfg_val = DEFAULT_RXCFG;
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maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
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maccfg1_val = DEFAULT_MACCFG1;
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break;
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case MEDIA_10FULL:
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debug ("ax88180: 10Mbps Full-duplex mode.\n");
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rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
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maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
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maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
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break;
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case MEDIA_10HALF:
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debug ("ax88180: 10Mbps Half-duplex mode.\n");
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rxcfg_val = DEFAULT_RXCFG;
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maccfg0_val = DEFAULT_MACCFG0;
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maccfg1_val = DEFAULT_MACCFG1;
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break;
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default:
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debug ("ax88180: Unknow media mode.\n");
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rxcfg_val = DEFAULT_RXCFG;
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maccfg0_val = DEFAULT_MACCFG0;
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maccfg1_val = DEFAULT_MACCFG1;
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priv->LinkState = INS_LINK_DOWN;
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break;
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}
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} else {
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rxcfg_val = DEFAULT_RXCFG;
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maccfg0_val = DEFAULT_MACCFG0;
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maccfg1_val = DEFAULT_MACCFG1;
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priv->LinkState = INS_LINK_DOWN;
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}
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OUTW (dev, rxcfg_val, RXCFG);
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OUTW (dev, maccfg0_val, MACCFG0);
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OUTW (dev, maccfg1_val, MACCFG1);
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return;
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}
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static unsigned long get_MarvellPHY_meida_mode (struct eth_device *dev)
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{
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unsigned long m88_ssr;
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unsigned long MediaMode;
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m88_ssr = ax88180_mdio_read (dev, M88_SSR);
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switch (m88_ssr & SSR_MEDIA_MASK) {
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case SSR_1000FULL:
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MediaMode = MEDIA_1000FULL;
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break;
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case SSR_1000HALF:
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MediaMode = MEDIA_1000HALF;
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break;
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case SSR_100FULL:
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MediaMode = MEDIA_100FULL;
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break;
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case SSR_100HALF:
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MediaMode = MEDIA_100HALF;
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break;
|
||||
case SSR_10FULL:
|
||||
MediaMode = MEDIA_10FULL;
|
||||
break;
|
||||
case SSR_10HALF:
|
||||
MediaMode = MEDIA_10HALF;
|
||||
break;
|
||||
default:
|
||||
MediaMode = MEDIA_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
return MediaMode;
|
||||
}
|
||||
|
||||
static unsigned long get_CicadaPHY_meida_mode (struct eth_device *dev)
|
||||
{
|
||||
unsigned long tmp_regval;
|
||||
unsigned long MediaMode;
|
||||
|
||||
tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
|
||||
switch (tmp_regval & CIS_MEDIA_MASK) {
|
||||
case CIS_1000FULL:
|
||||
MediaMode = MEDIA_1000FULL;
|
||||
break;
|
||||
case CIS_1000HALF:
|
||||
MediaMode = MEDIA_1000HALF;
|
||||
break;
|
||||
case CIS_100FULL:
|
||||
MediaMode = MEDIA_100FULL;
|
||||
break;
|
||||
case CIS_100HALF:
|
||||
MediaMode = MEDIA_100HALF;
|
||||
break;
|
||||
case CIS_10FULL:
|
||||
MediaMode = MEDIA_10FULL;
|
||||
break;
|
||||
case CIS_10HALF:
|
||||
MediaMode = MEDIA_10HALF;
|
||||
break;
|
||||
default:
|
||||
MediaMode = MEDIA_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
return MediaMode;
|
||||
}
|
||||
|
||||
static void ax88180_halt (struct eth_device *dev)
|
||||
{
|
||||
/* Disable AX88180 TX/RX functions */
|
||||
OUTW (dev, WAKEMOD, CMD);
|
||||
}
|
||||
|
||||
static int ax88180_init (struct eth_device *dev, bd_t * bd)
|
||||
{
|
||||
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
|
||||
unsigned short tmp_regval;
|
||||
|
||||
ax88180_mac_reset (dev);
|
||||
|
||||
/* Disable interrupt */
|
||||
OUTW (dev, CLEAR_IMR, IMR);
|
||||
|
||||
/* Disable AX88180 TX/RX functions */
|
||||
OUTW (dev, WAKEMOD, CMD);
|
||||
|
||||
/* Fill the MAC address */
|
||||
tmp_regval =
|
||||
dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
|
||||
OUTW (dev, tmp_regval, MACID0);
|
||||
|
||||
tmp_regval =
|
||||
dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
|
||||
OUTW (dev, tmp_regval, MACID1);
|
||||
|
||||
tmp_regval =
|
||||
dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
|
||||
OUTW (dev, tmp_regval, MACID2);
|
||||
|
||||
ax88180_meidia_config (dev);
|
||||
|
||||
OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
|
||||
|
||||
/* Initial variables here */
|
||||
priv->FirstTxDesc = TXDP0;
|
||||
priv->NextTxDesc = TXDP0;
|
||||
|
||||
/* Check if there is any invalid interrupt status and clear it. */
|
||||
OUTW (dev, INW (dev, ISR), ISR);
|
||||
|
||||
/* Start AX88180 TX/RX functions */
|
||||
OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get a data block via Ethernet */
|
||||
static int ax88180_recv (struct eth_device *dev)
|
||||
{
|
||||
unsigned short ISR_Status;
|
||||
unsigned short tmp_regval;
|
||||
|
||||
/* Read and check interrupt status here. */
|
||||
ISR_Status = INW (dev, ISR);
|
||||
|
||||
while (ISR_Status) {
|
||||
/* Clear the interrupt status */
|
||||
OUTW (dev, ISR_Status, ISR);
|
||||
|
||||
debug ("\nax88180: The interrupt status = 0x%04x\n",
|
||||
ISR_Status);
|
||||
|
||||
if (ISR_Status & ISR_PHY) {
|
||||
/* Read ISR register once to clear PHY interrupt bit */
|
||||
tmp_regval = ax88180_mdio_read (dev, M88_ISR);
|
||||
ax88180_meidia_config (dev);
|
||||
}
|
||||
|
||||
if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
|
||||
ax88180_rx_handler (dev);
|
||||
}
|
||||
|
||||
/* Read and check interrupt status again */
|
||||
ISR_Status = INW (dev, ISR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Send a data block via Ethernet. */
|
||||
static int
|
||||
ax88180_send (struct eth_device *dev, volatile void *packet, int length)
|
||||
{
|
||||
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
|
||||
unsigned short TXDES_addr;
|
||||
unsigned short txcmd_txdp, txbs_txdp;
|
||||
unsigned short tmp_data;
|
||||
int i;
|
||||
#if defined (CONFIG_DRIVER_AX88180_16BIT)
|
||||
volatile unsigned short *txdata = (volatile unsigned short *)packet;
|
||||
#else
|
||||
volatile unsigned long *txdata = (volatile unsigned long *)packet;
|
||||
#endif
|
||||
unsigned short count;
|
||||
|
||||
if (priv->LinkState != INS_LINK_UP) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
priv->FirstTxDesc = priv->NextTxDesc;
|
||||
txbs_txdp = 1 << priv->FirstTxDesc;
|
||||
|
||||
debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
|
||||
|
||||
txcmd_txdp = priv->FirstTxDesc << 13;
|
||||
TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
|
||||
|
||||
OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
|
||||
|
||||
/* Comput access times */
|
||||
count = (length + priv->PadSize) >> priv->BusWidth;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
WRITE_TXBUF (dev, *(txdata + i));
|
||||
}
|
||||
|
||||
OUTW (dev, txcmd_txdp | length, TXCMD);
|
||||
OUTW (dev, txbs_txdp, TXBS);
|
||||
OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
|
||||
|
||||
priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
|
||||
|
||||
/*
|
||||
* Check the available transmit descriptor, if we had exhausted all
|
||||
* transmit descriptor ,then we have to wait for at least one free
|
||||
* descriptor
|
||||
*/
|
||||
txbs_txdp = 1 << priv->NextTxDesc;
|
||||
tmp_data = INW (dev, TXBS);
|
||||
|
||||
if (tmp_data & txbs_txdp) {
|
||||
if (ax88180_poll_tx_complete (dev) < 0) {
|
||||
ax88180_mac_reset (dev);
|
||||
priv->FirstTxDesc = TXDP0;
|
||||
priv->NextTxDesc = TXDP0;
|
||||
printf ("ax88180: Transmit time out occurred!\n");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ax88180_read_mac_addr (struct eth_device *dev)
|
||||
{
|
||||
unsigned short macid0_val, macid1_val, macid2_val;
|
||||
unsigned short tmp_regval;
|
||||
unsigned short i;
|
||||
|
||||
/* Reload MAC address from EEPROM */
|
||||
OUTW (dev, RELOAD_EEPROM, PROMCTRL);
|
||||
|
||||
/* Waiting for reload eeprom completion */
|
||||
for (i = 0; i < 500; i++) {
|
||||
tmp_regval = INW (dev, PROMCTRL);
|
||||
if ((tmp_regval & RELOAD_EEPROM) == 0)
|
||||
break;
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
/* Get MAC addresses */
|
||||
macid0_val = INW (dev, MACID0);
|
||||
macid1_val = INW (dev, MACID1);
|
||||
macid2_val = INW (dev, MACID2);
|
||||
|
||||
if (((macid0_val | macid1_val | macid2_val) != 0) &&
|
||||
((macid0_val & 0x01) == 0)) {
|
||||
dev->enetaddr[0] = (unsigned char)macid0_val;
|
||||
dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
|
||||
dev->enetaddr[2] = (unsigned char)macid1_val;
|
||||
dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
|
||||
dev->enetaddr[4] = (unsigned char)macid2_val;
|
||||
dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
===========================================================================
|
||||
<<<<<< Exported SubProgram Bodies >>>>>>
|
||||
===========================================================================
|
||||
*/
|
||||
int ax88180_initialize (bd_t * bis)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
struct ax88180_private *priv;
|
||||
|
||||
dev = (struct eth_device *)malloc (sizeof *dev);
|
||||
|
||||
if (NULL == dev)
|
||||
return 0;
|
||||
|
||||
memset (dev, 0, sizeof *dev);
|
||||
|
||||
priv = (struct ax88180_private *)malloc (sizeof (*priv));
|
||||
|
||||
if (NULL == priv)
|
||||
return 0;
|
||||
|
||||
memset (priv, 0, sizeof *priv);
|
||||
|
||||
sprintf (dev->name, "ax88180");
|
||||
dev->iobase = AX88180_BASE;
|
||||
dev->priv = priv;
|
||||
dev->init = ax88180_init;
|
||||
dev->halt = ax88180_halt;
|
||||
dev->send = ax88180_send;
|
||||
dev->recv = ax88180_recv;
|
||||
|
||||
priv->BusWidth = BUS_WIDTH_32;
|
||||
priv->PadSize = 3;
|
||||
#if defined (CONFIG_DRIVER_AX88180_16BIT)
|
||||
OUTW (dev, (START_BASE >> 8), BASE);
|
||||
OUTW (dev, DECODE_EN, DECODE);
|
||||
|
||||
priv->BusWidth = BUS_WIDTH_16;
|
||||
priv->PadSize = 1;
|
||||
#endif
|
||||
|
||||
ax88180_mac_reset (dev);
|
||||
|
||||
/* Disable interrupt */
|
||||
OUTW (dev, CLEAR_IMR, IMR);
|
||||
|
||||
/* Disable AX88180 TX/RX functions */
|
||||
OUTW (dev, WAKEMOD, CMD);
|
||||
|
||||
ax88180_read_mac_addr (dev);
|
||||
|
||||
eth_register (dev);
|
||||
|
||||
return ax88180_phy_initial (dev);
|
||||
|
||||
}
|
||||
412
drivers/net/ax88180.h
Normal file
412
drivers/net/ax88180.h
Normal file
@ -0,0 +1,412 @@
|
||||
/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
|
||||
/*
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _AX88180_H_
|
||||
#define _AX88180_H_
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <config.h>
|
||||
|
||||
typedef enum _ax88180_link_state {
|
||||
INS_LINK_DOWN,
|
||||
INS_LINK_UP,
|
||||
INS_LINK_UNKNOWN
|
||||
} ax88180_link_state;
|
||||
|
||||
struct ax88180_private {
|
||||
unsigned char BusWidth;
|
||||
unsigned char PadSize;
|
||||
unsigned short PhyAddr;
|
||||
unsigned short PhyID0;
|
||||
unsigned short FirstTxDesc;
|
||||
unsigned short NextTxDesc;
|
||||
ax88180_link_state LinkState;
|
||||
};
|
||||
|
||||
#define BUS_WIDTH_16 1
|
||||
#define BUS_WIDTH_32 2
|
||||
|
||||
#define ENABLE_JUMBO 1
|
||||
#define DISABLE_JUMBO 0
|
||||
|
||||
#define ENABLE_BURST 1
|
||||
#define DISABLE_BURST 0
|
||||
|
||||
#define NORMAL_RX_MODE 0
|
||||
#define RX_LOOPBACK_MODE 1
|
||||
#define RX_INIFINIT_LOOP_MODE 2
|
||||
#define TX_INIFINIT_LOOP_MODE 3
|
||||
|
||||
#define DEFAULT_ETH_MTU 1500
|
||||
|
||||
/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
|
||||
#define MAX_JUMBO_MTU 4072
|
||||
|
||||
/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
|
||||
#define MAX_TX_JUMBO_SIZE 4086
|
||||
|
||||
/* Max Rx Jumbo size is 15K Bytes */
|
||||
#define MAX_RX_SIZE 0x3C00
|
||||
|
||||
#define MARVELL_88E1111_PHYADDR 0x18
|
||||
#define MARVELL_88E1111_PHYIDR0 0x0141
|
||||
|
||||
#define CICADA_CIS8201_PHYADDR 0x01
|
||||
#define CICADA_CIS8201_PHYIDR0 0x000F
|
||||
|
||||
#define MEDIA_AUTO 0
|
||||
#define MEDIA_1000FULL 1
|
||||
#define MEDIA_1000HALF 2
|
||||
#define MEDIA_100FULL 3
|
||||
#define MEDIA_100HALF 4
|
||||
#define MEDIA_10FULL 5
|
||||
#define MEDIA_10HALF 6
|
||||
#define MEDIA_UNKNOWN 7
|
||||
|
||||
#define AUTO_MEDIA 0
|
||||
#define FORCE_MEDIA 1
|
||||
|
||||
#define TXDP_MASK 3
|
||||
#define TXDP0 0
|
||||
#define TXDP1 1
|
||||
#define TXDP2 2
|
||||
#define TXDP3 3
|
||||
|
||||
#define CMD_MAP_SIZE 0x100
|
||||
|
||||
#if defined (CONFIG_DRIVER_AX88180_16BIT)
|
||||
#define AX88180_MEMORY_SIZE 0x00004000
|
||||
#define START_BASE 0x1000
|
||||
|
||||
#define RX_BUF_SIZE 0x1000
|
||||
#define TX_BUF_SIZE 0x0F00
|
||||
|
||||
#define TX_BASE START_BASE
|
||||
#define CMD_BASE (TX_BASE + TX_BUF_SIZE)
|
||||
#define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
|
||||
#else
|
||||
#define AX88180_MEMORY_SIZE 0x00010000
|
||||
|
||||
#define RX_BUF_SIZE 0x8000
|
||||
#define TX_BUF_SIZE 0x7C00
|
||||
|
||||
#define RX_BASE 0x0000
|
||||
#define TX_BASE (RX_BASE + RX_BUF_SIZE)
|
||||
#define CMD_BASE (TX_BASE + TX_BUF_SIZE)
|
||||
#endif
|
||||
|
||||
/* AX88180 Memory Mapping Definition */
|
||||
#define RXBUFFER_START RX_BASE
|
||||
#define RX_PACKET_LEN_OFFSET 0
|
||||
#define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
|
||||
#define TXBUFFER_START TX_BASE
|
||||
|
||||
/* AX88180 MAC Register Definition */
|
||||
#define DECODE (0)
|
||||
#define DECODE_EN 0x00000001
|
||||
#define BASE (6)
|
||||
#define CMD (CMD_BASE + 0x0000)
|
||||
#define WAKEMOD 0x00000001
|
||||
#define TXEN 0x00000100
|
||||
#define RXEN 0x00000200
|
||||
#define DEFAULT_CMD WAKEMOD
|
||||
#define IMR (CMD_BASE + 0x0004)
|
||||
#define IMR_RXBUFFOVR 0x00000001
|
||||
#define IMR_WATCHDOG 0x00000002
|
||||
#define IMR_TX 0x00000008
|
||||
#define IMR_RX 0x00000010
|
||||
#define IMR_PHY 0x00000020
|
||||
#define CLEAR_IMR 0x00000000
|
||||
#define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
|
||||
IMR_RXBUFFOVR | IMR_WATCHDOG)
|
||||
#define ISR (CMD_BASE + 0x0008)
|
||||
#define ISR_RXBUFFOVR 0x00000001
|
||||
#define ISR_WATCHDOG 0x00000002
|
||||
#define ISR_TX 0x00000008
|
||||
#define ISR_RX 0x00000010
|
||||
#define ISR_PHY 0x00000020
|
||||
#define TXCFG (CMD_BASE + 0x0010)
|
||||
#define AUTOPAD_CRC 0x00000050
|
||||
#define DEFAULT_TXCFG AUTOPAD_CRC
|
||||
#define TXCMD (CMD_BASE + 0x0014)
|
||||
#define TXCMD_TXDP_MASK 0x00006000
|
||||
#define TXCMD_TXDP0 0x00000000
|
||||
#define TXCMD_TXDP1 0x00002000
|
||||
#define TXCMD_TXDP2 0x00004000
|
||||
#define TXCMD_TXDP3 0x00006000
|
||||
#define TX_START_WRITE 0x00008000
|
||||
#define TX_STOP_WRITE 0x00000000
|
||||
#define DEFAULT_TXCMD 0x00000000
|
||||
#define TXBS (CMD_BASE + 0x0018)
|
||||
#define TXDP0_USED 0x00000001
|
||||
#define TXDP1_USED 0x00000002
|
||||
#define TXDP2_USED 0x00000004
|
||||
#define TXDP3_USED 0x00000008
|
||||
#define DEFAULT_TXBS 0x00000000
|
||||
#define TXDES0 (CMD_BASE + 0x0020)
|
||||
#define TXDPx_ENABLE 0x00008000
|
||||
#define TXDPx_LEN_MASK 0x00001FFF
|
||||
#define DEFAULT_TXDES0 0x00000000
|
||||
#define TXDES1 (CMD_BASE + 0x0024)
|
||||
#define TXDPx_ENABLE 0x00008000
|
||||
#define TXDPx_LEN_MASK 0x00001FFF
|
||||
#define DEFAULT_TXDES1 0x00000000
|
||||
#define TXDES2 (CMD_BASE + 0x0028)
|
||||
#define TXDPx_ENABLE 0x00008000
|
||||
#define TXDPx_LEN_MASK 0x00001FFF
|
||||
#define DEFAULT_TXDES2 0x00000000
|
||||
#define TXDES3 (CMD_BASE + 0x002C)
|
||||
#define TXDPx_ENABLE 0x00008000
|
||||
#define TXDPx_LEN_MASK 0x00001FFF
|
||||
#define DEFAULT_TXDES3 0x00000000
|
||||
#define RXCFG (CMD_BASE + 0x0030)
|
||||
#define RXBUFF_PROTECT 0x00000001
|
||||
#define RXTCPCRC_CHECK 0x00000010
|
||||
#define RXFLOW_ENABLE 0x00000100
|
||||
#define DEFAULT_RXCFG RXBUFF_PROTECT
|
||||
#define RXCURT (CMD_BASE + 0x0034)
|
||||
#define DEFAULT_RXCURT 0x00000000
|
||||
#define RXBOUND (CMD_BASE + 0x0038)
|
||||
#define DEFAULT_RXBOUND 0x7FF //RX pages 0~7FFh
|
||||
#define MACCFG0 (CMD_BASE + 0x0040)
|
||||
#define MACCFG0_BIT3_0 0x00000007
|
||||
#define IPGT_VAL 0x00000150
|
||||
#define TXFLOW_ENABLE 0x00001000
|
||||
#define SPEED100 0x00008000
|
||||
#define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
|
||||
#define MACCFG1 (CMD_BASE + 0x0044)
|
||||
#define RGMII_EN 0x00000002
|
||||
#define RXFLOW_EN 0x00000020
|
||||
#define FULLDUPLEX 0x00000040
|
||||
#define MAX_JUMBO_LEN 0x00000780
|
||||
#define RXJUMBO_EN 0x00000800
|
||||
#define GIGA_MODE_EN 0x00001000
|
||||
#define RXCRC_CHECK 0x00002000
|
||||
#define RXPAUSE_DA_CHECK 0x00004000
|
||||
|
||||
#define JUMBO_LEN_4K 0x00000200
|
||||
#define JUMBO_LEN_15K 0x00000780
|
||||
#define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
|
||||
RGMII_EN)
|
||||
#define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
|
||||
#define MACCFG2 (CMD_BASE + 0x0048)
|
||||
#define MACCFG2_BIT15_8 0x00000100
|
||||
#define JAM_LIMIT_MASK 0x000000FC
|
||||
#define DEFAULT_JAM_LIMIT 0x00000064
|
||||
#define DEFAULT_MACCFG2 MACCFG2_BIT15_8
|
||||
#define MACCFG3 (CMD_BASE + 0x004C)
|
||||
#define IPGR2_VAL 0x0000000E
|
||||
#define IPGR1_VAL 0x00000600
|
||||
#define NOABORT 0x00008000
|
||||
#define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
|
||||
#define TXPAUT (CMD_BASE + 0x0054)
|
||||
#define DEFAULT_TXPAUT 0x001FE000
|
||||
#define RXBTHD0 (CMD_BASE + 0x0058)
|
||||
#define DEFAULT_RXBTHD0 0x00000300
|
||||
#define RXBTHD1 (CMD_BASE + 0x005C)
|
||||
#define DEFAULT_RXBTHD1 0x00000600
|
||||
#define RXFULTHD (CMD_BASE + 0x0060)
|
||||
#define DEFAULT_RXFULTHD 0x00000100
|
||||
#define MISC (CMD_BASE + 0x0068)
|
||||
/* Normal operation mode */
|
||||
#define MISC_NORMAL 0x00000003
|
||||
/* Clear bit 0 to reset MAC */
|
||||
#define MISC_RESET_MAC 0x00000002
|
||||
/* Clear bit 1 to reset PHY */
|
||||
#define MISC_RESET_PHY 0x00000001
|
||||
/* Clear bit 0 and 1 to reset MAC and PHY */
|
||||
#define MISC_RESET_MAC_PHY 0x00000000
|
||||
#define DEFAULT_MISC MISC_NORMAL
|
||||
#define MACID0 (CMD_BASE + 0x0070)
|
||||
#define MACID1 (CMD_BASE + 0x0074)
|
||||
#define MACID2 (CMD_BASE + 0x0078)
|
||||
#define TXLEN (CMD_BASE + 0x007C)
|
||||
#define DEFAULT_TXLEN 0x000005FC
|
||||
#define RXFILTER (CMD_BASE + 0x0080)
|
||||
#define RX_RXANY 0x00000001
|
||||
#define RX_MULTICAST 0x00000002
|
||||
#define RX_UNICAST 0x00000004
|
||||
#define RX_BROADCAST 0x00000008
|
||||
#define RX_MULTI_HASH 0x00000010
|
||||
#define DISABLE_RXFILTER 0x00000000
|
||||
#define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
|
||||
#define MDIOCTRL (CMD_BASE + 0x0084)
|
||||
#define PHY_ADDR_MASK 0x0000001F
|
||||
#define REG_ADDR_MASK 0x00001F00
|
||||
#define READ_PHY 0x00004000
|
||||
#define WRITE_PHY 0x00008000
|
||||
#define MDIODP (CMD_BASE + 0x0088)
|
||||
#define GPIOCTRL (CMD_BASE + 0x008C)
|
||||
#define RXINDICATOR (CMD_BASE + 0x0090)
|
||||
#define RX_START_READ 0x00000001
|
||||
#define RX_STOP_READ 0x00000000
|
||||
#define DEFAULT_RXINDICATOR RX_STOP_READ
|
||||
#define TXST (CMD_BASE + 0x0094)
|
||||
#define MDCCLKPAT (CMD_BASE + 0x00A0)
|
||||
#define RXIPCRCCNT (CMD_BASE + 0x00A4)
|
||||
#define RXCRCCNT (CMD_BASE + 0x00A8)
|
||||
#define TXFAILCNT (CMD_BASE + 0x00AC)
|
||||
#define PROMDP (CMD_BASE + 0x00B0)
|
||||
#define PROMCTRL (CMD_BASE + 0x00B4)
|
||||
#define RELOAD_EEPROM 0x00000200
|
||||
#define MAXRXLEN (CMD_BASE + 0x00B8)
|
||||
#define HASHTAB0 (CMD_BASE + 0x00C0)
|
||||
#define HASHTAB1 (CMD_BASE + 0x00C4)
|
||||
#define HASHTAB2 (CMD_BASE + 0x00C8)
|
||||
#define HASHTAB3 (CMD_BASE + 0x00CC)
|
||||
#define DOGTHD0 (CMD_BASE + 0x00E0)
|
||||
#define DEFAULT_DOGTHD0 0x0000FFFF
|
||||
#define DOGTHD1 (CMD_BASE + 0x00E4)
|
||||
#define START_WATCHDOG_TIMER 0x00008000
|
||||
#define DEFAULT_DOGTHD1 0x00000FFF
|
||||
#define SOFTRST (CMD_BASE + 0x00EC)
|
||||
#define SOFTRST_NORMAL 0x00000003
|
||||
#define SOFTRST_RESET_MAC 0x00000002
|
||||
|
||||
/* External PHY Register Definition */
|
||||
#define BMCR 0x0000
|
||||
#define LINE_SPEED_MSB 0x0040
|
||||
#define DUPLEX_MODE 0x0100
|
||||
#define RESTART_AUTONEG 0x0200
|
||||
#define POWER_DOWN 0x0800
|
||||
#define AUTONEG_EN 0x1000
|
||||
#define LINE_SPEED_LSB 0x2000
|
||||
#define PHY_RESET 0x8000
|
||||
|
||||
#define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\
|
||||
DUPLEX_MODE)
|
||||
#define BMCR_SPEED_1000 LINE_SPEED_MSB
|
||||
#define BMCR_SPEED_100 LINE_SPEED_LSB
|
||||
#define BMCR_SPEED_10 0x0000
|
||||
|
||||
#define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE)
|
||||
#define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE)
|
||||
#define BMCR_100HALF BMCR_SPEED_100
|
||||
#define BMCR_10FULL DUPLEX_MODE
|
||||
#define BMCR_10HALF 0x0000
|
||||
#define BMSR 0x0001
|
||||
#define LINKOK 0x0004
|
||||
#define AUTONEG_ENABLE_STS 0x0008
|
||||
#define AUTONEG_COMPLETE 0x0020
|
||||
#define PHYIDR0 0x0002
|
||||
#define PHYIDR1 0x0003
|
||||
#define ANAR 0x0004
|
||||
#define ANAR_PAUSE 0x0400
|
||||
#define ANAR_100FULL 0x0100
|
||||
#define ANAR_100HALF 0x0080
|
||||
#define ANAR_10FULL 0x0040
|
||||
#define ANAR_10HALF 0x0020
|
||||
#define ANAR_8023BIT 0x0001
|
||||
#define ANLPAR 0x0005
|
||||
#define ANER 0x0006
|
||||
#define AUX_1000_CTRL 0x0009
|
||||
#define ENABLE_1000HALF 0x0100
|
||||
#define ENABLE_1000FULL 0x0200
|
||||
#define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL)
|
||||
#define AUX_1000_STATUS 0x000A
|
||||
#define LP_1000HALF 0x0400
|
||||
#define LP_1000FULL 0x0800
|
||||
|
||||
/* Marvell 88E1111 Gigabit PHY Register Definition */
|
||||
#define M88_SSR 0x0011
|
||||
#define SSR_SPEED_MASK 0xC000
|
||||
#define SSR_SPEED_1000 0x8000
|
||||
#define SSR_SPEED_100 0x4000
|
||||
#define SSR_SPEED_10 0x0000
|
||||
#define SSR_DUPLEX 0x2000
|
||||
#define SSR_MEDIA_RESOLVED_OK 0x0800
|
||||
|
||||
#define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
|
||||
#define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
|
||||
#define SSR_1000HALF SSR_SPEED_1000
|
||||
#define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
|
||||
#define SSR_100HALF SSR_SPEED_100
|
||||
#define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
|
||||
#define SSR_10HALF SSR_SPEED_10
|
||||
#define M88_IER 0x0012
|
||||
#define LINK_CHANGE_INT 0x0400
|
||||
#define M88_ISR 0x0013
|
||||
#define LINK_CHANGE_STATUS 0x0400
|
||||
#define M88_EXT_SCR 0x0014
|
||||
#define RGMII_RXCLK_DELAY 0x0080
|
||||
#define RGMII_TXCLK_DELAY 0x0002
|
||||
#define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
|
||||
#define M88_EXT_SSR 0x001B
|
||||
#define HWCFG_MODE_MASK 0x000F
|
||||
#define RGMII_COPPER_MODE 0x000B
|
||||
|
||||
/* CICADA CIS8201 Gigabit PHY Register Definition */
|
||||
#define CIS_IMR 0x0019
|
||||
#define CIS_INT_ENABLE 0x8000
|
||||
#define CIS_LINK_CHANGE_INT 0x2000
|
||||
#define CIS_ISR 0x001A
|
||||
#define CIS_INT_PENDING 0x8000
|
||||
#define CIS_LINK_CHANGE_STATUS 0x2000
|
||||
#define CIS_AUX_CTRL_STATUS 0x001C
|
||||
#define CIS_AUTONEG_COMPLETE 0x8000
|
||||
#define CIS_SPEED_MASK 0x0018
|
||||
#define CIS_SPEED_1000 0x0010
|
||||
#define CIS_SPEED_100 0x0008
|
||||
#define CIS_SPEED_10 0x0000
|
||||
#define CIS_DUPLEX 0x0020
|
||||
|
||||
#define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
|
||||
#define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
|
||||
#define CIS_1000HALF CIS_SPEED_1000
|
||||
#define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
|
||||
#define CIS_100HALF CIS_SPEED_100
|
||||
#define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
|
||||
#define CIS_10HALF CIS_SPEED_10
|
||||
#define CIS_SMI_PRIORITY 0x0004
|
||||
|
||||
static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
|
||||
{
|
||||
return le16_to_cpu (*(volatile unsigned short *) (addr + dev->iobase));
|
||||
}
|
||||
|
||||
static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
|
||||
{
|
||||
*(volatile unsigned short *) ((addr + dev->iobase)) = cpu_to_le16 (command);
|
||||
}
|
||||
|
||||
/*
|
||||
Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
|
||||
*/
|
||||
#if defined (CONFIG_DRIVER_AX88180_16BIT)
|
||||
static inline unsigned short READ_RXBUF (struct eth_device *dev)
|
||||
{
|
||||
return le16_to_cpu (*(volatile unsigned short *) (RXBUFFER_START + dev->iobase));
|
||||
}
|
||||
|
||||
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
|
||||
{
|
||||
*(volatile unsigned short *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le16 (data);
|
||||
}
|
||||
#else
|
||||
static inline unsigned long READ_RXBUF (struct eth_device *dev)
|
||||
{
|
||||
return le32_to_cpu (*(volatile unsigned long *) (RXBUFFER_START + dev->iobase));
|
||||
}
|
||||
|
||||
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
|
||||
{
|
||||
*(volatile unsigned long *) ((TXBUFFER_START + dev->iobase)) = cpu_to_le32 (data);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _AX88180_H_ */
|
||||
Loading…
Reference in New Issue
Block a user