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arm: Remove IXP425 boards pdnb3 and scpu

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Remove Prodrive pdnb3 board (including the scpu variant) support
from mainline. As its unmaintained and not needed any more for
quite some time.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Martijn de Gouw <martijn.de.gouw@prodrive.nl>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
This commit is contained in:
Stefan Roese
2013-09-24 08:22:19 +02:00
committed by Albert ARIBAUD
parent 262f08d6ea
commit 304db0b38c
7 changed files with 3 additions and 775 deletions
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28
board/prodrive/pdnb3/Makefile
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@@ -1,28 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := flash.o pdnb3.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

73
board/prodrive/pdnb3/flash.c
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@@ -1,73 +0,0 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ixp425.h>
#if !defined(CONFIG_FLASH_CFI_DRIVER)
/*
* include common flash code (for esd boards)
*/
#include "../common/flash.c"
/*
* Prototypes
*/
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
static inline ulong ld(ulong x)
{
ulong k = 0;
while (x >>= 1)
++k;
return k;
}
unsigned long flash_init(void)
{
unsigned long size;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN)
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size, size<<20);
/* Reconfigure CS0 to actual FLASH size */
*IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10);
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
flash_info[0].size = size;
return size;
}
#endif /* CONFIG_FLASH_CFI_DRIVER */

129
board/prodrive/pdnb3/nand.c
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@@ -1,129 +0,0 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#if defined(CONFIG_CMD_NAND)
#include <nand.h>
struct pdnb3_ndfc_regs {
uchar cmd;
uchar wait;
uchar addr;
uchar term;
uchar data;
};
static u8 hwctl;
static struct pdnb3_ndfc_regs *pdnb3_ndfc;
#define readb(addr) *(volatile u_char *)(addr)
#define readl(addr) *(volatile u_long *)(addr)
#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
/*
* The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
* the NAND devices. The NDFC has command, address and data registers that
* when accessed will set up the NAND flash pins appropriately. We'll use the
* hwcontrol function to save the configuration in a global variable.
* We can then use this information in the read and write functions to
* determine which NDFC register to access.
*
* There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
*/
static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
else
hwctl &= ~0x1;
if ( ctrl & NAND_ALE )
hwctl |= 0x2;
else
hwctl &= ~0x2;
if ( (ctrl & NAND_NCE) != NAND_NCE)
writeb(0x00, &(pdnb3_ndfc->term));
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
{
return readb(&(pdnb3_ndfc->data));
}
static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
if (hwctl & 0x1)
writeb(buf[i], &(pdnb3_ndfc->cmd));
else if (hwctl & 0x2)
writeb(buf[i], &(pdnb3_ndfc->addr));
else
writeb(buf[i], &(pdnb3_ndfc->data));
}
}
static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
int i;
for (i = 0; i < len; i++)
buf[i] = readb(&(pdnb3_ndfc->data));
}
static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
for (i = 0; i < len; i++)
if (buf[i] != readb(&(pdnb3_ndfc->data)))
return i;
return 0;
}
static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
{
/*
* Blocking read to wait for NAND to be ready
*/
readb(&(pdnb3_ndfc->wait));
/*
* Return always true
*/
return 1;
}
int board_nand_init(struct nand_chip *nand)
{
pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
nand->ecc.mode = NAND_ECC_SOFT;
/* Set address of NAND IO lines (Using Linear Data Access Region) */
nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
/* Reference hardware control function */
nand->cmd_ctrl = pdnb3_nand_hwcontrol;
nand->read_byte = pdnb3_nand_read_byte;
nand->write_buf = pdnb3_nand_write_buf;
nand->read_buf = pdnb3_nand_read_buf;
nand->verify_buf = pdnb3_nand_verify_buf;
nand->dev_ready = pdnb3_nand_dev_ready;
return 0;
}
#endif

220
board/prodrive/pdnb3/pdnb3.c
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@@ -1,220 +0,0 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <asm/arch/ixp425.h>
DECLARE_GLOBAL_DATA_PTR;
/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
#define OLD_VAL old_val
static unsigned long old_val = 0;
/*
* include common fpga code (for prodrive boards)
*/
#include "../common/fpga.c"
/*
* Miscelaneous platform dependent initialisations
*/
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
/*
* Setup GPIO's for FPGA programming
*/
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
/*
* Setup GPIO's for interrupts
*/
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
/*
* Setup GPIO's for 33MHz clock output
*/
*IXP425_GPIO_GPCLKR = 0x01FF0000;
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
/*
* Setup other chip select's
*/
*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
return 0;
}
/*
* Check Board Identity
*/
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
puts("Board: PDNB3");
if (i > 0) {
puts(", serial# ");
puts(buf);
}
putc('\n');
return (0);
}
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
}
int do_fpga_boot(unsigned char *fpgadata)
{
unsigned char *dst;
int status;
int index;
int i;
ulong len = CONFIG_SYS_MALLOC_LEN;
/*
* Setup GPIO's for FPGA programming
*/
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
/*
* Save value so no readback is required upon programming
*/
old_val = *IXP425_GPIO_GPOUTR;
/*
* First try to decompress fpga image (gzip compressed?)
*/
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf("Error: Image has to be gzipp'ed!\n");
return -1;
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len+3;
}
putc ('\n');
/* delayed reboot */
for (i=5; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
udelay(1000);
}
putc('\n');
do_reset(NULL, 0, 0, NULL);
}
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("%s ", &(dst[index+1]));
index += len+3;
}
putc('\n');
free(dst);
/*
* Reset FPGA
*/
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
udelay(10);
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
return (0);
}
int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong addr;
if (argc < 2)
return cmd_usage(cmdtp);
addr = simple_strtoul(argv[1], NULL, 16);
return do_fpga_boot((unsigned char *)addr);
}
U_BOOT_CMD(
fpga, 2, 0, do_fpga,
"boot FPGA",
"address size\n - boot FPGA with gzipped image at <address>"
);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
extern struct pci_controller hose;
extern void pci_ixp_init(struct pci_controller * hose);
void pci_init_board(void)
{
extern void pci_ixp_init (struct pci_controller *hose);
pci_ixp_init(&hose);
}
#endif