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net: tsec: Remove non-DM_ETH support code

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As DM_ETH is required for all network drivers, it's now safe to remove
the non-DM_ETH support code.  Doing this removes some board support code
which was also unused. Finally, this removes some CONFIG symbols that
otherwise needed to be migrated to Kconfig, but were unused in code now.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-11-27 10:25:04 -05:00
parent 8457d023b8
commit 2f420f135f
17 changed files with 1 additions and 710 deletions
Download Patch File Download Diff File Expand all files Collapse all files

73
board/freescale/common/pixis.c
View File

@@ -281,79 +281,6 @@ U_BOOT_CMD(
""
);
#ifdef CONFIG_PIXIS_SGMII_CMD
/* Enable or disable SGMII mode for a TSEC
*/
static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int which_tsec = -1;
unsigned char mask;
unsigned char switch_mask;
if ((argc > 2) && (strcmp(argv[1], "all") != 0))
which_tsec = simple_strtoul(argv[1], NULL, 0);
switch (which_tsec) {
#ifdef CONFIG_TSEC1
case 1:
mask = PIXIS_VSPEED2_TSEC1SER;
switch_mask = PIXIS_VCFGEN1_TSEC1SER;
break;
#endif
#ifdef CONFIG_TSEC2
case 2:
mask = PIXIS_VSPEED2_TSEC2SER;
switch_mask = PIXIS_VCFGEN1_TSEC2SER;
break;
#endif
#ifdef CONFIG_TSEC3
case 3:
mask = PIXIS_VSPEED2_TSEC3SER;
switch_mask = PIXIS_VCFGEN1_TSEC3SER;
break;
#endif
#ifdef CONFIG_TSEC4
case 4:
mask = PIXIS_VSPEED2_TSEC4SER;
switch_mask = PIXIS_VCFGEN1_TSEC4SER;
break;
#endif
default:
mask = PIXIS_VSPEED2_MASK;
switch_mask = PIXIS_VCFGEN1_MASK;
break;
}
/* Toggle whether the switches or FPGA control the settings */
if (!strcmp(argv[argc - 1], "switch"))
clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
else
setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
/* If it's not the switches, enable or disable SGMII, as specified */
if (!strcmp(argv[argc - 1], "on"))
clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
else if (!strcmp(argv[argc - 1], "off"))
setbits_8(pixis_base + PIXIS_VSPEED2, mask);
return 0;
}
U_BOOT_CMD(
pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
"pixis_set_sgmii"
" - Enable or disable SGMII mode for a given TSEC \n",
"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
" TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
" on - enables SGMII\n"
" off - disables SGMII\n"
" switch - use switch settings"
);
#endif
/*
* This function takes the non-integral cpu:mpx pll ratio
* and converts it to an integer that can be used to assign

82
board/freescale/mpc8548cds/mpc8548cds.c
View File

@@ -168,85 +168,3 @@ void lbc_sdram_init(void)
#endif /* enable SDRAM init */
}
#ifndef CONFIG_DM_ETH
static void configure_rgmii(void)
{
unsigned short temp;
/* Change the resistors for the PHY */
/* This is needed to get the RGMII working for the 1.3+
* CDS cards */
if (get_board_version() == 0x13) {
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 18);
miiphy_read(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f);
temp |= 2 << 9; /* 36 ohm */
temp |= 2 << 6; /* 39 ohm */
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, temp);
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 3);
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, 0x8000);
}
return;
}
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
#ifdef CONFIG_TSEC3
/* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
if (get_board_version() >= 0x13) {
SET_STD_TSEC_INFO(tsec_info[num], 3);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
}
#endif
#ifdef CONFIG_TSEC4
/* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
if (get_board_version() >= 0x13) {
SET_STD_TSEC_INFO(tsec_info[num], 4);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
}
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
configure_rgmii();
#endif
return pci_eth_init(bis);
}
#endif

43
board/freescale/p1010rdb/p1010rdb.c
View File

@@ -478,49 +478,6 @@ int checkboard(void)
return 0;
}
#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
struct cpu_type *cpu;
int num = 0;
cpu = gd->arch.cpu;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
#ifdef CONFIG_TSEC3
/* P1014 and it's derivatives do not support eTSEC3 */
if (cpu->soc_ver != SVR_P1014) {
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
}
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
{

50
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@@ -364,56 +364,6 @@ int board_early_init_r(void)
return 0;
}
#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
printf("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#if defined(CONFIG_UEC_ETH)
/* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
uec_standard_init(bis);
#endif
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP)
static void fix_max6370_watchdog(void *blob)
{