diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 6413a307d2..14f86df5ed 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -36,11 +36,6 @@
 
 #define CFG_SYS_FSL_SEC_OFFSET		0x00700000
 #define CFG_SYS_FSL_JR0_OFFSET		0x00710000
-#define CFG_SYS_TSEC1_OFFSET			0x01d10000
-#define CFG_SYS_MDIO1_OFFSET			0x01d24000
-
-#define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 
 #define SCTR_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01b00000)
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d9e5a7d621..1b5b4947f1 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -24,18 +24,9 @@
 
 #elif defined(CONFIG_ARCH_P1010)
 #define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 
-/* P1011 is single core version of P1020 */
-#elif defined(CONFIG_ARCH_P1011)
-#define CONFIG_TSECV2
-
-#elif defined(CONFIG_ARCH_P1020)
-#define CONFIG_TSECV2
-
 #elif defined(CONFIG_ARCH_P1021)
-#define CONFIG_TSECV2
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
@@ -47,13 +38,8 @@
 #define CFG_SYS_BMAN_NUM_PORTALS	3
 #define CFG_SYS_FM_MURAM_SIZE	0x10000
 
-/* P1024 is lower end variant of P1020 */
-#elif defined(CONFIG_ARCH_P1024)
-#define CONFIG_TSECV2
-
 /* P1025 is lower end variant of P1021 */
 #elif defined(CONFIG_ARCH_P1025)
-#define CONFIG_TSECV2
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
@@ -108,12 +94,10 @@
 
 #elif defined(CONFIG_ARCH_BSC9131)
 #define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_BSC9132)
 #define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_T4240)
@@ -221,7 +205,6 @@
 
 #elif defined(CONFIG_ARCH_C29X)
 #define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_TSECV2_1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 19774f3053..24bd438c14 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -873,9 +873,4 @@ struct ccsr_gpio {
 
 #define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
 
-#define CFG_SYS_TSEC1_OFFSET		0x24000
-#define CFG_SYS_MDIO1_OFFSET		0x24000
-
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 #endif				/* __IMMAP_83xx__ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 283fdf3b45..7293720fb3 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2541,13 +2541,6 @@ struct ccsr_pman {
 #define CFG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
-#ifdef CONFIG_TSECV2
-#define CFG_SYS_TSEC1_OFFSET			0xB0000
-#elif defined(CONFIG_TSECV2_1)
-#define CFG_SYS_TSEC1_OFFSET			0x10000
-#else
-#define CFG_SYS_TSEC1_OFFSET			0x24000
-#endif
 #define CFG_SYS_MDIO1_OFFSET			0x24000
 #define CFG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
@@ -2673,7 +2666,6 @@ struct ccsr_pman {
 #define CFG_SYS_SEC_MON_ADDR  \
 	(CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET)
 
-#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index 6fdb11039e..cb9f454972 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -281,79 +281,6 @@ U_BOOT_CMD(
 	""
 );
 
-#ifdef CONFIG_PIXIS_SGMII_CMD
-
-/* Enable or disable SGMII mode for a TSEC
- */
-static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc,
-			   char *const argv[])
-{
-	int which_tsec = -1;
-	unsigned char mask;
-	unsigned char switch_mask;
-
-	if ((argc > 2) && (strcmp(argv[1], "all") != 0))
-		which_tsec = simple_strtoul(argv[1], NULL, 0);
-
-	switch (which_tsec) {
-#ifdef CONFIG_TSEC1
-	case 1:
-		mask = PIXIS_VSPEED2_TSEC1SER;
-		switch_mask = PIXIS_VCFGEN1_TSEC1SER;
-		break;
-#endif
-#ifdef CONFIG_TSEC2
-	case 2:
-		mask = PIXIS_VSPEED2_TSEC2SER;
-		switch_mask = PIXIS_VCFGEN1_TSEC2SER;
-		break;
-#endif
-#ifdef CONFIG_TSEC3
-	case 3:
-		mask = PIXIS_VSPEED2_TSEC3SER;
-		switch_mask = PIXIS_VCFGEN1_TSEC3SER;
-		break;
-#endif
-#ifdef CONFIG_TSEC4
-	case 4:
-		mask = PIXIS_VSPEED2_TSEC4SER;
-		switch_mask = PIXIS_VCFGEN1_TSEC4SER;
-		break;
-#endif
-	default:
-		mask = PIXIS_VSPEED2_MASK;
-		switch_mask = PIXIS_VCFGEN1_MASK;
-		break;
-	}
-
-	/* Toggle whether the switches or FPGA control the settings */
-	if (!strcmp(argv[argc - 1], "switch"))
-		clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
-	else
-		setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
-
-	/* If it's not the switches, enable or disable SGMII, as specified */
-	if (!strcmp(argv[argc - 1], "on"))
-		clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
-	else if (!strcmp(argv[argc - 1], "off"))
-		setbits_8(pixis_base + PIXIS_VSPEED2, mask);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
-	"pixis_set_sgmii"
-	" - Enable or disable SGMII mode for a given TSEC \n",
-	"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
-	"    TSEC num: 1,2,3,4 or 'all'.  'all' is default.\n"
-	"    on - enables SGMII\n"
-	"    off - disables SGMII\n"
-	"    switch - use switch settings"
-);
-
-#endif
-
 /*
  * This function takes the non-integral cpu:mpx pll ratio
  * and converts it to an integer that can be used to assign
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 73e024eaa0..ec6e3a2d0a 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -168,85 +168,3 @@ void lbc_sdram_init(void)
 
 #endif	/* enable SDRAM init */
 }
-
-#ifndef CONFIG_DM_ETH
-static void configure_rgmii(void)
-{
-	unsigned short temp;
-
-	/* Change the resistors for the PHY */
-	/* This is needed to get the RGMII working for the 1.3+
-	 * CDS cards */
-	if (get_board_version() ==  0x13) {
-		miiphy_write(DEFAULT_MII_NAME,
-				TSEC1_PHY_ADDR, 29, 18);
-
-		miiphy_read(DEFAULT_MII_NAME,
-				TSEC1_PHY_ADDR, 30, &temp);
-
-		temp = (temp & 0xf03f);
-		temp |= 2 << 9;		/* 36 ohm */
-		temp |= 2 << 6;		/* 39 ohm */
-
-		miiphy_write(DEFAULT_MII_NAME,
-				TSEC1_PHY_ADDR, 30, temp);
-
-		miiphy_write(DEFAULT_MII_NAME,
-				TSEC1_PHY_ADDR, 29, 3);
-
-		miiphy_write(DEFAULT_MII_NAME,
-				TSEC1_PHY_ADDR, 30, 0x8000);
-	}
-
-	return;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[4];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	/* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
-	if (get_board_version() >= 0x13) {
-		SET_STD_TSEC_INFO(tsec_info[num], 3);
-		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
-		num++;
-	}
-#endif
-#ifdef CONFIG_TSEC4
-	/* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
-	if (get_board_version() >= 0x13) {
-		SET_STD_TSEC_INFO(tsec_info[num], 4);
-		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
-		num++;
-	}
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-
-		return 0;
-	}
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-	configure_rgmii();
-#endif
-
-	return pci_eth_init(bis);
-}
-#endif
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 0f014823c9..d32274b248 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -478,49 +478,6 @@ int checkboard(void)
 	return 0;
 }
 
-#ifndef CONFIG_DM_ETH
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[4];
-	struct cpu_type *cpu;
-	int num = 0;
-
-	cpu = gd->arch.cpu;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	/* P1014 and it's derivatives do not support eTSEC3 */
-	if (cpu->soc_ver != SVR_P1014) {
-		SET_STD_TSEC_INFO(tsec_info[num], 3);
-		num++;
-	}
-#endif
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-
-	return pci_eth_init(bis);
-}
-#endif
-
 #if defined(CONFIG_OF_BOARD_SETUP)
 void fdt_del_flexcan(void *blob)
 {
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index ab79724429..df9f6ae473 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -364,56 +364,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-#ifndef CONFIG_DM_ETH
-int board_eth_init(struct bd_info *bis)
-{
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[4];
-	ccsr_gur_t *gur __attribute__((unused)) =
-		(void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	num++;
-#endif
-#ifdef CONFIG_TSEC2
-	SET_STD_TSEC_INFO(tsec_info[num], 2);
-	if (is_serdes_configured(SGMII_TSEC2)) {
-		printf("eTSEC2 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	num++;
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-		return 0;
-	}
-
-	mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
-	mdio_info.name = DEFAULT_MII_NAME;
-
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-
-#if defined(CONFIG_UEC_ETH)
-	/*  QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
-	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
-
-	uec_standard_init(bis);
-#endif
-
-	return pci_eth_init(bis);
-}
-#endif
-
 #if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP)
 static void fix_max6370_watchdog(void *blob)
 {
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 8b6f034ea1..f465409d8c 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -22,34 +22,6 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 
-#ifndef CONFIG_DM_ETH
-/* Default initializations for TSEC controllers. */
-
-static struct tsec_info_struct tsec_info[] = {
-#ifdef CONFIG_TSEC1
-	STD_TSEC_INFO(1),	/* TSEC1 */
-#endif
-#ifdef CONFIG_TSEC2
-	STD_TSEC_INFO(2),	/* TSEC2 */
-#endif
-#ifdef CONFIG_MPC85XX_FEC
-	{
-		.regs = TSEC_GET_REGS(2, 0x2000),
-		.devname = CONFIG_MPC85XX_FEC_NAME,
-		.phyaddr = FEC_PHY_ADDR,
-		.flags = FEC_FLAGS,
-		.mii_devname = DEFAULT_MII_NAME
-	},			/* FEC */
-#endif
-#ifdef CONFIG_TSEC3
-	STD_TSEC_INFO(3),	/* TSEC3 */
-#endif
-#ifdef CONFIG_TSEC4
-	STD_TSEC_INFO(4),	/* TSEC4 */
-#endif
-};
-#endif /* CONFIG_DM_ETH */
-
 #define TBIANA_SETTINGS ( \
 		TBIANA_ASYMMETRIC_PAUSE \
 		| TBIANA_SYMMETRIC_PAUSE \
@@ -124,23 +96,14 @@ static u32 ether_crc(size_t len, unsigned char const *p)
  * for PowerPC (tm) is usually the case) in the register holds
  * the entry.
  */
-#ifndef CONFIG_DM_ETH
-static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
-			   int join)
-#else
 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
-#endif
 {
 	struct tsec_private *priv;
 	struct tsec __iomem *regs;
 	u32 result, value;
 	u8 whichbit, whichreg;
 
-#ifndef CONFIG_DM_ETH
-	priv = (struct tsec_private *)dev->priv;
-#else
 	priv = dev_get_priv(dev);
-#endif
 	regs = priv->regs;
 	result = ether_crc(MAC_ADDR_LEN, mcast_mac);
 	whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
@@ -271,11 +234,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
  * do the same. Presumably, this would be zero if there were no
  * errors
  */
-#ifndef CONFIG_DM_ETH
-static int tsec_send(struct eth_device *dev, void *packet, int length)
-#else
 static int tsec_send(struct udevice *dev, void *packet, int length)
-#endif
 {
 	struct tsec_private *priv;
 	struct tsec __iomem *regs;
@@ -283,11 +242,7 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
 	u16 status;
 	int i;
 
-#ifndef CONFIG_DM_ETH
-	priv = (struct tsec_private *)dev->priv;
-#else
 	priv = dev_get_priv(dev);
-#endif
 	regs = priv->regs;
 	/* Find an empty buffer descriptor */
 	for (i = 0;
@@ -324,42 +279,6 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
 	return result;
 }
 
-#ifndef CONFIG_DM_ETH
-static int tsec_recv(struct eth_device *dev)
-{
-	struct tsec_private *priv = (struct tsec_private *)dev->priv;
-	struct tsec __iomem *regs = priv->regs;
-
-	while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
-		int length = in_be16(&priv->rxbd[priv->rx_idx].length);
-		u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
-		uchar *packet = net_rx_packets[priv->rx_idx];
-
-		/* Send the packet up if there were no errors */
-		if (!(status & RXBD_STATS))
-			net_process_received_packet(packet, length - 4);
-		else
-			printf("Got error %x\n", (status & RXBD_STATS));
-
-		out_be16(&priv->rxbd[priv->rx_idx].length, 0);
-
-		status = RXBD_EMPTY;
-		/* Set the wrap bit if this is the last element in the list */
-		if ((priv->rx_idx + 1) == PKTBUFSRX)
-			status |= RXBD_WRAP;
-		out_be16(&priv->rxbd[priv->rx_idx].status, status);
-
-		priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
-	}
-
-	if (in_be32(&regs->ievent) & IEVENT_BSY) {
-		out_be32(&regs->ievent, IEVENT_BSY);
-		out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
-	}
-
-	return -1;
-}
-#else
 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
 {
 	struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
@@ -406,22 +325,12 @@ static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
 
 	return 0;
 }
-#endif
 
-/* Stop the interface */
-#ifndef CONFIG_DM_ETH
-static void tsec_halt(struct eth_device *dev)
-#else
 static void tsec_halt(struct udevice *dev)
-#endif
 {
 	struct tsec_private *priv;
 	struct tsec __iomem *regs;
-#ifndef CONFIG_DM_ETH
-	priv = (struct tsec_private *)dev->priv;
-#else
 	priv = dev_get_priv(dev);
-#endif
 	regs = priv->regs;
 
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
@@ -583,27 +492,15 @@ static void startup_tsec(struct tsec_private *priv)
  * that it returns success if the link is up, failure otherwise.
  * This allows U-Boot to find the first active controller.
  */
-#ifndef CONFIG_DM_ETH
-static int tsec_init(struct eth_device *dev, struct bd_info *bd)
-#else
 static int tsec_init(struct udevice *dev)
-#endif
 {
 	struct tsec_private *priv;
 	struct tsec __iomem *regs;
-#ifdef CONFIG_DM_ETH
 	struct eth_pdata *pdata = dev_get_plat(dev);
-#else
-	struct eth_device *pdata = dev;
-#endif
 	u32 tempval;
 	int ret;
 
-#ifndef CONFIG_DM_ETH
-	priv = (struct tsec_private *)dev->priv;
-#else
 	priv = dev_get_priv(dev);
-#endif
 	regs = priv->regs;
 	/* Make sure the controller is stopped */
 	tsec_halt(dev);
@@ -715,7 +612,7 @@ static int init_phy(struct tsec_private *priv)
 	if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 		tsec_configure_serdes(priv);
 
-#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
+#if defined(CONFIG_DM_MDIO)
 	phydev = dm_eth_phy_connect(priv->dev);
 #else
 	phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
@@ -734,99 +631,6 @@ static int init_phy(struct tsec_private *priv)
 	return 1;
 }
 
-#ifndef CONFIG_DM_ETH
-/*
- * Initialize device structure. Returns success if PHY
- * initialization succeeded (i.e. if it recognizes the PHY)
- */
-static int tsec_initialize(struct bd_info *bis,
-			   struct tsec_info_struct *tsec_info)
-{
-	struct tsec_private *priv;
-	struct eth_device *dev;
-	int i;
-
-	dev = (struct eth_device *)malloc(sizeof(*dev));
-
-	if (!dev)
-		return 0;
-
-	memset(dev, 0, sizeof(*dev));
-
-	priv = (struct tsec_private *)malloc(sizeof(*priv));
-
-	if (!priv) {
-		free(dev);
-		return 0;
-	}
-
-	priv->regs = tsec_info->regs;
-	priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
-
-	priv->phyaddr = tsec_info->phyaddr;
-	priv->tbiaddr = CFG_SYS_TBIPA_VALUE;
-	priv->flags = tsec_info->flags;
-
-	strcpy(dev->name, tsec_info->devname);
-	priv->interface = tsec_info->interface;
-	priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
-	priv->dev = dev;
-	dev->iobase = 0;
-	dev->priv = priv;
-	dev->init = tsec_init;
-	dev->halt = tsec_halt;
-	dev->send = tsec_send;
-	dev->recv = tsec_recv;
-	dev->mcast = tsec_mcast_addr;
-
-	/* Tell U-Boot to get the addr from the env */
-	for (i = 0; i < 6; i++)
-		dev->enetaddr[i] = 0;
-
-	eth_register(dev);
-
-	/* Reset the MAC */
-	setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
-	udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
-	clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
-
-	/* Try to initialize PHY here, and return */
-	return init_phy(priv);
-}
-
-/*
- * Initialize all the TSEC devices
- *
- * Returns the number of TSEC devices that were initialized
- */
-int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
-		  int num)
-{
-	int i;
-	int count = 0;
-
-	for (i = 0; i < num; i++) {
-		int ret = tsec_initialize(bis, &tsecs[i]);
-
-		if (ret > 0)
-			count += ret;
-	}
-
-	return count;
-}
-
-int tsec_standard_init(struct bd_info *bis)
-{
-	struct fsl_pq_mdio_info info;
-
-	info.regs = TSEC_GET_MDIO_REGS_BASE(1);
-	info.name = DEFAULT_MII_NAME;
-
-	fsl_pq_mdio_init(bis, &info);
-
-	return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
-}
-#else /* CONFIG_DM_ETH */
 int tsec_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
@@ -966,4 +770,3 @@ U_BOOT_DRIVER(eth_tsec) = {
 	.plat_auto	= sizeof(struct eth_pdata),
 	.flags = DM_FLAG_ALLOC_PRIV_DMA,
 };
-#endif /* CONFIG_DM_ETH */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 95a90199a4..f312ffb37e 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -41,8 +41,6 @@
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CONFIG_TSEC2
-
 /* The flash address and size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
@@ -178,31 +176,6 @@
 #define CFG_SYS_PCIE2_MEM_PHYS	0xC8000000
 #define CFG_SYS_PCIE2_IO_PHYS	0xD8000000
 
-/*
- * TSEC
- */
-#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_GMII			/* MII PHY management */
-
-#define CONFIG_TSEC1
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME		"TSEC0"
-#define CFG_SYS_TSEC1_OFFSET		0x24000
-#define TSEC1_PHY_ADDR			2
-#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC1_PHYIDX			0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME		"TSEC1"
-#define TSEC2_PHY_ADDR			0x1c
-#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_PHYIDX			0
-#endif
-#endif
-
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC83xx_ESDHC_ADDR
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 780ee5ae86..34b876f829 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -283,33 +283,6 @@
 #endif
 #define CFG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"eTSEC0"
-#define CONFIG_TSEC2	1
-#define CONFIG_TSEC2_NAME	"eTSEC1"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC2"
-#define CONFIG_TSEC4
-#define CONFIG_TSEC4_NAME	"eTSEC3"
-#undef CONFIG_MPC85XX_FEC
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC2_PHY_ADDR		1
-#define TSEC3_PHY_ADDR		2
-#define TSEC4_PHY_ADDR		3
-
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC2_FLAGS		TSEC_GIGABIT
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#endif	/* CONFIG_TSEC_ENET */
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index b1d6b15811..4418d51695 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -349,37 +349,6 @@ extern unsigned long get_sdram_size(void);
 /* eSPI - Enhanced SPI */
 #endif
 
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC2	1
-#define CONFIG_TSEC2_NAME	"eTSEC2"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-
-#define TSEC1_PHY_ADDR		1
-#define TSEC2_PHY_ADDR		0
-#define TSEC3_PHY_ADDR		2
-
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC3_PHYIDX		0
-
-/* TBI PHY configuration for SGMII mode */
-#define CONFIG_TSEC_TBICR_SETTINGS ( \
-		TBICR_PHY_RESET \
-		| TBICR_ANEG_ENABLE \
-		| TBICR_FULL_DUPLEX \
-		| TBICR_SPEED1_SET \
-		)
-
-#endif	/* CONFIG_TSEC_ENET */
-
 #ifdef CONFIG_MMC
 #define CFG_SYS_FSL_ESDHC_ADDR	CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 024a718527..179c5128e3 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -66,27 +66,6 @@
 
 /* SPI */
 
-/*
- * eTSEC
- */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_MII_DEFAULT_TSEC		1
-#define CONFIG_TSEC1			1
-#define CONFIG_TSEC1_NAME		"eTSEC1"
-#define CONFIG_TSEC2			1
-#define CONFIG_TSEC2_NAME		"eTSEC2"
-
-#define TSEC1_PHY_ADDR			1
-#define TSEC2_PHY_ADDR			3
-
-#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
-#endif
-
 #define FSL_PCIE_COMPAT		"fsl,ls1021a-pcie"
 
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5a91cc3efe..d6681e8598 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -247,32 +247,6 @@
  * MMC
  */
 
-/*
- * eTSEC
- */
-
-#ifdef CONFIG_TSEC_ENET
-#define CONFIG_MII_DEFAULT_TSEC		3
-#define CONFIG_TSEC1			1
-#define CONFIG_TSEC1_NAME		"eTSEC1"
-#define CONFIG_TSEC2			1
-#define CONFIG_TSEC2_NAME		"eTSEC2"
-#define CONFIG_TSEC3			1
-#define CONFIG_TSEC3_NAME		"eTSEC3"
-
-#define TSEC1_PHY_ADDR			1
-#define TSEC2_PHY_ADDR			2
-#define TSEC3_PHY_ADDR			3
-
-#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
-#define TSEC3_PHYIDX			0
-#endif
-
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 9738e9fa9c..49c5aef305 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -366,27 +366,6 @@
 #endif
 #endif /* CONFIG_PCI */
 
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC2
-#define CONFIG_TSEC2_NAME	"eTSEC2"
-#define CONFIG_TSEC3
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-
-#define TSEC1_PHY_ADDR	2
-#define TSEC2_PHY_ADDR	0
-#define TSEC3_PHY_ADDR	1
-
-#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX	0
-#define TSEC2_PHYIDX	0
-#define TSEC3_PHYIDX	0
-#endif /* CONFIG_TSEC_ENET */
-
 /*
  * Environment
  */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 95393d3ab2..2a07671602 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -111,22 +111,6 @@
 #define CFG_SYS_PCI1_MEM_PHYS	0x80000000
 #define CFG_SYS_PCI1_IO_PHYS	0xE2000000
 
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"TSEC1"
-#undef CONFIG_MPC85XX_FEC
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC3_PHY_ADDR		1
-
-#define TSEC1_PHYIDX		0
-#define TSEC3_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC3_FLAGS		TSEC_GIGABIT
-
-/* Options are: TSEC[0,1] */
-
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/tsec.h b/include/tsec.h
index de279b2117..153337837a 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -19,56 +19,6 @@
 
 #define TSEC_MDIO_REGS_OFFSET	0x520
 
-#ifndef CONFIG_DM_ETH
-
-#ifdef CONFIG_ARCH_LS1021A
-#define TSEC_SIZE		0x40000
-#define TSEC_MDIO_OFFSET	0x40000
-#else
-#define TSEC_SIZE		0x01000
-#define TSEC_MDIO_OFFSET	0x01000
-#endif
-
-#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
-
-#define TSEC_GET_REGS(num, offset) \
-	(struct tsec __iomem *)\
-	(TSEC_BASE_ADDR + (((num) - 1) * (offset)))
-
-#define TSEC_GET_REGS_BASE(num) \
-	TSEC_GET_REGS((num), TSEC_SIZE)
-
-#define TSEC_GET_MDIO_REGS(num, offset) \
-	(struct tsec_mii_mng __iomem *)\
-	(CONFIG_SYS_MDIO_BASE_ADDR  + ((num) - 1) * (offset))
-
-#define TSEC_GET_MDIO_REGS_BASE(num) \
-	TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
-
-#define DEFAULT_MII_NAME "FSL_MDIO"
-
-#define STD_TSEC_INFO(num) \
-{			\
-	.regs = TSEC_GET_REGS_BASE(num), \
-	.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
-	.devname = CONFIG_TSEC##num##_NAME, \
-	.phyaddr = TSEC##num##_PHY_ADDR, \
-	.flags = TSEC##num##_FLAGS, \
-	.mii_devname = DEFAULT_MII_NAME \
-}
-
-#define SET_STD_TSEC_INFO(x, num) \
-{			\
-	x.regs = TSEC_GET_REGS_BASE(num); \
-	x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
-	x.devname = CONFIG_TSEC##num##_NAME; \
-	x.phyaddr = TSEC##num##_PHY_ADDR; \
-	x.flags = TSEC##num##_FLAGS;\
-	x.mii_devname = DEFAULT_MII_NAME;\
-}
-
-#endif /* CONFIG_DM_ETH */
-
 #define MAC_ADDR_LEN		6
 
 /* #define TSEC_TIMEOUT	1000000 */
@@ -414,11 +364,7 @@ struct tsec_private {
 	u32 flags;
 	uint rx_idx;	/* index of the current RX buffer */
 	uint tx_idx;	/* index of the current TX buffer */
-#ifndef CONFIG_DM_ETH
-	struct eth_device *dev;
-#else
 	struct udevice *dev;
-#endif
 };
 
 struct tsec_info_struct {
@@ -431,10 +377,4 @@ struct tsec_info_struct {
 	u32 flags;
 };
 
-#ifndef CONFIG_DM_ETH
-int tsec_standard_init(struct bd_info *bis);
-int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsec_info,
-		  int num);
-#endif
-
 #endif /* __TSEC_H */